Pump Questa Version to 10.6

Makefile

@@ -51,8 +51,8 @@ incdir = ./includes
 # Test case to run
 test_case = core_test
 # QuestaSim Version
-questa_version = -10.5c
-compile_flag = +cover=bcfst+/dut -incr -64 -nologo -quiet
+questa_version = -10.6
+compile_flag = +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262
 # Moore binary
 moore = ~fschuiki/bin/moore
 # Iterate over all include directories and write them with +incdir+ prefixed
@@ -77,7 +77,7 @@ $(library)/.build-srcs: $(util) $(src)
 # build TBs
 $(library)/.build-tb: $(dpi) $(tbs)
 	# Compile top level with DPI headers
-	vlog -sv $(tbs) -work $(library) $(filter %.c %.cc, $(dpi)) -ccflags "-g -std=c++11 " -dpiheader tb/dpi/elfdpi.h
+	vlog$(questa_version) -sv $(tbs) -work $(library) $(filter %.c %.cc, $(dpi)) -ccflags "-g -std=c++11 " -dpiheader tb/dpi/elfdpi.h
 	touch $(library)/.build-tb
 
 
@@ -136,3 +136,5 @@ clean:
 
 .PHONY:
 	build lint build-moore
+
+	# make CC=/usr/pack/modelsim-10.6-kgf/questasim/gcc-5.3.0-linux_x86_64/bin/gcc CXX=/usr/pack/modelsim-10.6-kgf/questasim/gcc-5.3.0-linux_x86_64/bin/g++ -j20

src/fetch_fifo.sv

@@ -52,10 +52,10 @@ module fetch_fifo
     logic [31:0] decompressed_instruction [2];
     logic        is_illegal [2];
 
-    fetch_entry mem_n[DEPTH-1:0], mem_q[DEPTH-1:0];
-    logic [$clog2(DEPTH)-1:0]     read_pointer_n, read_pointer_q;
-    logic [$clog2(DEPTH)-1:0]     write_pointer_n, write_pointer_q;
-    logic [$clog2(DEPTH)-1:0]     status_cnt_n,    status_cnt_q; // this integer will be truncated by the synthesis tool
+    fetch_entry                   mem_n[DEPTH-1:0], mem_q[DEPTH-1:0];
+    logic [$clog2(DEPTH)-1:0]     read_pointer_n,   read_pointer_q;
+    logic [$clog2(DEPTH)-1:0]     write_pointer_n,  write_pointer_q;
+    logic [$clog2(DEPTH)-1:0]     status_cnt_n,     status_cnt_q; // this integer will be truncated by the synthesis tool
 
     // status signals
     logic full, empty;

src/lsu.sv

@@ -421,7 +421,7 @@ module lsu #(
                 end
                 // word
                 LW, LWU, SW: begin
-                    if (vaddr_i[1:0] != 1'b00)
+                    if (vaddr_i[1:0] != 2'b00)
                         data_misaligned = 1'b1;
                 end
 
@@ -455,7 +455,7 @@ module lsu #(
     end
 
     // this process selects the input based on the current state of the LSU
-    // it can either be feedthrough from the issue stage or from the internal register
+    // it can either be feed-through from the issue stage or from the internal registers
     always_comb begin : input_select
         // if we are stalling use the values we saved
         if (stall_q) begin

src/util/instruction_trace_item.svh

@@ -185,13 +185,13 @@ class instruction_trace_item;
 
         foreach (result_regs[i]) begin
             if (result_regs[i] != 0)
-                s = $sformatf(s, " %-4s:%16x", regAddrToStr(result_regs[i]), this.result);
+                s = $sformatf("%s %-4s:%16x", s, regAddrToStr(result_regs[i]), this.result);
         end
 
 
         foreach (read_regs[i]) begin
             if (read_regs[i] != 0)
-                s = $sformatf(s, " %-4s:%16x", regAddrToStr(read_regs[i]), reg_file[read_regs[i]]);
+                s = $sformatf("%s %-4s:%16x", s, regAddrToStr(read_regs[i]), reg_file[read_regs[i]]);
         end
 
         return s;

tb/core_tb.sv

@@ -152,8 +152,9 @@ module core_tb;
         string plus_args [$];
         longint unsigned address;
         string file;
+        string test;
         // offset the temporary RAM
-        logic [7:0] rmem [`DRAM_BASE + 0:`DRAM_BASE + 16384];
+        logic [7:0] rmem [`DRAM_BASE:`DRAM_BASE + 16384];
         // get the file name from a command line plus arg
         void'(uvcl.get_arg_value("+ASMTEST=",file));
 
@@ -162,7 +163,6 @@ module core_tb;
         void'(read_elf(file));
         // we are interested in the .tohost ELF symbol in-order to observe end of test signals
         address = get_symbol_address("tohost");
-        $display("tohost address: %0h\n", address);
         // get the objdump verilog file to load our memorys
         $readmemh({file, ".v"}, rmem);
         // copy bitwise from verilog file

tb/dpi/elfdpi.h

@@ -1,7 +1,7 @@
 /* MTI_DPI */
 
 /*
- * Copyright 2002-2016 Mentor Graphics Corporation.
+ * Copyright 2002-2017 Mentor Graphics Corporation.
  *
  * Note:
  *   This file is automatically generated.