mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-20 04:07:36 -04:00
[HOTFIX] Delete vendor/patches/riscv/riscv-isa-sim directory (#1545)
Spike has been moved from CVA6 to Core-v-verif repository except the patches. Clean-up to avoid redundancy between repositories.
This commit is contained in:
JeanRochCoulon
GitHub
parent
3e72504d97
commit
d29021ea22
7 changed files with 0 additions and 782 deletions
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@ -1,12 +0,0 @@
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diff --git a/fesvr/fesvr.mk.in b/fesvr/fesvr.mk.in
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index 695de5278..43aed6786 100644
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--- a/fesvr/fesvr.mk.in
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+++ b/fesvr/fesvr.mk.in
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@@ -20,6 +20,7 @@ fesvr_install_hdrs = $(fesvr_hdrs)
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fesvr_install_config_hdr = yes
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fesvr_install_lib = yes
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+fesvr_install_shared_lib = yes
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fesvr_srcs = \
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elfloader.cc \
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@ -1,15 +0,0 @@
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diff --git a/riscv/extensions.cc b/riscv/extensions.cc
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index 347dc5e91..b488aad15 100644
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--- a/riscv/extensions.cc
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+++ b/riscv/extensions.cc
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@@ -27,8 +27,8 @@ std::function<extension_t*()> find_extension(const char* name)
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if (!dlh) {
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dlh = dlopen(libdefault.c_str(), RTLD_LAZY);
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if (!dlh) {
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- fprintf(stderr, "couldn't find shared library either '%s' or '%s')\n",
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- libname.c_str(), libdefault.c_str());
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+ fprintf(stderr, "couldn't load shared library (either '%s' or '%s'), reason: %s\n",
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+ libname.c_str(), libdefault.c_str(), dlerror());
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exit(-1);
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}
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@ -1,533 +0,0 @@
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diff --git a/customext/customext.mk.in b/customext/customext.mk.in
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index a14e771c2..888634b46 100644
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--- a/customext/customext.mk.in
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+++ b/customext/customext.mk.in
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@@ -7,5 +7,6 @@ customext_subproject_deps = \
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customext_srcs = \
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dummy_rocc.cc \
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cflush.cc \
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+ cvxif.cc \
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customext_install_shared_lib = yes
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diff --git a/customext/cvxif.cc b/customext/cvxif.cc
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new file mode 100644
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index 000000000..dd1a7329a
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--- /dev/null
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+++ b/customext/cvxif.cc
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@@ -0,0 +1,226 @@
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+// Copyright (C) 2022 Thales DIS Design Services SAS
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+//
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+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0.
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+//
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+// Original Author: Zbigniew CHAMSKI <zbigniew.chamski@thalesgroup.com>
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+
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+#include "cvxif.h"
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+#include "mmu.h"
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+#include <cstring>
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+
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+// Define custom insns templates.
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+// The insn-level wrapper is 'c##n' (default implementation,
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+// writeback disabled), the default implementation
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+// is 'custom##n': illegal instruction, return 0.
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+// The writeback controller 'cvxif_extn_t::do_writeback_p'
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+// is in charge of determining if writeback is required or not.
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+// Expected instruction encoding is 4 bytes.
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+#define customX(n) \
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+static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \
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+ { \
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+ cvxif_t* cvxif = static_cast<cvxif_t*>(p->get_extension()); \
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+ cvxif_insn_t custom_insn; \
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+ custom_insn.i = insn; \
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+ reg_t xd = cvxif->default_custom##n(custom_insn); \
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+ if (cvxif->do_writeback_p(custom_insn)) \
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+ WRITE_RD(xd); \
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+ return pc+4; \
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+ } \
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+ \
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+ reg_t default_custom##n(cvxif_insn_t insn) \
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+ { \
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+ return custom##n(insn); \
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+ }
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+
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+// This class instantiates the CV-X-IF interface.
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+class cvxif_t : public cvxif_extn_t
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+{
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+ public:
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+ const char* name() { return "cvxif_spike"; }
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+
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+ bool do_writeback_p(cvxif_insn_t copro_insn)
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+ {
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+ // INSN_R personality serves to simplify access to standard encoding fields.
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+ cvxif_r_insn_t insn_r = copro_insn.r_type;
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+
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+ if (insn_r.opcode != MATCH_CUSTOM3)
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+ return false;
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+ else switch (insn_r.funct3)
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+ {
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+ case 0b000:
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+ // CUSTOM_NOP and CUSTOM_EXC have rd == x0.
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+ // Return TRUE if destination is NOT x0.
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+ return (insn_r.rd != 0x0);
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+
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+ case 0b010:
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+ // Return false for CUS_SD.
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+ return false;
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+
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+ default:
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+ // All other cases: writeback is assumed REQUIRED.
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+ return true;
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+ }
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+ }
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+
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+ // Custom0 instructions: default behaviour.
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+ reg_t custom0(cvxif_insn_t incoming_insn)
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+ {
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+ illegal_instruction();
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+ return -1;
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+ }
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+
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+ // Custom1 instructions: default behaviour.
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+ reg_t custom1(cvxif_insn_t incoming_insn)
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+ {
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+ illegal_instruction();
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+ return -1;
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+ }
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+
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+ // Custom2 instructions: default behaviour.
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+ reg_t custom2(cvxif_insn_t incoming_insn)
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+ {
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+ illegal_instruction();
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+ return -1;
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+ }
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+
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+ // Custom3 instructions: provide an explicit implementation of decode+exec.
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+ reg_t custom3(cvxif_insn_t incoming_insn)
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+ {
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+ // Assume R-type insn: it shares opcode and funct3 fields with other CVXIF insn formats.
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+ cvxif_r_insn_t r_insn = incoming_insn.r_type;
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+ // INSN_T simplifies access to register values.
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+ insn_t insn = incoming_insn.i;
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+
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+ switch (r_insn.funct3)
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+ {
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+ case 0:
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+
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+ // funct7[1:0] == 0b01: three-input RV add.
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+ // If rd is x0: illegal instruction.
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+ if ((r_insn.funct7 & 0x3) == 0b01)
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+ {
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+ if (insn.rd() == 0x0)
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+ illegal_instruction();
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+
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+ // Destination is not x0: R4-type insn performing a 3-operand RV add
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+ return (reg_t) ((reg_t) RS1 + (reg_t) RS2 + (reg_t) RS3);
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+ }
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+
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+ // Non-memory operations (including NOP and EXC)
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+ switch (r_insn.funct7 & 0b1111001)
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+ {
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+ case 0:
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+ {
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+ // Single-cycle RV addition with privilege: all non-privilege bits are zero.
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+ // funct7[2:1] == 0x0 (PRV_U): CUS_ADD (single-cycle RV ADD, any mode)
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+ // funct7[2:1] == 0x1 (PRV_S): CUS_S_ADD (single-cycle S-/M-mode RV ADD)
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+ // funct7[2:1] == 0x2 (PRV_HS): ILLEGAL
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+ // funct7[2:1] == 0x3 (PRV_M): CUS_M_ADD (single-cycle M-mode RV ADD)
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+ reg_t required_priv = (r_insn.funct7 & 0x6) >> 1;
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+ if (required_priv != PRV_HS && (p->get_state()->prv & required_priv) == required_priv)
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+ return (reg_t) ((reg_t) RS1 + (reg_t) RS2);
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+ else
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+ illegal_instruction();
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+ }
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+
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+ case 0x8:
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+ // Multi-cycle RV add.
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+ // TODO FIXME: Represent delay.
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+ return (reg_t) ((reg_t) RS1 + (reg_t) RS2);
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+
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+ case 0x40:
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+ // Exception. MCAUSE[4:0] encoded in RS1, MCAUSE[5] assumed to be 0.
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+ if (insn.rd() == 0x0 && insn.rs2() == 0x0)
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+ {
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+ // Raise an exception only if registers rd and rs2 are both x0 (no 'bit 5' extension yet).
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+ raise_exception(insn, insn.rs1());
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+ // Writeback will be disabled by 'do_writeback_p'.
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+ return (reg_t) -1;
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+ }
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+ else
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+ // Illegal instruction.
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+ illegal_instruction();
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+
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+ default:
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+ illegal_instruction();
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+ }
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+
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+ case 1:
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+ // Perform RV load. If runtime XLEN is not 64, assume 32.
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+ if (p->get_xlen() == 64)
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+ return MMU.load_int64(RS1 + insn.i_imm());
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+ else
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+ return MMU.load_int32(RS1 + insn.i_imm());
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+
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+ case 2:
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+ // Perform RV store. If runtime XLEN is not 64, assume 32.
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+ if (p->get_xlen() == 64)
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+ MMU.store_uint64(RS1 + insn.s_imm(), RS2);
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+ else
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+ MMU.store_uint32(RS1 + insn.s_imm(), RS2);
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+
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+ // Writeback will be disabled by 'do_writeback_p'.
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+ break;
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+
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+ default:
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+ illegal_instruction();
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+ }
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+
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+ // FORNOW: Return 0xf......f to simplify debugging.
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+ return (reg_t) -1;
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+ }
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+
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+ cvxif_t()
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+ {
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+ }
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+
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+ void raise_exception(insn_t insn, reg_t exc_index)
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+ {
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+ switch (exc_index) {
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+ case CAUSE_MISALIGNED_LOAD:
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+ // Use 0x1 as perfectly unaligned address;-)
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+ throw trap_load_address_misaligned((p ? p->get_state()->v : false), 1, 0, 0);
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+ case CAUSE_LOAD_ACCESS:
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+ // Use 0x1 as invalid address.
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+ throw trap_load_access_fault((p ? p->get_state()->v : false), 1, 0, 0);
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+ case CAUSE_MISALIGNED_STORE:
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+ // Use 0x1 as perfectly unaligned address;-)
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+ throw trap_store_address_misaligned((p ? p->get_state()->v : false), 1, 0, 0);
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+ case CAUSE_STORE_ACCESS:
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+ // Use 0x1 as invalid address.
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+ throw trap_store_access_fault((p ? p->get_state()->v : false), 1, 0, 0);
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+ case CAUSE_LOAD_PAGE_FAULT:
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+ // Use 0x1 as always-faulting address.
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+ throw trap_load_page_fault((p ? p->get_state()->v : false), 1, 0, 0);
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+ case CAUSE_STORE_PAGE_FAULT:
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+ // Use 0x1 as always-faulting address.
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+ throw trap_store_page_fault((p ? p->get_state()->v : false), 1, 0, 0);
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+ default:
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+ illegal_instruction();
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+ }
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+ }
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+
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+ // Define templates of new instructions.
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+ customX(0)
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+ customX(1)
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+ customX(2)
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+ customX(3)
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+
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+ // Set instruction handlers for customN opcode patterns.
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+ // NOTE: This method may need revisiting if multiple custom extensions are to be loaded
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+ // simultaneously in the future.
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+ std::vector<insn_desc_t> get_instructions()
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+ {
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+ std::vector<insn_desc_t> insns;
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+ insns.push_back((insn_desc_t){0x0b, 0x7f, &::illegal_instruction, c0});
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+ insns.push_back((insn_desc_t){0x2b, 0x7f, &::illegal_instruction, c1});
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+ insns.push_back((insn_desc_t){0x5b, 0x7f, &::illegal_instruction, c2});
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+ insns.push_back((insn_desc_t){0x7b, 0x7f, &c3, c3});
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+ return insns;
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+ }
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+
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+private:
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+ // State variables go here.
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+};
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+
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+REGISTER_EXTENSION(cvxif, []() { return new cvxif_t; })
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diff --git a/customext/cvxif_test.c b/customext/cvxif_test.c
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new file mode 100644
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index 000000000..d39ca2229
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--- /dev/null
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+++ b/customext/cvxif_test.c
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@@ -0,0 +1,111 @@
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+// Copyright (C) 2022 Thales DIS Design Services SAS
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+//
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+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0.
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+//
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+// Original Author: Zbigniew CHAMSKI <zbigniew.chamski@thalesgroup.com>
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+//
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+// The following is a RISC-V program to test the functionality of the
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+// basic CVXIF accelerator interface on the Core-V side.
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+// Compile using "riscv-none-elf-gcc -O2 cvxif_test.elf cvxif_test.c"
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+// with -march=/-mabi= settings appropriate for your project.
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+// Run using "spike -l --extension=cvxif cvxif_test.elf", adding
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+// an --isa= setting appropriate for your project.
|
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+//
|
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+// Upon simulating the compiled program, the trace should contain five
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+// instances of custom3 instructions (the third one being decoded as
|
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+// 'unknown').
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+// The last occurrence of 'custom3' instruction in the trace, encoded as
|
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+// 0x8002007b, should be immediately followed by exception
|
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+// 'trap_load_address_misaligned' with a tval equal to 0x1 and the
|
||||
+// execution should terminate correctly with exit code 0.
|
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+//
|
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+// In 64-bit mode, the trace of the last occurrence of custom3
|
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+// instruction should be equivalent to
|
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+//
|
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+// core 0: 0x0000000080002686 (0x8002007b) custom3 (args unknown)
|
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+// core 0: exception trap_load_address_misaligned, epc 0x0000000080002686
|
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+// core 0: tval 0x0000000000000001
|
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+//
|
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+// The corresponding trace in 32-bit mode should be equivalent to
|
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+//
|
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+// core 0: 0x8000205a (0x8002007b) custom3 (args unknown)
|
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+// core 0: exception trap_load_address_misaligned, epc 0x8000205a
|
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+// core 0: tval 0x00000001
|
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+
|
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+#include <assert.h>
|
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+#include <stdio.h>
|
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+#include <stdint.h>
|
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+#include <stdlib.h>
|
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+
|
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+// Values of MCAUSE corresponding to exceptions coming from the coprocessor I/F
|
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+#define CAUSE_MISALIGNED_LOAD 0x4
|
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+#define CAUSE_LOAD_ACCESS 0x5
|
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+#define CAUSE_MISALIGNED_STORE 0x6
|
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+#define CAUSE_STORE_ACCESS 0x7
|
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+#define CAUSE_LOAD_PAGE_FAULT 0xd
|
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+#define CAUSE_STORE_PAGE_FAULT 0xf
|
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+#define CAUSE_COPROCESSOR_EXCEPTION 0x20
|
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+
|
||||
+// Value of TVAL to pass around.
|
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+#define COPRO_TVAL_TEST 0x1a
|
||||
+
|
||||
+// Macro to read a CSR (from spike's "encoding.h")
|
||||
+#define read_csr(reg) ({ unsigned long __tmp; \
|
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+ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
|
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+ __tmp; })
|
||||
+
|
||||
+int main() {
|
||||
+ // "unsigned long int" is always XLEN bits wide.
|
||||
+ unsigned long int x = 123, y = 456, z = 0, t = 0;
|
||||
+ static unsigned long int amem = 111, bmem = 0;
|
||||
+ unsigned long a;
|
||||
+
|
||||
+ // Add x + y into z. Funct7 == 0, funct3 == 0x0.
|
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+ asm volatile (".insn r CUSTOM_3, 0, 0, %0, %1, %2" : "=r"(z) : "r"(x), "r"(y));
|
||||
+ if (z != 123 + 456)
|
||||
+ {
|
||||
+ // printf("FAILURE!!!\n");
|
||||
+ return 1;
|
||||
+ }
|
||||
+
|
||||
+ // Add three operands in a single R4-type add.
|
||||
+ // Leverage current values of x, y and z (z == x + y).
|
||||
+ asm volatile (".insn r CUSTOM_3, 0, 0x1, %0, %1, %2, %3" : "=r"(t) : "r"(x), "r"(y), "r"(z));
|
||||
+ if (t != x + y + z)
|
||||
+ {
|
||||
+ // printf("FAILURE");
|
||||
+ return 2;
|
||||
+ }
|
||||
+ // Load 'a' from 'amem'. CUSTOM_LD: opcode == CUSTOM_3, insn_type == I, funct3 == 0x1.
|
||||
+ asm volatile (".insn i CUSTOM_3, 0x1, %0, %1" : "=r"(a) : "m"(amem), "I"(0));
|
||||
+ if (a != 111)
|
||||
+ {
|
||||
+ // printf("FAILURE!!!\n");
|
||||
+ return 3;
|
||||
+ }
|
||||
+
|
||||
+ // Store 'a' in 'bmem'. CUSTOM_SD: opcode == CUSTOM_3, insn_type == S, funct3 == 0x2.
|
||||
+ asm volatile (".insn s CUSTOM_3, 0x2, %0, %1" : : "r"(a), "m"(bmem));
|
||||
+ if (bmem != 111)
|
||||
+ {
|
||||
+ // printf("FAILURE!!!\n");
|
||||
+ return 4;
|
||||
+ }
|
||||
+
|
||||
+ // Generate a misaligned load exception (mcause == 0x4).
|
||||
+ asm volatile (".insn r CUSTOM_3, 0x0, 0x40, x0, x4, x0" : : );
|
||||
+
|
||||
+ // If we get here, then the exception test failed ==> exit with general failure code.
|
||||
+ exit(1337);
|
||||
+}
|
||||
+
|
||||
+// Override default trap handler.
|
||||
+uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
|
||||
+{
|
||||
+ if (cause == CAUSE_MISALIGNED_LOAD)
|
||||
+ // Successfully terminate.
|
||||
+ exit(0);
|
||||
+ else
|
||||
+ // Fail with explicit retcode.
|
||||
+ exit(5);
|
||||
+}
|
||||
diff --git a/riscv/cvxif.h b/riscv/cvxif.h
|
||||
new file mode 100644
|
||||
index 000000000..e3a6fba1d
|
||||
--- /dev/null
|
||||
+++ b/riscv/cvxif.h
|
||||
@@ -0,0 +1,77 @@
|
||||
+// Copyright (C) 2022 Thales DIS Design Services SAS
|
||||
+//
|
||||
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0.
|
||||
+//
|
||||
+// Original Author: Zbigniew CHAMSKI <zbigniew.chamski@thalesgroup.com>
|
||||
+
|
||||
+#ifndef _RISCV_CVXIF_H
|
||||
+#define _RISCV_CVXIF_H
|
||||
+
|
||||
+#include "extension.h"
|
||||
+
|
||||
+// R-type instruction format
|
||||
+struct cvxif_r_insn_t
|
||||
+{
|
||||
+ unsigned opcode : 7;
|
||||
+ unsigned rd : 5;
|
||||
+ unsigned funct3 : 3;
|
||||
+ unsigned rs1 : 5;
|
||||
+ unsigned rs2 : 5;
|
||||
+ unsigned funct7 : 7;
|
||||
+};
|
||||
+
|
||||
+// R4-type instruction format
|
||||
+struct cvxif_r4_insn_t
|
||||
+{
|
||||
+ unsigned opcode : 7;
|
||||
+ unsigned rd : 5;
|
||||
+ unsigned funct3 : 3;
|
||||
+ unsigned rs1 : 5;
|
||||
+ unsigned rs2 : 5;
|
||||
+ unsigned funct2 : 2;
|
||||
+ unsigned rs3 : 5;
|
||||
+};
|
||||
+
|
||||
+// I-type instruction format
|
||||
+struct cvxif_i_insn_t
|
||||
+{
|
||||
+ unsigned opcode : 7;
|
||||
+ unsigned rd : 5;
|
||||
+ unsigned funct3 : 3;
|
||||
+ unsigned rs1 : 5;
|
||||
+ unsigned imm : 12;
|
||||
+};
|
||||
+
|
||||
+// S-type instruction format
|
||||
+struct cvxif_s_insn_t
|
||||
+{
|
||||
+ unsigned opcode : 7;
|
||||
+ unsigned imm_low : 5;
|
||||
+ unsigned funct3 : 3;
|
||||
+ unsigned rs1 : 5;
|
||||
+ unsigned rs2 : 5;
|
||||
+ unsigned imm_high : 7;
|
||||
+};
|
||||
+
|
||||
+union cvxif_insn_t
|
||||
+{
|
||||
+ cvxif_r_insn_t r_type;
|
||||
+ cvxif_r4_insn_t r4_type;
|
||||
+ cvxif_i_insn_t i_type;
|
||||
+ cvxif_s_insn_t s_type;
|
||||
+ insn_t i;
|
||||
+};
|
||||
+
|
||||
+class cvxif_extn_t : public extension_t
|
||||
+{
|
||||
+ public:
|
||||
+ virtual bool do_writeback_p(cvxif_insn_t insn);
|
||||
+ virtual reg_t custom0(cvxif_insn_t insn);
|
||||
+ virtual reg_t custom1(cvxif_insn_t insn);
|
||||
+ virtual reg_t custom2(cvxif_insn_t insn);
|
||||
+ virtual reg_t custom3(cvxif_insn_t insn);
|
||||
+ std::vector<insn_desc_t> get_instructions();
|
||||
+ std::vector<disasm_insn_t*> get_disasms();
|
||||
+};
|
||||
+
|
||||
+#endif
|
||||
diff --git a/riscv/cvxif_base.cc b/riscv/cvxif_base.cc
|
||||
new file mode 100644
|
||||
index 000000000..5097344c5
|
||||
--- /dev/null
|
||||
+++ b/riscv/cvxif_base.cc
|
||||
@@ -0,0 +1,64 @@
|
||||
+// Copyright (C) 2022 Thales DIS Design Services SAS
|
||||
+//
|
||||
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0.
|
||||
+//
|
||||
+// Original Author: Zbigniew CHAMSKI <zbigniew.chamski@thalesgroup.com>
|
||||
+
|
||||
+#include "cvxif.h"
|
||||
+#include "trap.h"
|
||||
+#include <cstdlib>
|
||||
+
|
||||
+// Virtual base class of CVXIF.
|
||||
+
|
||||
+// Return true if writeback is required.
|
||||
+// Be on the safe side, disable writeback.
|
||||
+bool cvxif_extn_t::do_writeback_p(cvxif_insn_t insn)
|
||||
+{
|
||||
+ return false;
|
||||
+}
|
||||
+
|
||||
+// Define custom insns templates.
|
||||
+// The insn-level wrapper is 'c##n' (default implementation,
|
||||
+// writeback disabled), the default implementation
|
||||
+// is 'custom##n': illegal instruction, return 0.
|
||||
+// The writeback controller 'cvxif_extn_t::do_writeback_p'
|
||||
+// is in charge of determining if writeback is required or not.
|
||||
+// Expected instruction encoding is 4 bytes.
|
||||
+#define customX(n) \
|
||||
+static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \
|
||||
+ { \
|
||||
+ cvxif_extn_t* cvxif = static_cast<cvxif_extn_t*>(p->get_extension()); \
|
||||
+ cvxif_insn_t custom_insn; \
|
||||
+ custom_insn.i = insn; \
|
||||
+ reg_t xd = cvxif->custom##n(custom_insn); \
|
||||
+ if (cvxif->do_writeback_p(custom_insn)) \
|
||||
+ WRITE_RD(xd); \
|
||||
+ return pc+4; \
|
||||
+ } \
|
||||
+ \
|
||||
+ reg_t cvxif_extn_t::custom##n(cvxif_insn_t insn) \
|
||||
+ { \
|
||||
+ illegal_instruction(); \
|
||||
+ return -1; \
|
||||
+ }
|
||||
+
|
||||
+customX(0)
|
||||
+customX(1)
|
||||
+customX(2)
|
||||
+customX(3)
|
||||
+
|
||||
+std::vector<insn_desc_t> cvxif_extn_t::get_instructions()
|
||||
+{
|
||||
+ std::vector<insn_desc_t> insns;
|
||||
+ insns.push_back((insn_desc_t){0x0b, 0x7f, &::illegal_instruction, c0});
|
||||
+ insns.push_back((insn_desc_t){0x2b, 0x7f, &::illegal_instruction, c1});
|
||||
+ insns.push_back((insn_desc_t){0x5b, 0x7f, &::illegal_instruction, c2});
|
||||
+ insns.push_back((insn_desc_t){0x7b, 0x7f, &::illegal_instruction, c3});
|
||||
+ return insns;
|
||||
+}
|
||||
+
|
||||
+std::vector<disasm_insn_t*> cvxif_extn_t::get_disasms()
|
||||
+{
|
||||
+ std::vector<disasm_insn_t*> insns;
|
||||
+ return insns;
|
||||
+}
|
||||
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
|
||||
index 56014662c..3da5f6d8b 100644
|
||||
--- a/riscv/riscv.mk.in
|
||||
+++ b/riscv/riscv.mk.in
|
||||
@@ -26,6 +26,7 @@ riscv_hdrs = \
|
||||
cfg.h \
|
||||
common.h \
|
||||
csrs.h \
|
||||
+ cvxif.h \
|
||||
debug_defines.h \
|
||||
debug_module.h \
|
||||
debug_rom_defines.h \
|
||||
@@ -58,6 +59,7 @@
|
||||
extension.cc \
|
||||
extensions.cc \
|
||||
rocc.cc \
|
||||
+ cvxif_base.cc \
|
||||
devices.cc \
|
||||
rom.cc \
|
||||
clint.cc \
|
||||
|
|
@ -1,110 +0,0 @@
|
|||
diff --git a/vendor/riscv/riscv-isa-sim/riscv/sim.cc b/vendor/riscv/riscv-isa-sim/riscv/sim.cc
|
||||
index dcbd469d3..8863a5f78 100644
|
||||
--- a/vendor/riscv/riscv-isa-sim/riscv/sim.cc
|
||||
+++ b/vendor/riscv/riscv-isa-sim/riscv/sim.cc
|
||||
@@ -40,7 +40,8 @@ sim_t::sim_t(const cfg_t *cfg, bool halted,
|
||||
const char *log_path,
|
||||
bool dtb_enabled, const char *dtb_file,
|
||||
bool socket_enabled,
|
||||
- FILE *cmd_file) // needed for command line option --cmd
|
||||
+ FILE *cmd_file, // needed for command line option --cmd
|
||||
+ size_t max_steps)
|
||||
: htif_t(args),
|
||||
isa(cfg->isa(), cfg->priv()),
|
||||
cfg(cfg),
|
||||
@@ -52,6 +53,8 @@ sim_t::sim_t(const cfg_t *cfg, bool halted,
|
||||
cmd_file(cmd_file),
|
||||
sout_(nullptr),
|
||||
current_step(0),
|
||||
+ total_steps(0),
|
||||
+ max_steps(max_steps),
|
||||
current_proc(0),
|
||||
debug(false),
|
||||
histogram_enabled(false),
|
||||
@@ -236,6 +239,21 @@ void sim_t::step(size_t n)
|
||||
procs[current_proc]->step(steps);
|
||||
|
||||
current_step += steps;
|
||||
+ total_steps += steps;
|
||||
+
|
||||
+ // max_steps must be non-zero to act as an execution limit.
|
||||
+ if (max_steps && total_steps >= max_steps)
|
||||
+ {
|
||||
+ // "Stepout": max step count reached/exceeded.
|
||||
+ std::cerr << "*** Maximum step count reached (total_steps = "
|
||||
+ << std::dec << total_steps << ", max_steps = "
|
||||
+ << max_steps << "), exiting!" << std::endl;
|
||||
+ // TODO FIXME: Determine the best method of terminating.
|
||||
+ // FORNOW: Exit successfully and let the caller of Spike
|
||||
+ // decide how to proceed in view of simulation results.
|
||||
+ exit(0);
|
||||
+ }
|
||||
+
|
||||
if (current_step == INTERLEAVE)
|
||||
{
|
||||
current_step = 0;
|
||||
diff --git a/vendor/riscv/riscv-isa-sim/riscv/sim.h b/vendor/riscv/riscv-isa-sim/riscv/sim.h
|
||||
index 3109173f1..377e96514 100644
|
||||
--- a/vendor/riscv/riscv-isa-sim/riscv/sim.h
|
||||
+++ b/vendor/riscv/riscv-isa-sim/riscv/sim.h
|
||||
@@ -32,7 +32,8 @@ public:
|
||||
const debug_module_config_t &dm_config, const char *log_path,
|
||||
bool dtb_enabled, const char *dtb_file,
|
||||
bool socket_enabled,
|
||||
- FILE *cmd_file); // needed for command line option --cmd
|
||||
+ FILE *cmd_file, // needed for command line option --cmd
|
||||
+ size_t max_steps);
|
||||
~sim_t();
|
||||
|
||||
// run the simulation to completion
|
||||
@@ -88,6 +89,8 @@ private:
|
||||
static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core
|
||||
static const size_t CPU_HZ = 1000000000; // 1GHz CPU
|
||||
size_t current_step;
|
||||
+ size_t total_steps;
|
||||
+ size_t max_steps;
|
||||
size_t current_proc;
|
||||
bool debug;
|
||||
bool histogram_enabled; // provide a histogram of PCs
|
||||
diff --git a/vendor/riscv/riscv-isa-sim/spike_main/spike.cc b/vendor/riscv/riscv-isa-sim/spike_main/spike.cc
|
||||
index 7290f38bb..657533cb1 100644
|
||||
--- a/vendor/riscv/riscv-isa-sim/spike_main/spike.cc
|
||||
+++ b/vendor/riscv/riscv-isa-sim/spike_main/spike.cc
|
||||
@@ -86,6 +86,8 @@ static void help(int exit_code = 1)
|
||||
fprintf(stderr, " --dm-no-halt-groups Debug module won't support halt groups\n");
|
||||
fprintf(stderr, " --dm-no-impebreak Debug module won't support implicit ebreak in program buffer\n");
|
||||
fprintf(stderr, " --blocksz=<size> Cache block size (B) for CMO operations(powers of 2) [default 64]\n");
|
||||
+ fprintf(stderr, " --steps=<n> Stop simulation after reaching specified number of steps "
|
||||
+ "(default: unlimited)\n");
|
||||
|
||||
exit(exit_code);
|
||||
}
|
||||
@@ -361,6 +363,7 @@ int main(int argc, char** argv)
|
||||
.support_haltgroups = true,
|
||||
.support_impebreak = true
|
||||
};
|
||||
+ size_t max_steps = 0;
|
||||
cfg_arg_t<size_t> nprocs(1);
|
||||
|
||||
cfg_t cfg(/*default_initrd_bounds=*/std::make_pair((reg_t)0, (reg_t)0),
|
||||
@@ -465,6 +468,7 @@ int main(int argc, char** argv)
|
||||
exit(-1);
|
||||
}
|
||||
});
|
||||
+ parser.option(0, "steps", 1, [&](const char* s){max_steps = strtoull(s, 0, 0);});
|
||||
parser.option(0, "dm-progsize", 1,
|
||||
[&](const char* s){dm_config.progbufsize = atoul_safe(s);});
|
||||
parser.option(0, "dm-no-impebreak", 0,
|
||||
@@ -564,9 +568,9 @@ int main(int argc, char** argv)
|
||||
}
|
||||
|
||||
sim_t s(&cfg, halted,
|
||||
- mems, plugin_devices, htif_args, dm_config, log_path, dtb_enabled, dtb_file,
|
||||
- socket,
|
||||
- cmd_file);
|
||||
+ mems, plugin_devices, htif_args, dm_config, log_path, dtb_enabled, dtb_file,
|
||||
+ socket,
|
||||
+ cmd_file, max_steps);
|
||||
std::unique_ptr<remote_bitbang_t> remote_bitbang((remote_bitbang_t *) NULL);
|
||||
std::unique_ptr<jtag_dtm_t> jtag_dtm(
|
||||
new jtag_dtm_t(&s.debug_module, dmi_rti));
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
diff --git a/vendor/riscv/riscv-isa-sim/riscv/sim.cc b/vendor/riscv/riscv-isa-sim/riscv/sim.cc
|
||||
index 8863a5f7..9179ee4e 100644
|
||||
--- a/vendor/riscv/riscv-isa-sim/riscv/sim.cc
|
||||
+++ b/vendor/riscv/riscv-isa-sim/riscv/sim.cc
|
||||
@@ -257,7 +257,8 @@ void sim_t::step(size_t n)
|
||||
if (current_step == INTERLEAVE)
|
||||
{
|
||||
current_step = 0;
|
||||
- procs[current_proc]->get_mmu()->yield_load_reservation();
|
||||
+ if (procs.size() > 1)
|
||||
+ procs[current_proc]->get_mmu()->yield_load_reservation();
|
||||
if (++current_proc == procs.size()) {
|
||||
current_proc = 0;
|
||||
if (clint) clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
|
||||
|
|
@ -1,85 +0,0 @@
|
|||
diff --git a/vendor/riscv/riscv-isa-sim/customext/cvxif.cc b/vendor/riscv/riscv-isa-sim/customext/cvxif.cc
|
||||
index ae92b1cc..b1bef8e6 100644
|
||||
--- a/vendor/riscv/riscv-isa-sim/customext/cvxif.cc
|
||||
+++ b/vendor/riscv/riscv-isa-sim/customext/cvxif.cc
|
||||
@@ -134,17 +134,26 @@ class cvxif_t : public cvxif_extn_t
|
||||
}
|
||||
break;
|
||||
case FUNC3_1:
|
||||
- //Actually only CUS_ADD using func3 equal to one, we don't need to add another switch case
|
||||
- return (reg_t) ((reg_t) RS1 + (reg_t) RS2);
|
||||
+ switch(r_insn.funct7) {
|
||||
+ case 0:
|
||||
+ return (reg_t) ((reg_t) RS1 + (reg_t) RS2);
|
||||
+ break;
|
||||
+ default:
|
||||
+ illegal_instruction();
|
||||
+ }
|
||||
|
||||
case FUNC3_2:
|
||||
- //Actually only CUS_EXC using func3 equal to one, we don't need to add another switch case
|
||||
- if (r_insn.rs2 != 0 || r_insn.rd != 0){
|
||||
- illegal_instruction();
|
||||
- } else {
|
||||
- raise_exception(insn, (reg_t) (r_insn.rs1));
|
||||
- }
|
||||
- break;
|
||||
+ switch (r_insn.funct7) {
|
||||
+ case (0x60):
|
||||
+ if (r_insn.rs2 != 0 || r_insn.rd != 0){
|
||||
+ illegal_instruction();
|
||||
+ } else {
|
||||
+ raise_exception(insn, (reg_t) (r_insn.rs1));
|
||||
+ }
|
||||
+ break;
|
||||
+ default:
|
||||
+ illegal_instruction();
|
||||
+ }
|
||||
default:
|
||||
illegal_instruction();
|
||||
}
|
||||
@@ -195,15 +204,15 @@ class cvxif_t : public cvxif_extn_t
|
||||
// Use 0x1 as always-faulting address.
|
||||
throw trap_store_page_fault((p ? p->get_state()->v : false), 1, 0, 0);
|
||||
case CAUSE_FETCH_GUEST_PAGE_FAULT:
|
||||
- throw trap_instruction_guest_page_fault(1, 0, 0);
|
||||
+ throw trap_instruction_guest_page_fault(0, 0, 0);
|
||||
case CAUSE_LOAD_GUEST_PAGE_FAULT:
|
||||
- throw trap_load_guest_page_fault( 1, 0, 0);
|
||||
+ throw trap_load_guest_page_fault(0, 0, 0);
|
||||
case CAUSE_VIRTUAL_INSTRUCTION:
|
||||
- throw trap_virtual_instruction(1);
|
||||
+ throw trap_virtual_instruction(0);
|
||||
case CAUSE_STORE_GUEST_PAGE_FAULT:
|
||||
- throw trap_store_guest_page_fault(1, 0, 0);
|
||||
+ throw trap_store_guest_page_fault(0, 0, 0);
|
||||
default:
|
||||
- illegal_instruction();
|
||||
+ throw trap_unknown_instruction(exc_index, (reg_t)0);
|
||||
}
|
||||
}
|
||||
|
||||
diff --git a/vendor/riscv/riscv-isa-sim/riscv/trap.h b/vendor/riscv/riscv-isa-sim/riscv/trap.h
|
||||
index 54948fdd..78b549cf 100644
|
||||
--- a/vendor/riscv/riscv-isa-sim/riscv/trap.h
|
||||
+++ b/vendor/riscv/riscv-isa-sim/riscv/trap.h
|
||||
@@ -82,6 +82,12 @@ class mem_trap_t : public trap_t
|
||||
std::string name() { return "trap_"#x; } \
|
||||
};
|
||||
|
||||
+#define DECLARE_CUSTOM_TRAP(x) class trap_##x : public insn_trap_t { \
|
||||
+ public: \
|
||||
+ trap_##x(reg_t n, reg_t tval) : insn_trap_t(n, false, tval) {} \
|
||||
+ std::string name() { return "trap_"#x; } \
|
||||
+};
|
||||
+
|
||||
#define DECLARE_INST_WITH_GVA_TRAP(n, x) class trap_##x : public insn_trap_t { \
|
||||
public: \
|
||||
trap_##x(bool gva, reg_t tval) : insn_trap_t(n, gva, tval) {} \
|
||||
@@ -119,5 +125,6 @@ DECLARE_MEM_GVA_TRAP(CAUSE_FETCH_GUEST_PAGE_FAULT, instruction_guest_page_fault)
|
||||
DECLARE_MEM_GVA_TRAP(CAUSE_LOAD_GUEST_PAGE_FAULT, load_guest_page_fault)
|
||||
DECLARE_INST_TRAP(CAUSE_VIRTUAL_INSTRUCTION, virtual_instruction)
|
||||
DECLARE_MEM_GVA_TRAP(CAUSE_STORE_GUEST_PAGE_FAULT, store_guest_page_fault)
|
||||
+DECLARE_CUSTOM_TRAP(unknown_instruction)
|
||||
|
||||
#endif
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
diff --git a/vendor/riscv/riscv-isa-sim/customext/cvxif.cc b/vendor/riscv/riscv-isa-sim/customext/cvxif.cc
|
||||
index b1bef8e6..20aea89c 100644
|
||||
--- a/vendor/riscv/riscv-isa-sim/customext/cvxif.cc
|
||||
+++ b/vendor/riscv/riscv-isa-sim/customext/cvxif.cc
|
||||
@@ -101,7 +101,7 @@ class cvxif_t : public cvxif_extn_t
|
||||
case FUNC3_0:
|
||||
switch (r_insn.funct7 & 0x1) {
|
||||
case NO_RS3:
|
||||
- switch (r_insn.funct7 & 0xe) {
|
||||
+ switch (r_insn.funct7 & 0x7e) {
|
||||
case CUS_NOP:
|
||||
break;
|
||||
case CUS_U_ADD:
|
||||
Loading…
Add table
Add a link
Reference in a new issue