fpu: Add distributed pipe regs to ease FPGA timing

.gitlab-ci.yml

@@ -63,12 +63,13 @@ amo-quest:
   dependencies:
     - build
 
-# fp-quest:
-#   stage: write-back
-#   script:
-#     - make -j${NUM_JOBS} run-fp-tests batch-mode=1 defines=WB_DCACHE
-#   dependencies:
-#     - build
+# floating point
+fp-quest:
+  stage: write-back
+  script:
+    - make -j${NUM_JOBS} run-fp-tests batch-mode=1 defines=WB_DCACHE
+  dependencies:
+    - build
 
 bench-quest:
   stage: write-back
@@ -110,12 +111,12 @@ amo-ver:
     - build
 
 # floating point
-# fp-ver:
-#   stage: write-back
-#   script:
-#     - make -j${NUM_JOBS} run-fp-verilator defines=WB_DCACHE
-#   dependencies:
-#     - build
+fp-ver:
+  stage: write-back
+  script:
+    - make -j${NUM_JOBS} run-fp-verilator defines=WB_DCACHE
+  dependencies:
+    - build
 
 bench-ver:
   stage: write-back
@@ -167,12 +168,12 @@ s-amo-quest:
     - build
 
 # floating point
-# s-fp-quest:
-#   stage: write-through
-#   script:
-#     - make -j${NUM_JOBS} run-fp-tests defines=WT_DCACHE batch-mode=1
-#   dependencies:
-#     - build
+s-fp-quest:
+  stage: write-through
+  script:
+    - make -j${NUM_JOBS} run-fp-tests defines=WT_DCACHE batch-mode=1
+  dependencies:
+    - build
 
 s-bench-quest:
   stage: write-through
@@ -214,12 +215,12 @@ amo-ver:
     - build
 
 # floating point
-# s-fp-ver:
-#   stage: write-through
-#   script:
-#     - make -j${NUM_JOBS} run-fp-verilator defines=WT_DCACHE
-#   dependencies:
-#     - build
+s-fp-ver:
+  stage: write-through
+  script:
+    - make -j${NUM_JOBS} run-fp-verilator defines=WT_DCACHE
+  dependencies:
+    - build
 
 s-bench-ver:
   stage: write-through

CHANGELOG.md

@@ -8,10 +8,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 
 ### Added
 
-- Chcek execute PMA on instruction frontend
+- Check execute PMA on instruction frontend
+- Add support for non-contiguous cacheable regions to the PMA checks
 
 ### Changed
 
+- Several small fixes to get the code running on VCS
 - Fix compressed instruction decoding in tracer
 - Fix privilege bug in performance counters. The counters have always been accessible in user mode.
 - Re-work interrupt and debug subsystem to associate requests during decode. This improves stability on for non-idempotent loads.
@@ -22,6 +24,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 - Bump `common_cells` to v1.12.0
 - Provision exponential backoff for AMO SC in L1 D$ miss handler
 - Add lowrisc PLIC
+- Improve FPU pipelining 
 
 ### 4.1.2
 

Flist.ariane

@@ -16,60 +16,61 @@
 // Date: 15.08.2018
 // Description: File list for OpenPiton flow
 +incdir+src/common_cells/include/common_cells/
-src/common_cells/src/fifo_v1.sv
-src/common_cells/src/fifo_v2.sv
++incdir+src/util/
+src/common_cells/src/deprecated/fifo_v1.sv
+src/common_cells/src/deprecated/fifo_v2.sv
 src/common_cells/src/fifo_v3.sv
 src/common_cells/src/lfsr_8bit.sv
 src/common_cells/src/lzc.sv
 src/common_cells/src/rr_arb_tree.sv
-src/common_cells/src/rrarbiter.sv
+src/common_cells/src/deprecated/rrarbiter.sv
 src/common_cells/src/rstgen_bypass.sv
 src/common_cells/src/sync.sv
 src/common_cells/src/sync_wedge.sv
 src/common_cells/src/cdc_2phase.sv
-src/common_cells/src/stream_arbiter_flushable.sv
+src/common_cells/src/deprecated/stream_arbiter.sv
+src/common_cells/src/deprecated/stream_arbiter_flushable.sv
 src/common_cells/src/shift_reg.sv
 src/register_interface/src/apb_to_reg.sv
 src/register_interface/src/reg_intf_pkg.sv
 src/register_interface/src/reg_intf.sv
 src/fpu/src/fpnew_pkg.sv
-// src/fpu/src/fpu_div_sqrt_mvp/hdl/fpu_ff.sv
-// src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
-// src/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
-// src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv
-// src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
-// src/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
-// src/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
-// src/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
-// src/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
-// src/fpu/src/fpnew_cast_multi.sv
-// src/fpu/src/fpnew_classifier.sv
-// src/fpu/src/fpnew_divsqrt_multi.sv
-// src/fpu/src/fpnew_f2fcast.sv
-// src/fpu/src/fpnew_f2icast.sv
-// src/fpu/src/fpnew_fma_multi.sv
-// src/fpu/src/fpnew_fma.sv
-// src/fpu/src/fpnew_i2fcast.sv
-// src/fpu/src/fpnew_noncomp.sv
-// src/fpu/src/fpnew_opgroup_block.sv
-// src/fpu/src/fpnew_opgroup_fmt_slice.sv
-// src/fpu/src/fpnew_opgroup_multifmt_slice.sv
-// src/fpu/src/fpnew_pipe_in.sv
-// src/fpu/src/fpnew_pipe_out.sv
-// src/fpu/src/fpnew_pkg.sv
-// src/fpu/src/fpnew_rounding.sv
-// src/fpu/src/fpnew_top.sv
+src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
+src/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
+src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv
+src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
+src/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
+src/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
+src/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
+src/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
+src/fpu/src/fpnew_cast_multi.sv
+src/fpu/src/fpnew_classifier.sv
+src/fpu/src/fpnew_divsqrt_multi.sv
+src/fpu/src/fpnew_f2fcast.sv
+src/fpu/src/fpnew_f2icast.sv
+src/fpu/src/fpnew_fma_multi.sv
+src/fpu/src/fpnew_fma.sv
+src/fpu/src/fpnew_i2fcast.sv
+src/fpu/src/fpnew_noncomp.sv
+src/fpu/src/fpnew_opgroup_block.sv
+src/fpu/src/fpnew_opgroup_fmt_slice.sv
+src/fpu/src/fpnew_opgroup_multifmt_slice.sv
+src/fpu/src/fpnew_pipe_in.sv
+src/fpu/src/fpnew_pipe_out.sv
+src/fpu/src/fpnew_pipe_fma_inside.sv
+src/fpu/src/fpnew_rounding.sv
+src/fpu/src/fpnew_top.sv
 src/axi/src/axi_pkg.sv
-tb/ariane_soc_pkg.sv
 src/riscv-dbg/src/dm_pkg.sv
 include/riscv_pkg.sv
 include/ariane_pkg.sv
+tb/ariane_soc_pkg.sv
 include/ariane_axi_pkg.sv
 include/wt_cache_pkg.sv
 //include/std_cache_pkg.sv
 include/axi_intf.sv
-src/util/instruction_tracer_pkg.sv
 src/util/instruction_tracer_if.sv
+src/util/instruction_tracer.sv
 src/util/sram.sv
 src/util/axi_master_connect.sv
 src/util/axi_master_connect_rev.sv

Makefile

@@ -137,8 +137,8 @@ src :=  $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv))              \
         src/common_cells/src/rstgen.sv                                         \
         src/common_cells/src/stream_mux.sv                                     \
         src/common_cells/src/stream_demux.sv                                   \
-        src/common_cells/src/stream_arbiter.sv                                 \
-        src/common_cells/src/stream_arbiter_flushable.sv                       \
+        src/common_cells/src/deprecated/stream_arbiter.sv                      \
+        src/common_cells/src/deprecated/stream_arbiter_flushable.sv            \
         src/util/axi_master_connect.sv                                         \
         src/util/axi_slave_connect.sv                                          \
         src/util/axi_master_connect_rev.sv                                     \
@@ -154,11 +154,11 @@ src :=  $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv))              \
         src/common_cells/src/sync_wedge.sv                                     \
         src/common_cells/src/edge_detect.sv                                    \
         src/common_cells/src/fifo_v3.sv                                        \
-        src/common_cells/src/fifo_v2.sv                                        \
-        src/common_cells/src/fifo_v1.sv                                        \
+        src/common_cells/src/deprecated/fifo_v2.sv                             \
+        src/common_cells/src/deprecated/fifo_v1.sv                             \
         src/common_cells/src/lzc.sv                                            \
         src/common_cells/src/rr_arb_tree.sv                                    \
-        src/common_cells/src/rrarbiter.sv                                      \
+        src/common_cells/src/deprecated/rrarbiter.sv                           \
         src/common_cells/src/stream_delay.sv                                   \
         src/common_cells/src/lfsr_8bit.sv                                      \
         src/common_cells/src/lfsr_16bit.sv                                     \

ci/riscv-fp-tests.list

@@ -28,6 +28,10 @@ rv64ud-p-fcvt_w
 rv64ud-p-fdiv
 rv64ud-p-fmadd
 rv64ud-p-fmin
+rv64ud-p-ldst
+rv64ud-p-move
+rv64ud-p-recoding
+rv64ud-p-structural
 rv64ud-v-fadd
 rv64ud-v-fclass
 rv64ud-v-fcmp
@@ -36,3 +40,7 @@ rv64ud-v-fcvt_w
 rv64ud-v-fdiv
 rv64ud-v-fmadd
 rv64ud-v-fmin
+rv64ud-v-ldst
+rv64ud-v-move
+rv64ud-v-recoding
+rv64ud-v-structural

include/ariane_pkg.sv

@@ -161,12 +161,12 @@ package ariane_pkg;
 
 `ifdef PITON_ARIANE
     // Floating-point extensions configuration
-    localparam bit RVF = 1'b0; // Is F extension enabled
-    localparam bit RVD = 1'b0; // Is D extension enabled
+    localparam bit RVF = 1'b1; // Is F extension enabled
+    localparam bit RVD = 1'b1; // Is D extension enabled
 `else
     // Floating-point extensions configuration
-    localparam bit RVF = 1'b0; // Is F extension enabled
-    localparam bit RVD = 1'b0; // Is D extension enabled
+    localparam bit RVF = 1'b1; // Is F extension enabled
+    localparam bit RVD = 1'b1; // Is D extension enabled
 `endif
     localparam bit RVA = 1'b1; // Is A extension enabled
 

src/common_cells

@@ -1 +1 @@
-Subproject commit 51ffae3ff2e339c672b51ae3ac2cb38c29dbe254
+Subproject commit 34d8ed90e03209501fa64da5cb30068846caaeca

src/fpu

@@ -1 +1 @@
-Subproject commit b34d5f6069bf35abeb8a9b155d4f80d80dcde250
+Subproject commit 857ae928242d8afc40b4fea3f9d4a0cdf4ebe7c5

src/fpu_wrap.sv

@@ -71,7 +71,7 @@ generate
                    '{default: fpnew_pkg::MERGED},   // DIVSQRT
                    '{default: fpnew_pkg::PARALLEL}, // NONCOMP
                    '{default: fpnew_pkg::MERGED}},  // CONV
-      PipeConfig: fpnew_pkg::AFTER
+      PipeConfig: fpnew_pkg::DISTRIBUTED
     };
 
     //-------------------------------------------------