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Implement debug instruction and CSR in tracer

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This commit is contained in:
Florian Zaruba 2018-07-10 14:36:01 -07:00
parent f501291661
commit d4a1d7e616
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GPG key ID: E742FFE8EC38A792
2 changed files with 40 additions and 33 deletions
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72
src/util/instruction_trace_item.svh
View file

@ -65,41 +65,46 @@ class instruction_trace_item;
function string csrAddrToStr(logic [11:0] addr);
case (addr)
CSR_SSTATUS: return "sstatus";
CSR_SIE: return "sie";
CSR_STVEC: return "stvec";
CSR_SCOUNTEREN: return "scounteren";
CSR_SSCRATCH: return "sscratch";
CSR_SEPC: return "sepc";
CSR_SCAUSE: return "scause";
CSR_STVAL: return "stval";
CSR_SIP: return "sip";
CSR_SATP: return "satp";
riscv::CSR_SSTATUS: return "sstatus";
riscv::CSR_SIE: return "sie";
riscv::CSR_STVEC: return "stvec";
riscv::CSR_SCOUNTEREN: return "scounteren";
riscv::CSR_SSCRATCH: return "sscratch";
riscv::CSR_SEPC: return "sepc";
riscv::CSR_SCAUSE: return "scause";
riscv::CSR_STVAL: return "stval";
riscv::CSR_SIP: return "sip";
riscv::CSR_SATP: return "satp";
CSR_MSTATUS: return "mstatus";
CSR_MISA: return "misa";
CSR_MEDELEG: return "medeleg";
CSR_MIDELEG: return "mideleg";
CSR_MIE: return "mie";
CSR_MTVEC: return "mtvec";
CSR_MCOUNTEREN: return "mcounteren";
CSR_MSCRATCH: return "mscratch";
CSR_MEPC: return "mepc";
CSR_MCAUSE: return "mcause";
CSR_MTVAL: return "mtval";
CSR_MIP: return "mip";
CSR_PMPCFG0: return "pmpcfg0";
CSR_PMPADDR0: return "pmpaddr0";
CSR_MVENDORID: return "mvendorid";
CSR_MARCHID: return "marchid";
CSR_MIMPID: return "mimpid";
CSR_MHARTID: return "mhartid";
CSR_MCYCLE: return "mcycle";
CSR_MINSTRET: return "minstret";
riscv::CSR_MSTATUS: return "mstatus";
riscv::CSR_MISA: return "misa";
riscv::CSR_MEDELEG: return "medeleg";
riscv::CSR_MIDELEG: return "mideleg";
riscv::CSR_MIE: return "mie";
riscv::CSR_MTVEC: return "mtvec";
riscv::CSR_MCOUNTEREN: return "mcounteren";
riscv::CSR_MSCRATCH: return "mscratch";
riscv::CSR_MEPC: return "mepc";
riscv::CSR_MCAUSE: return "mcause";
riscv::CSR_MTVAL: return "mtval";
riscv::CSR_MIP: return "mip";
riscv::CSR_PMPCFG0: return "pmpcfg0";
riscv::CSR_PMPADDR0: return "pmpaddr0";
riscv::CSR_MVENDORID: return "mvendorid";
riscv::CSR_MARCHID: return "marchid";
riscv::CSR_MIMPID: return "mimpid";
riscv::CSR_MHARTID: return "mhartid";
riscv::CSR_MCYCLE: return "mcycle";
riscv::CSR_MINSTRET: return "minstret";
CSR_CYCLE: return "cycle";
CSR_TIME: return "time";
CSR_INSTRET: return "instret";
riscv::CSR_DCSR return "dcsr";
riscv::CSR_DPC return "dpc";
riscv::CSR_DSCRATCH0 return "dscratch0";
riscv::CSR_DSCRATCH1 return "dscratch0";
riscv::CSR_CYCLE: return "cycle";
riscv::CSR_TIME: return "time";
riscv::CSR_INSTRET: return "instret";
default: return $sformatf("%0h", addr);
endcase
@ -185,6 +190,7 @@ class instruction_trace_item;
INSTR_EBREAK: s = this.printMnemonic("ebreak");
INSTR_MRET: s = this.printMnemonic("mret");
INSTR_SRET: s = this.printMnemonic("sret");
INSTR_DRET: s = this.printMnemonic("dret");
INSTR_WFI: s = this.printMnemonic("wfi");
INSTR_SFENCE: s = this.printMnemonic("sfence.vma");
// loads and stores

1
src/util/instruction_tracer_defines.svh
View file

@ -90,6 +90,7 @@ parameter INSTR_ECALL = { 12'b000000000000, 13'b0, OPCODE_SYSTEM };
parameter INSTR_EBREAK = { 12'b000000000001, 13'b0, OPCODE_SYSTEM };
parameter INSTR_MRET = { 12'b001100000010, 13'b0, OPCODE_SYSTEM };
parameter INSTR_SRET = { 12'b000100000010, 13'b0, OPCODE_SYSTEM };
parameter INSTR_DRET = { 12'b011110110010, 13'b0, OPCODE_SYSTEM };
parameter INSTR_WFI = { 12'b000100000101, 13'b0, OPCODE_SYSTEM };
parameter INSTR_SFENCE = { 12'b0001001?????, 13'b?, OPCODE_SYSTEM };