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Fix vcs-uvm simulation flow (#2485)

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AEzzejjari 2024-08-30 16:57:35 +01:00 • committed by GitHub
parent 8ef28596d5
commit d577aaf850
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2
verif/env/uvme/uvme_cva6_env.sv vendored
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@ -166,7 +166,7 @@ function void uvme_cva6_env_c::build_phase(uvm_phase phase);
`uvm_info("CFG", $sformatf("Found configuration handle:\n%s", cfg.sprint()), UVM_DEBUG)
end
cfg.rvfi_cfg.nret = cfg.CVA6Cfg.NrCommitPorts;
cfg.rvfi_cfg.nret = RTLCVA6Cfg.NrCommitPorts;
if (cfg.enabled) begin
void'(uvm_config_db#(uvme_cva6_cntxt_c)::get(this, "", "cntxt", cntxt));