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Increase code coverage on second ALU by removing branch logic (#2362)
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3 changed files with 18 additions and 20 deletions
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@ -1,2 +1,2 @@
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cv32a65x:
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gates: 171990
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gates: 171460
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34
core/alu.sv
34
core/alu.sv
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@ -22,6 +22,7 @@ module alu
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import ariane_pkg::*;
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#(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter bit HasBranch = 1'b1,
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parameter type fu_data_t = logic
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) (
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// Subsystem Clock - SUBSYSTEM
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@ -68,15 +69,7 @@ module alu
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logic [CVA6Cfg.XLEN-1:0] adder_result;
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logic [CVA6Cfg.XLEN-1:0] operand_a_bitmanip, bit_indx;
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always_comb begin
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adder_op_b_negate = 1'b0;
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unique case (fu_data_i.operation)
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// ADDER OPS
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EQ, NE, SUB, SUBW, ANDN, ORN, XNOR: adder_op_b_negate = 1'b1;
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default: ;
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endcase
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end
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assign adder_op_b_negate = fu_data_i.operation inside {EQ, NE, SUB, SUBW, ANDN, ORN, XNOR};
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always_comb begin
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operand_a_bitmanip = fu_data_i.operand_a;
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@ -115,16 +108,19 @@ module alu
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assign adder_z_flag = ~|adder_result;
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// get the right branch comparison result
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always_comb begin : branch_resolve
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// set comparison by default
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alu_branch_res_o = 1'b1;
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case (fu_data_i.operation)
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EQ: alu_branch_res_o = adder_z_flag;
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NE: alu_branch_res_o = ~adder_z_flag;
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LTS, LTU: alu_branch_res_o = less;
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GES, GEU: alu_branch_res_o = ~less;
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default: alu_branch_res_o = 1'b1;
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endcase
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if (HasBranch) begin
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always_comb begin : branch_resolve
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// set comparison by default
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case (fu_data_i.operation)
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EQ: alu_branch_res_o = adder_z_flag;
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NE: alu_branch_res_o = ~adder_z_flag;
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LTS, LTU: alu_branch_res_o = less;
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GES, GEU: alu_branch_res_o = ~less;
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default: alu_branch_res_o = 1'b1;
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endcase
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end
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end else begin
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assign alu_branch_res_o = 1'b0;
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end
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// ---------
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@ -294,6 +294,7 @@ module ex_stage
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// 1. ALU (combinatorial)
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alu #(
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.CVA6Cfg (CVA6Cfg),
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.HasBranch(1'b1),
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.fu_data_t(fu_data_t)
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) alu_i (
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.clk_i,
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@ -460,6 +461,7 @@ module ex_stage
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alu #(
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.CVA6Cfg (CVA6Cfg),
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.HasBranch(1'b0),
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.fu_data_t(fu_data_t)
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) alu2_i (
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.clk_i,
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