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Bump verif/core-v-verif from f7bda8e to NOTMERGED (#2044)

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MarioOpenHWGroup 2024-05-30 15:57:58 +02:00 • committed by GitHub
parent 0da83492f6
commit d714d833cb
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17 changed files with 242 additions and 156 deletions
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6
.github/workflows/ci.yml vendored
View file

@ -42,7 +42,7 @@ jobs:
cache-name: cache-spike
with:
path: tools/spike/
key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ hashFiles('verif/regress/install-spike.sh', 'verif/core-v-verif/vendor/riscv/riscv-isa-sim/') }}
key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ hashFiles('verif/regress/install-spike.sh', 'verif/core-v-verif/vendor/riscv/') }}
- name: Prepare
run: |
@ -95,7 +95,7 @@ jobs:
cache-name: cache-spike
with:
path: tools/spike/
key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ hashFiles('verif/regress/install-spike.sh', 'verif/core-v-verif/vendor/riscv/riscv-isa-sim/') }}
key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ hashFiles('verif/regress/install-spike.sh', 'verif/core-v-verif/vendor/riscv/') }}
- name: Run Tests
run: |
@ -155,7 +155,7 @@ jobs:
cache-name: cache-spike
with:
path: tools/spike/
key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ hashFiles('verif/regress/install-spike.sh', 'verif/core-v-verif/vendor/riscv/riscv-isa-sim/') }}
key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ hashFiles('verif/regress/install-spike.sh', 'verif/core-v-verif/vendor/riscv/') }}
- name: Run Tests
run: |

2
.gitlab-ci.yml
View file

@ -139,8 +139,10 @@ smoke:
- DV_SIMULATORS:
- "veri-testharness,spike"
- "vcs-testharness,spike"
- "questa-testharness,spike"
- "vcs-uvm,spike"
script:
- source $QUESTA_BASHRC
- bash verif/regress/smoke-tests.sh
- !reference [.simu_after_script]

8
Makefile
View file

@ -254,11 +254,11 @@ incdir := $(CVA6_REPO_DIR)/vendor/pulp-platform/common_cells/include/ $(CVA6_REP
$(SPIKE_INSTALL_DIR)/include/disasm/
# Compile and sim flags
compile_flag += -incr -64 -nologo -quiet -suppress 13262 -suppress 8607 -permissive -svinputport=compat +define+$(defines) -suppress 8386
vopt_flag += -incr -64 -nologo -quiet -suppress 13262 -permissive -svinputport=compat -t 1ns
compile_flag += -incr -64 -nologo -quiet -suppress 13262 -suppress 8607 -permissive -svinputport=compat +define+$(defines) -suppress 8386 -suppress vlog-2577
vopt_flag += -suppress 2085 -suppress 7063 -suppress 2698 -suppress 13262
uvm-flags += +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
questa-flags += -t 1ns -64 $(gui-sim) $(QUESTASIM_FLAGS) +tohost_addr=$(tohost_addr) +define+QUESTA
questa-flags += -t 1ns -64 $(gui-sim) $(QUESTASIM_FLAGS) +tohost_addr=$(tohost_addr) +define+QUESTA -suppress 3356
compile_flag_vhd += -64 -nologo -quiet -2008
# Iterate over all include directories and write them with +incdir+ prefixed
@ -318,7 +318,7 @@ vcs: vcs_build
# Build the TB and module using QuestaSim
build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ariane_dpi.so
# Optimize top level
$(VOPT) -64 -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis -dpilib $(SPIKE_INSTALL_DIR)/lib/libriscv -dpilib $(SPIKE_INSTALL_DIR)/lib/lifesvr -suppress 2085 -suppress 7063
$(VOPT) -64 -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis -dpilib $(SPIKE_INSTALL_DIR)/lib/libriscv -dpilib $(SPIKE_INSTALL_DIR)/lib/lifesvr $(vopt_flag)
# src files
$(library)/.build-srcs: $(library)

5
core/cva6_rvfi.sv
View file

@ -349,7 +349,8 @@ module cva6_rvfi
`CONNECT_RVFI_FULL(1'b1, mstatus, csr.mstatus_extended)
`CONNECT_RVFI_FULL(1'b1, mstatush, '0)
bit [31:0] mstatush_q;
`CONNECT_RVFI_FULL(1'b1, mstatush, mstatush_q)
`CONNECT_RVFI_FULL(1'b1, misa, IsaCode)
@ -369,7 +370,7 @@ module cva6_rvfi
`CONNECT_RVFI_FULL(1'b1, menvcfg, csr.fiom_q)
`CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, menvcfgh, 0)
`CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, menvcfgh, 32'h0)
`CONNECT_RVFI_FULL(1'b1, mvendorid, OPENHWGROUP_MVENDORID)
`CONNECT_RVFI_FULL(1'b1, marchid, ARIANE_MARCHID)

31
corev_apu/tb/ariane_testharness.sv
View file

@ -65,6 +65,8 @@ module ariane_testharness #(
logic init_done;
logic [31:0] jtag_exit, dmi_exit;
logic [31:0] rvfi_exit;
logic [31:0] tracer_exit;
logic [31:0] tandem_exit;
logic jtag_TCK;
logic jtag_TMS;
@ -700,7 +702,7 @@ module ariane_testharness #(
.rst_ni(rst_ni),
.rvfi_i(rvfi_instr),
.rvfi_csr_i(rvfi_csr),
.end_of_test_o(rvfi_exit)
.end_of_test_o(tracer_exit)
);
`ifdef SPIKE_TANDEM
@ -713,11 +715,36 @@ module ariane_testharness #(
.rst_ni,
.clint_tick_i ( rtc_i ),
.rvfi_i ( rvfi_instr ),
.rvfi_csr_i ( rvfi_csr )
.rvfi_csr_i ( rvfi_csr ),
.end_of_test_o ( tandem_exit )
);
initial begin
$display("Running binary in tandem mode");
end
bit tandem_timeout_enable;
bit [31:0] tandem_timeout;
localparam TANDEM_TIMEOUT_THRESHOLD = 60;
// Tandem timeout logic
always_ff @(posedge clk_i) begin
if(tandem_timeout > TANDEM_TIMEOUT_THRESHOLD)
tandem_timeout_enable <= 0;
else if (tracer_exit)
tandem_timeout_enable <= 1;
if (tandem_timeout_enable)
tandem_timeout <= tandem_timeout + 1;
end
always_ff @(posedge clk_i) begin
if (tandem_exit || (tandem_timeout > TANDEM_TIMEOUT_THRESHOLD)) begin
rvfi_exit <= tracer_exit;
end
end
`else
assign rvfi_exit = tracer_exit;
`endif
`ifdef VERILATOR

72
corev_apu/tb/common/spike.sv
View file

@ -41,12 +41,14 @@ module spike #(
input logic rst_ni,
input logic clint_tick_i,
input rvfi_instr_t[CVA6Cfg.NrCommitPorts-1:0] rvfi_i,
input rvfi_csr_t rvfi_csr_i
input rvfi_csr_t rvfi_csr_i,
output logic[31:0] end_of_test_o
);
string binary = "";
string rtl_isa = "";
st_core_cntrl_cfg st;
bit sim_finished;
initial begin
string core_name = "cva6";
@ -73,13 +75,13 @@ module spike #(
st_rvfi s_core [CVA6Cfg.NrCommitPorts-1:0];
bit core_valid [CVA6Cfg.NrCommitPorts-1:0];
`define GET_RVFI_CSR(CSR_ADDR, CSR_NAME, CSR_INDEX) \
s_core[i].csr_valid[CSR_INDEX] <= 1; \
s_core[i].csr_addr [CSR_INDEX] <= CSR_ADDR;\
s_core[i].csr_rdata[CSR_INDEX] <= rvfi_csr_i.``CSR_NAME``.rdata;\
s_core[i].csr_rmask[CSR_INDEX] <= rvfi_csr_i.``CSR_NAME``.rmask;\
s_core[i].csr_wdata[CSR_INDEX] <= rvfi_csr_i.``CSR_NAME``.wdata;\
s_core[i].csr_wmask[CSR_INDEX] <= rvfi_csr_i.``CSR_NAME``.wmask;\
`define GET_RVFI_CSR(CSR_ADDR, CSR_NAME) \
s_core[i].csr_valid[CSR_ADDR] <= 1; \
s_core[i].csr_addr [CSR_ADDR] <= CSR_ADDR;\
s_core[i].csr_rdata[CSR_ADDR] <= rvfi_csr_i.``CSR_NAME``.rdata;\
s_core[i].csr_rmask[CSR_ADDR] <= rvfi_csr_i.``CSR_NAME``.rmask;\
s_core[i].csr_wdata[CSR_ADDR] <= rvfi_csr_i.``CSR_NAME``.wdata;\
s_core[i].csr_wmask[CSR_ADDR] <= rvfi_csr_i.``CSR_NAME``.wmask;
always_ff @(posedge clk_i) begin
if (rst_ni) begin
@ -111,40 +113,48 @@ module spike #(
s_core[i].mem_wdata <= rvfi_i[i].mem_wdata;
`GET_RVFI_CSR (CSR_MSTATUS , mstatus , 0)
`GET_RVFI_CSR (CSR_MCAUSE , mcause , 1)
`GET_RVFI_CSR (CSR_MEPC , mepc , 2)
`GET_RVFI_CSR (CSR_MTVEC , mtvec , 3)
`GET_RVFI_CSR (CSR_MISA , misa , 4)
`GET_RVFI_CSR (CSR_MTVAL , mtval , 5)
`GET_RVFI_CSR (CSR_MIDELEG , mideleg , 6)
`GET_RVFI_CSR (CSR_MEDELEG , medeleg , 7)
`GET_RVFI_CSR (CSR_SATP , satp , 8)
`GET_RVFI_CSR (CSR_MIE , mie , 9)
`GET_RVFI_CSR (CSR_STVEC , stvec , 10)
`GET_RVFI_CSR (CSR_SSCRATCH , sscratch , 11)
`GET_RVFI_CSR (CSR_SEPC , sepc , 12)
`GET_RVFI_CSR (CSR_MSCRATCH , mscratch , 13)
`GET_RVFI_CSR (CSR_STVAL , stval , 14)
`GET_RVFI_CSR (CSR_SCAUSE , scause , 15)
`GET_RVFI_CSR (CSR_PMPCFG0 , pmpcfg0 , 16)
`GET_RVFI_CSR (CSR_PMPCFG1 , pmpcfg1 , 17)
`GET_RVFI_CSR (CSR_PMPCFG2 , pmpcfg2 , 18)
`GET_RVFI_CSR (CSR_PMPCFG3 , pmpcfg3 , 19)
`GET_RVFI_CSR (CSR_MSTATUS , mstatus )
`GET_RVFI_CSR (CSR_MCAUSE , mcause )
`GET_RVFI_CSR (CSR_MEPC , mepc )
`GET_RVFI_CSR (CSR_MTVEC , mtvec )
`GET_RVFI_CSR (CSR_MISA , misa )
`GET_RVFI_CSR (CSR_MTVAL , mtval )
`GET_RVFI_CSR (CSR_MIDELEG , mideleg )
`GET_RVFI_CSR (CSR_MEDELEG , medeleg )
`GET_RVFI_CSR (CSR_SATP , satp )
`GET_RVFI_CSR (CSR_MIE , mie )
`GET_RVFI_CSR (CSR_STVEC , stvec )
`GET_RVFI_CSR (CSR_SSCRATCH , sscratch )
`GET_RVFI_CSR (CSR_SEPC , sepc )
`GET_RVFI_CSR (CSR_MSCRATCH , mscratch )
`GET_RVFI_CSR (CSR_STVAL , stval )
`GET_RVFI_CSR (CSR_SCAUSE , scause )
`GET_RVFI_CSR (CSR_PMPCFG0 , pmpcfg0 )
`GET_RVFI_CSR (CSR_PMPCFG1 , pmpcfg1 )
`GET_RVFI_CSR (CSR_PMPCFG2 , pmpcfg2 )
`GET_RVFI_CSR (CSR_PMPCFG3 , pmpcfg3 )
for (int j = 0; j < 16; j++) begin
`GET_RVFI_CSR (CSR_PMPADDR0 + j , pmpaddr[j] , 20 + j)
`GET_RVFI_CSR (CSR_PMPADDR0 + j , pmpaddr[j])
end
`GET_RVFI_CSR (CSR_MINSTRET , instret , 37)
`GET_RVFI_CSR (CSR_MINSTRET , instret )
`GET_RVFI_CSR (CSR_MINSTRETH , instreth )
`GET_RVFI_CSR (CSR_MSTATUSH , mstatush )
`GET_RVFI_CSR (CSR_MIP , mip )
`GET_RVFI_CSR (CSR_MCYCLE , mcycle )
end
else begin
core_valid[i] <= 0;
end
if (core_valid[i]) begin
if (core_valid[i] && !sim_finished) begin
st_rvfi core, reference_model;
core = s_core[i];
rvfi_spike_step(core, reference_model);
rvfi_compare(core, reference_model);
end_of_test_o = reference_model.halt;
sim_finished = reference_model.halt[0];
end
end
end

7
corev_apu/tb/rvfi_tracer.sv
View file

@ -70,8 +70,9 @@ module rvfi_tracer #(
logic[31:0] end_of_test_d;
assign end_of_test_o = end_of_test_d;
always_ff @(posedge clk_i) begin
end_of_test_q = (rst_ni && (end_of_test_d[0] == 1'b1)) ? end_of_test_d : 0;
end_of_test_q <= (rst_ni && (end_of_test_d[0] == 1'b1)) ? end_of_test_d : 0;
for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
pc64 = {{CVA6Cfg.XLEN-CVA6Cfg.VLEN{rvfi_i[i].pc_rdata[CVA6Cfg.VLEN-1]}}, rvfi_i[i].pc_rdata};
// print the instruction information if the instruction is valid or a trap is taken
@ -111,7 +112,7 @@ module rvfi_tracer #(
if (TOHOST_ADDR != '0 &&
rvfi_i[i].mem_paddr == TOHOST_ADDR &&
rvfi_i[i].mem_wdata[0] == 1'b1) begin
end_of_test_q = rvfi_i[i].mem_wdata[31:0];
end_of_test_q <= rvfi_i[i].mem_wdata[31:0];
end
end
end
@ -138,7 +139,7 @@ module rvfi_tracer #(
else
cycles <= cycles+1;
if (cycles > SIM_FINISH)
end_of_test_q = 32'hffff_ffff;
end_of_test_q <= 32'hffff_ffff;
end_of_test_d <= end_of_test_q;
end

2
verif/core-v-verif

@ -1 +1 @@
Subproject commit 399438e92ae9dc0b94b97bfd764d34ac865c1b07
Subproject commit 4a70806f3cd8ddb5d693f4bfb99d16a4fbd2a15e

8
verif/env/uvme/uvme_cva6_cfg.sv vendored
View file

@ -32,7 +32,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
rand bit enabled;
rand bit scoreboard_enabled;
rand bit spike_tandem_enabled;
rand bit tandem_enabled;
rand bit cov_model_enabled;
rand bit cov_cvxif_model_enabled;
rand bit cov_isa_model_enabled;
@ -60,7 +60,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
`uvm_field_int ( enabled , UVM_DEFAULT )
`uvm_field_enum(uvm_active_passive_enum, is_active , UVM_DEFAULT )
`uvm_field_int ( scoreboard_enabled , UVM_DEFAULT )
`uvm_field_int ( spike_tandem_enabled , UVM_DEFAULT )
`uvm_field_int ( tandem_enabled , UVM_DEFAULT )
`uvm_field_int ( cov_model_enabled , UVM_DEFAULT )
`uvm_field_int ( trn_log_enabled , UVM_DEFAULT )
`uvm_field_int ( ext_zicond_supported , UVM_DEFAULT )
@ -187,7 +187,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
isacov_cfg.reg_crosses_enabled == 0;
isacov_cfg.reg_hazards_enabled == 1;
rvfi_cfg.nret == CVA6Cfg.NrCommitPorts;
rvfi_cfg.unified_exceptions == 0;
unified_traps == 0;
if (is_active == UVM_ACTIVE) {
clknrst_cfg.is_active == UVM_ACTIVE;
@ -244,6 +244,8 @@ function uvme_cva6_cfg_c::new(string name="uvme_cva6_cfg");
isacov_cfg.core_cfg = this;
rvfi_cfg.core_cfg = this;
$value$plusargs("core_name=%s", this.core_name);
endfunction : new
function void uvme_cva6_cfg_c::sample_parameters(uvma_core_cntrl_cntxt_c cntxt);

8
verif/env/uvme/uvme_cva6_env.sv vendored
View file

@ -178,8 +178,8 @@ function void uvme_cva6_env_c::build_phase(uvm_phase phase);
cntxt = uvme_cva6_cntxt_c::type_id::create("cntxt");
end
if ($test$plusargs("spike_tandem_enabled"))
$value$plusargs("spike_tandem_enabled=%b",cfg.spike_tandem_enabled);
if ($test$plusargs("tandem_enabled"))
$value$plusargs("tandem_enabled=%b",cfg.tandem_enabled);
retrieve_vif();
assign_cfg ();
@ -283,7 +283,7 @@ endfunction: create_agents
function void uvme_cva6_env_c::create_env_components();
if (cfg.spike_tandem_enabled) begin
if (cfg.tandem_enabled) begin
reference_model = uvmc_rvfi_reference_model#(ILEN,XLEN)::type_id::create("reference_model", this);
end
@ -338,7 +338,7 @@ function void uvme_cva6_env_c::connect_scoreboard();
// TODO Connect predictor -> scoreboard
// Ex: predictor.debug_ap.connect(sb.debug_sb.exp_export);
if (cfg.spike_tandem_enabled) begin
if (cfg.tandem_enabled) begin
rvfi_agent.rvfi_core_ap.connect(sb.m_rvfi_scoreboard.m_imp_core);
rvfi_agent.rvfi_core_ap.connect(reference_model.m_analysis_imp);
reference_model.m_analysis_port.connect(sb.m_rvfi_scoreboard.m_imp_reference_model);

3
verif/env/uvme/uvme_cva6_sb.sv vendored
View file

@ -171,7 +171,8 @@ function void uvme_cva6_sb_c::create_sbs();
// TODO Implement uvme_cva6_sb_c::create_sbs()
// Ex: egress_sb = uvme_cva6_sb_simplex_c::type_id::create("egress_sb" , this);
// ingress_sb = uvme_cva6_sb_simplex_c::type_id::create("ingress_sb", this);
m_rvfi_scoreboard = uvmc_rvfi_scoreboard_c#(ILEN,XLEN)::type_id::create("m_rvfi_scoreboard", this);
if (cfg.tandem_enabled)
m_rvfi_scoreboard = uvmc_rvfi_scoreboard_c#(ILEN,XLEN)::type_id::create("m_rvfi_scoreboard", this);
endfunction : create_sbs

110
verif/sim/Makefile
View file

@ -141,48 +141,6 @@ spike:
$(tool_path)/spike $(spike_stepout) $(spike_extension) --log-commits --isa=$(variant) --priv=$(priv) $(spike_params) -l $(elf)
cp $(log).iss $(log)
###############################################################################
# testharness specific commands, variables
###############################################################################
vcs-testharness:
make -C $(path_var) work-dpi/ariane_dpi.so
make -C $(path_var) vcs_build target=$(target) defines=$(subst +define+,,$(isscomp_opts))$(if $(spike-tandem),SPIKE_TANDEM=1)
$(path_var)/work-vcs/simv $(if $(VERDI), -verdi -do $(path_var)/util/init_testharness.do,) +permissive \
+tohost_addr=$(shell $$RISCV/bin/${CV_SW_PREFIX}nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \
$(spike-yaml-plusarg) \
+elf_file=$(elf) +permissive-off ++$(elf) $(issrun_opts) \
$(if $(spike-tandem),-sv_lib $(SPIKE_INSTALL_DIR)/lib/libdisasm) \
$(if $(spike-tandem),-sv_lib $(SPIKE_INSTALL_DIR)/lib/libriscv) \
-sv_lib $(SPIKE_INSTALL_DIR)/lib/libfesvr
# If present, move default waveform files to log directory.
# Keep track of target in waveform file name.
[ ! -f novas.vpd ] || \
mv novas.vpd `dirname $(log)`/`basename $(log) .log`.vpd
[ ! -f novas.fsdb ] || \
mv novas.fsdb `dirname $(log)`/`basename $(log) .log`.fsdb
# Generate disassembled log.
$(tool_path)/spike-dasm --isa=$(variant) < ./trace_rvfi_hart_00.dasm > $(log)
grep $(isspostrun_opts) ./trace_rvfi_hart_00.dasm
veri-testharness:
make -C $(path_var) verilate verilator="verilator --no-timing" target=$(target) defines=$(subst +define+,,$(isscomp_opts))
$(path_var)/work-ver/Variane_testharness $(if $(TRACE_COMPACT), -f verilator.fst) $(if $(TRACE_FAST), -v verilator.vcd) $(elf) $(issrun_opts) \
$(COMMON_PLUS_ARGS)
# If present, move default waveform files to log directory.
# Keep track of target in waveform file name.
[ ! -f verilator.fst ] || mv verilator.fst `dirname $(log)`/`basename $(log) .log`.fst
[ ! -f verilator.vcd ] || mv verilator.vcd `dirname $(log)`/`basename $(log) .log`.vcd
# Generate disassembled log.
$(tool_path)/spike-dasm --isa=$(variant) < ./trace_rvfi_hart_00.dasm > $(log)
grep $(isspostrun_opts) ./trace_rvfi_hart_00.dasm
questa-testharness:
mkdir -p $(path_var)/tmp
make -C $(path_var) sim target=$(target) defines=$(subst +define+,,$(isscomp_opts)) batch-mode=1 elf_file=$(elf) \
# TODO: Add support for waveform collection.
$(tool_path)/spike-dasm --isa=$(variant) < $(path_var)/trace_rvfi_hart_00.dasm > $(log)
grep $(isspostrun_opts) $(path_var)/trace_rvfi_hart_00.dasm
###############################################################################
# UVM specific commands, variables
###############################################################################
@ -234,31 +192,23 @@ COMMON_PLUS_ARGS = \
+elf_file=$(elf) \
$(spike-yaml-plusarg) \
+tohost_addr=$(shell $$RISCV/bin/$(CV_SW_PREFIX)nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \
+signature=$(elf).signature_output +UVM_TESTNAME=uvmt_cva6_firmware_test_c
ifneq ($(UVM_VERBOSITY),)
COMMON_PLUS_ARGS += +UVM_VERBOSITY=$(UVM_VERBOSITY)
endif
COMMON_RUN_UVM_FLAGS = \
-sv_lib $(SPIKE_INSTALL_DIR)/lib/libriscv \
-sv_lib $(SPIKE_INSTALL_DIR)/lib/libfesvr \
-sv_lib $(SPIKE_INSTALL_DIR)/lib/libdisasm \
++$(elf) \
+elf_file=$(elf) \
+signature=$(elf).signature_output +UVM_TESTNAME=uvmt_cva6_firmware_test_c \
$(spike-yaml-plusarg) \
+tohost_addr=$(shell $$RISCV/bin/$(CV_SW_PREFIX)nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \
+signature=$(elf).signature_output +UVM_TESTNAME=uvmt_cva6_firmware_test_c
ifneq ($(UVM_VERBOSITY),)
COMMON_PLUS_ARGS += +UVM_VERBOSITY=$(UVM_VERBOSITY)
endif
COMMON_RUN_UVM_FLAGS = \
+UVM_TESTNAME=uvmt_cva6_firmware_test_c \
+report_file=$(log).yaml +core_name=$(target)
COMMON_RUN_ARGS = \
$(COMMON_PLUS_ARGS) $(issrun_opts) \
-sv_lib $(SPIKE_INSTALL_DIR)/lib/libcustomext \
-sv_lib $(SPIKE_INSTALL_DIR)/lib/libriscv \
-sv_lib $(SPIKE_INSTALL_DIR)/lib/libfesvr \
-sv_lib $(SPIKE_INSTALL_DIR)/lib/libdisasm \
$(COMMON_PLUS_ARGS)
-sv_lib $(SPIKE_INSTALL_DIR)/lib/libdisasm
ALL_UVM_FLAGS = -lca -sverilog +incdir+$(VCS_HOME)/etc/uvm/src \
$(VCS_HOME)/etc/uvm/src/uvm_pkg.sv -ntb_opts uvm-1.2 -timescale=1ns/1ps \
@ -287,9 +237,9 @@ ifneq ($(DEBUG),) # If RTL DEBUG support requested
endif
ifneq ($(SPIKE_TANDEM),)
COMMON_RUN_UVM_FLAGS += +spike_tandem_enabled=1
COMMON_RUN_ARGS += +tandem_enabled=1
else
COMMON_RUN_UVM_FLAGS += +spike_tandem_enabled=0
COMMON_RUN_ARGS += +tandem_enabled=0
endif
vcs_uvm_comp:
@ -305,7 +255,7 @@ vcs_uvm_run: vcs_uvm_comp
$(if $(TRACE_FAST), unset VERDI_HOME ;) \
cd $(VCS_WORK_DIR)/ && \
$(VCS_WORK_DIR)/simv \
$(COMMON_RUN_UVM_FLAGS) \
$(COMMON_RUN_ARGS) \
$(ALL_SIMV_UVM_FLAGS) \
$(cov-run-opt) $(issrun_opts)
@ -344,7 +294,7 @@ questa_uvm_comp:
questa_uvm_run:
@echo "[QUESTA] Running Model"
vsim -64 \
$(COMMON_RUN_UVM_FLAGS) \
$(COMMON_RUN_ARGS) \
-sv_lib $(QUESTASIM_HOME)/uvm-1.2/linux_x86_64/uvm_dpi \
-c -do "run -all; " \
-work $(VSIM_WORK_DIR) -t 1ns \
@ -372,6 +322,42 @@ vcs_clean_all:
@echo "[VCS] Cleanup (entire vcs_work dir)"
rm -rf $(CVA6_REPO_DIR)/verif/sim/vcs_results/ verdiLog/ simv* *.daidir *.vpd *.fsdb *.db csrc ucli.key vc_hdrs.h novas* inter.fsdb uart
###############################################################################
# testharness specific commands, variables
###############################################################################
vcs-testharness:
make -C $(path_var) vcs_build target=$(target) defines=$(subst +define+,,$(isscomp_opts))$(if $(spike-tandem),SPIKE_TANDEM=1)
$(path_var)/work-vcs/simv $(if $(VERDI), -verdi -do $(path_var)/util/init_testharness.do,) +permissive \
+permissive-off $(COMMON_RUN_ARGS)
# If present, move default waveform files to log directory.
# Keep track of target in waveform file name.
[ ! -f novas.vpd ] || \
mv novas.vpd `dirname $(log)`/`basename $(log) .log`.vpd
[ ! -f novas.fsdb ] || \
mv novas.fsdb `dirname $(log)`/`basename $(log) .log`.fsdb
# Generate disassembled log.
$(tool_path)/spike-dasm --isa=$(variant) < ./trace_rvfi_hart_00.dasm > $(log)
grep $(isspostrun_opts) ./trace_rvfi_hart_00.dasm
veri-testharness:
make -C $(path_var) verilate verilator="verilator --no-timing" target=$(target) defines=$(subst +define+,,$(isscomp_opts))
$(path_var)/work-ver/Variane_testharness $(if $(TRACE_COMPACT), -f verilator.fst) $(if $(TRACE_FAST), -v verilator.vcd) $(elf) $(issrun_opts) \
$(COMMON_PLUS_ARGS)
# If present, move default waveform files to log directory.
# Keep track of target in waveform file name.
[ ! -f verilator.fst ] || mv verilator.fst `dirname $(log)`/`basename $(log) .log`.fst
[ ! -f verilator.vcd ] || mv verilator.vcd `dirname $(log)`/`basename $(log) .log`.vcd
# Generate disassembled log.
$(tool_path)/spike-dasm --isa=$(variant) < ./trace_rvfi_hart_00.dasm > $(log)
grep $(isspostrun_opts) ./trace_rvfi_hart_00.dasm
questa-testharness:
mkdir -p $(path_var)/tmp
make -C $(path_var) sim target=$(target) defines=$(subst +define+,,$(isscomp_opts)) batch-mode=1 elf_file=$(elf) \
# TODO: Add support for waveform collection.
$(tool_path)/spike-dasm --isa=$(variant) < $(path_var)/trace_rvfi_hart_00.dasm > $(log)
grep $(isspostrun_opts) $(path_var)/trace_rvfi_hart_00.dasm
###############################################################################
# Common targets and rules
###############################################################################

30
verif/sim/cva6.py
View file

@ -24,6 +24,7 @@ import sys
import logging
import subprocess
import datetime
import yaml
from dv.scripts.lib import *
from verilator_log_to_trace_csv import *
@ -463,6 +464,7 @@ def run_assembly(asm_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, outp
log = ("%s/%s_sim/%s_%d.%s.log" % (output_dir, iss, test_log_name, test_iteration, target))
else:
log = ("%s/%s_sim/%s.%s.log" % (output_dir, iss, test_log_name, target))
yaml = ("%s/%s_sim/%s.%s.log.yaml" % (output_dir, iss, test_log_name, target))
log_list.append(log)
base_cmd = parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd, priv, spike_params)
cmd = get_iss_cmd(base_cmd, elf, target, log)
@ -471,6 +473,9 @@ def run_assembly(asm_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, outp
else: ratio = 1
run_cmd(cmd, iss_timeout//ratio, debug_cmd = debug_cmd)
logging.info("[%0s] Running ISS simulation: %s ...done" % (iss, elf))
if (iss != "spike" and os.environ.get('SPIKE_TANDEM') != None):
analize_result_yaml(yaml)
if len(iss_list) == 2:
compare_iss_log(iss_list, log_list, report)
@ -505,6 +510,21 @@ def run_assembly_from_dir(asm_test_dir, iss_yaml, isa, mabi, gcc_opts, iss,
else:
logging.error("No assembly test(*.S) found under %s" % asm_test_dir)
def analize_result_yaml(yaml_path):
if (os.path.exists(yaml_path)):
with open(yaml_path, 'r') as f:
data = yaml.safe_load(f)
mismatches = data["mismatches"]
mismatches_count = (data["mismatches_count"])
instr_count = (data["instr_count"])
matches_count = instr_count - mismatches_count
logging.info("TANDEM Result : %s with %s mismatches and %s matches"
% (data["exit_cause"], mismatches_count, matches_count))
else:
logging.info("TANDEM YAML not found")
# python3 run.py --target rv64gc --iss=spike,verilator --elf_tests bbl.o
def run_elf(c_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir,
setting_dir, debug_cmd, priv, spike_params, iss_timeout=50000):
@ -541,7 +561,8 @@ def run_elf(c_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir,
# ISS simulation
for iss in iss_list:
run_cmd("mkdir -p %s/%s_sim" % (output_dir, iss))
log = ("%s/%s_sim/%s.%s.log" % (output_dir, iss, c, target))
log = ("%s/%s_sim/%s.%s.log" % (output_dir, iss, c, target))
yaml = ("%s/%s_sim/%s.%s.log.yaml" % (output_dir, iss, c, target))
log_list.append(log)
base_cmd = parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd, priv, spike_params)
cmd = get_iss_cmd(base_cmd, elf, target, log)
@ -551,10 +572,10 @@ def run_elf(c_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir,
else: ratio = 1
run_cmd(cmd, int(iss_timeout*ratio), debug_cmd = debug_cmd)
logging.info("[%0s] Running ISS simulation: %s ...done" % (iss, elf))
if len(iss_list) == 2:
compare_iss_log(iss_list, log_list, report)
def run_c(c_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir,
setting_dir, debug_cmd, linker, priv, spike_params, test_name = None, iss_timeout=500):
"""Run a directed c test with ISS
@ -606,6 +627,7 @@ def run_c(c_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir,
log = ("%s/%s_sim/%s_%d.%s.log" % (output_dir, iss, test_log_name, test_iteration, target))
else:
log = ("%s/%s_sim/%s.%s.log" % (output_dir, iss, test_log_name, target))
yaml = ("%s/%s_sim/%s.%s.log.yaml" % (output_dir, iss, test_log_name, target))
log_list.append(log)
base_cmd = parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd, priv, spike_params)
cmd = get_iss_cmd(base_cmd, elf, target, log)
@ -614,6 +636,10 @@ def run_c(c_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir,
else: ratio = 1
run_cmd(cmd, iss_timeout//ratio, debug_cmd = debug_cmd)
logging.info("[%0s] Running ISS simulation: %s ...done" % (iss, elf))
if (iss != "spike" and os.environ.get('SPIKE_TANDEM') != None):
analize_result_yaml(yaml)
if len(iss_list) == 2:
compare_iss_log(iss_list, log_list, report)

2
verif/tb/core/custom_uvm_macros.svh
View file

@ -67,7 +67,7 @@ function void uvm_report_info(string id,
string filename = "",
int line = 0);
if (verbosity <= current_verbosity_level)
$display($sformatf("UVM_INFO @ %t ns : %s %s", $time, id, message));
$display($sformatf("UVM_INFO @ %t ns : %s %s", $time, id, message));
endfunction

1
verif/tb/core/uvma_core_cntrl_pkg.sv
View file

@ -6,6 +6,7 @@ package uvma_core_cntrl_pkg;
// Constants / Structs / Enums
`include "uvma_core_cntrl_constants.sv"
`include "uvma_core_cntrl_tdefs.sv"
`include "uvma_core_cntrl_utils.sv"
endpackage : uvma_core_cntrl_pkg

102
verif/tb/core/uvma_cva6pkg_utils.sv
View file

@ -1,54 +1,82 @@
import "DPI-C" function void spike_set_param_uint64_t(string base, string name, longint unsigned value);
import "DPI-C" function void spike_set_param_str(string base, string name, string value);
import "DPI-C" function void spike_set_param_bool(string base, string name, bit value);
import "DPI-C" function void spike_set_default_params(string profile);
function st_core_cntrl_cfg cva6pkg_to_core_cntrl_cfg(st_core_cntrl_cfg base);
function st_core_cntrl_cfg cva6pkg_to_core_cntrl_cfg(st_core_cntrl_cfg cfg);
automatic config_pkg::cva6_cfg_t CVA6Cfg = build_config_pkg::build_config(cva6_config_pkg::cva6_cfg);
string base;
$cast(base.xlen, CVA6Cfg.XLEN);
$cast(cfg.xlen, CVA6Cfg.XLEN);
base.ilen = 32;
cfg.ilen = 32;
base.ext_i_supported = 1;
base.ext_a_supported = CVA6Cfg.RVA;
base.ext_m_supported = 1;
base.ext_c_supported = CVA6Cfg.RVC;
base.ext_p_supported = 1;
base.ext_v_supported = CVA6Cfg.RVV;
base.ext_f_supported = CVA6Cfg.RVF;
base.ext_d_supported = CVA6Cfg.RVD;
base.ext_zba_supported = CVA6Cfg.RVB;
base.ext_zbb_supported = CVA6Cfg.RVB;
base.ext_zbc_supported = CVA6Cfg.RVB;
base.ext_zbe_supported = CVA6Cfg.RVB;
base.ext_zbf_supported = 0;
base.ext_zbm_supported = 0;
base.ext_zbp_supported = 0;
base.ext_zbr_supported = 0;
base.ext_zbs_supported = CVA6Cfg.RVB;
base.ext_zbt_supported = 0;
base.ext_zcb_supported = CVA6Cfg.RVZCB;
base.ext_zifencei_supported = 1;
base.ext_zicsr_supported = 1;
base.ext_zicntr_supported = 1;
cfg.marchid = ariane_pkg::ARIANE_MARCHID;
cfg.mvendorid = ariane_pkg::OPENHWGROUP_MVENDORID;
base.mode_s_supported = CVA6Cfg.RVS;
base.mode_u_supported = CVA6Cfg.RVU;
cfg.ext_i_supported = 1;
cfg.ext_a_supported = CVA6Cfg.RVA;
cfg.ext_m_supported = 1;
cfg.ext_c_supported = CVA6Cfg.RVC;
cfg.ext_p_supported = 1;
cfg.ext_v_supported = CVA6Cfg.RVV;
cfg.ext_f_supported = CVA6Cfg.RVF;
cfg.ext_d_supported = CVA6Cfg.RVD;
cfg.ext_zba_supported = CVA6Cfg.RVB;
cfg.ext_zbb_supported = CVA6Cfg.RVB;
cfg.ext_zbc_supported = CVA6Cfg.RVB;
cfg.ext_zbe_supported = CVA6Cfg.RVB;
cfg.ext_zbf_supported = 0;
cfg.ext_zbm_supported = 0;
cfg.ext_zbp_supported = 0;
cfg.ext_zbr_supported = 0;
cfg.ext_zbs_supported = CVA6Cfg.RVB;
cfg.ext_zbt_supported = 0;
cfg.ext_zcb_supported = CVA6Cfg.RVZCB;
cfg.ext_zifencei_supported = 1;
cfg.ext_zicsr_supported = 1;
cfg.ext_zicntr_supported = 1;
base.pmp_supported = (CVA6Cfg.NrPMPEntries > 0);
base.pmp_regions = CVA6Cfg.NrPMPEntries;
base.debug_supported = CVA6Cfg.DebugEn;
cfg.ext_cv32a60x_supported = 1;
// FIXME TODO: Temporary solution. We need explicit info on memory map.
// FORNOW The solution below relies on specific region ordering.
base.dram_base = CVA6Cfg.ExecuteRegionAddrBase[2];
base.dram_size = CVA6Cfg.ExecuteRegionLength[2];
base.dram_valid = 1;
cfg.dram_base = CVA6Cfg.ExecuteRegionAddrBase[2];
cfg.dram_size = CVA6Cfg.ExecuteRegionLength[2];
cfg.dram_valid = 1;
base.disable_all_csr_checks = 0;
cfg.disable_all_csr_checks = 0;
cfg.mode_s_supported = CVA6Cfg.RVS;
cfg.mode_u_supported = CVA6Cfg.RVU;
base.unsupported_csr_mask['h643] = 1; // HTVAL
base.unsupported_csr_mask['h64A] = 1; // HTINST
cfg.pmp_supported = (CVA6Cfg.NrPMPEntries > 0);
cfg.pmp_regions = CVA6Cfg.NrPMPEntries;
cfg.debug_supported = CVA6Cfg.DebugEn;
return base;
cfg.unsupported_csr_mask['h643] = 1; // HTVAL
cfg.unsupported_csr_mask['h64A] = 1; // HTINST
// Disable comparison
cfg.unsupported_csr_mask['h7C0] = 1; // ICACHE
cfg.unsupported_csr_mask['h7C1] = 1; // DCACHE
// MHPMEVENT
for (int unsigned i = 32'h323; i < 32'h33F; i++)
cfg.unsupported_csr_mask[i] = 1;
base = $sformatf("/top/core/%0d/", cfg.mhartid);
void'(spike_set_param_bool(base, "hide_csrs_based_on_priv", 1));
void'(spike_set_param_uint64_t(base, "mtvec_vectored_alignment", 64 * 4));
void'(spike_set_param_str(base, "extensions", "cv32a60x"));
void'(spike_set_param_bool(base, "status_xs_field_we_enable", 1'b1));
void'(spike_set_param_bool(base, "status_xs_field_we", 1'b0));
void'(spike_set_param_uint64_t(base, "misa_override_value", get_misa(cfg)));
void'(spike_set_param_uint64_t(base, "misa_override_mask", 64'h0FFF_FFFF));
return cfg;
endfunction : cva6pkg_to_core_cntrl_cfg

1
verif/tb/core/uvma_cva6pkg_utils_pkg.sv
View file

@ -3,6 +3,7 @@
package uvma_cva6pkg_utils_pkg;
import ariane_pkg::*;
import cva6_config_pkg::*;
import uvma_core_cntrl_pkg::*;
`include "uvma_cva6pkg_utils.sv"