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fixup! Adds cacheable region rules to the configuration script, modify instruction traces such that it can be used with VCS

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This commit is contained in:
Florian Zaruba 2019-04-26 12:02:14 +02:00
parent 5797e0f6e2
commit d71c8ff69b
1 changed files with 3 additions and 2 deletions
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5
Makefile
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@ -456,12 +456,13 @@ check-torture:
diff -s $(riscv-torture-dir)/$(test-location).spike.sig $(riscv-torture-dir)/$(test-location).rtlsim.sig
fpga_filter := $(addprefix $(root-dir), bootrom/bootrom.sv)
fpga_filter += $(addprefix $(root-dir), src/util/instruction_tracer.sv)
fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(util) $(uart_src)
fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src)
@echo "[FPGA] Generate sources"
@echo read_vhdl {$(uart_src)} > fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(ariane_pkg)} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(util)} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(util))} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl
@echo "[FPGA] Generate Bitstream"