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[Skip CI] Various user's guide edits (#1201)

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* Add mention to a single hart core

Mentions CVA6 has a single hart + minor edit.

* Update Custom_Instructions.rst

Minor edit.
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Jérôme Quévremont 2023-04-19 18:33:24 +02:00 • committed by GitHub
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6
docs/01_cva6_user/Custom_Instructions.rst
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@ -20,6 +20,8 @@
Custom RISC-V instructions
==========================
Desired for step2 verification.
This is mostly for FENCE.T.
As of now, CVA6 does not implement custom RISC-V instructions.
The team is looking for contributors to implement the ``fence.t`` instruction that ensures that the execution time of subsequent instructions is unrelated with predecessor instructions.
The user or integrator can also use the CV-X-IF coprocessor interface to implement their own extensions, without modifying the core.

10
docs/01_cva6_user/Programmer_View.rst
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@ -20,7 +20,7 @@
Programmer’s View
=================
In each section, we must make clear when a feature is variable upon parameters
RISC-V specifications allow many variations. This chapter provides more details about RISC-V variants available for the programmer.
RISC-V Extensions
-----------------
@ -52,5 +52,11 @@ Notes for the integrator:
Memory Alignment
----------------
CVA6 does not support non-aligned memory accesses.
CVA6 **does not support non-aligned** memory accesses.
Harts
-----
CVA6 features a **single hart**, i.e. a single hardware thread.
Therefore the words *hart* and *core* have the same meaning in this guide.