Add register file to gf22 target for synthesis

src/fifo.sv

@@ -111,4 +111,4 @@ module fifo #(
     end
     `endif
     `endif
-endmodule
+endmodule

src/store_buffer.sv

@@ -179,6 +179,7 @@ module store_buffer (
         page_offset_matches_o = 1'b0;
         // check if the LSBs are identical and the entry is valid
         for (int unsigned i = 0; i < DEPTH; i++) begin
+            // Check if the page offset matches and whether the entry is valid
             if ((page_offset_i[11:3] == commit_queue_q[i].address[11:3]) && commit_queue_q[i].valid) begin
                 page_offset_matches_o = 1'b1;
                 break;
@@ -219,4 +220,4 @@ module store_buffer (
         else $error ("You are trying to commit and flush in the same cycle");
     `endif
     `endif
-endmodule
+endmodule

src_files.yml

@@ -41,6 +41,7 @@ ariane:
 riscv_regfile_rtl:
   targets: [
     rtl,
+    gf22,
   ]
   incdirs: [
     include,