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🐛 Flush pipeline after return from exception

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This commit is contained in:
Florian Zaruba 2017-06-03 17:50:35 +02:00
parent 7c6b982a59
commit d946c1491d
2 changed files with 21 additions and 7 deletions
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7
src/ariane.sv
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@ -89,6 +89,7 @@ module ariane
exception ex_commit; // exception from commit stage
branchpredict resolved_branch;
logic [63:0] pc_commit;
logic eret;
// --------------
// PCGEN <-> IF
// --------------
@ -104,7 +105,6 @@ module ariane
// --------------
logic [63:0] trap_vector_base_commit_pcgen;
logic [63:0] epc_commit_pcgen;
logic eret_commit_pcgen;
// --------------
// IF <-> ID
// --------------
@ -234,7 +234,7 @@ module ariane
.boot_addr_i ( boot_addr_i ),
.pc_commit_i ( pc_commit ),
.epc_i ( epc_commit_pcgen ),
.eret_i ( eret_commit_pcgen ),
.eret_i ( eret ),
.trap_vector_base_i ( trap_vector_base_commit_pcgen ),
.ex_i ( ex_commit ),
.*
@ -425,7 +425,7 @@ module ariane
.csr_exception_o ( csr_exception_csr_commit ),
.irq_enable_o ( ),
.epc_o ( epc_commit_pcgen ),
.eret_o ( eret_commit_pcgen ),
.eret_o ( eret ),
.trap_vector_base_o ( trap_vector_base_commit_pcgen ),
.priv_lvl_o ( priv_lvl ),
@ -448,6 +448,7 @@ module ariane
.flush_id_o ( flush_ctrl_id ),
.flush_ex_o ( flush_ctrl_ex ),
.eret_i ( eret ),
.ex_i ( ex_commit ),
.flush_csr_i ( flush_csr_ctrl ),
.resolved_branch_i ( resolved_branch ),

21
src/controller.sv
View file

@ -30,9 +30,10 @@ module controller (
output logic flush_id_o, // flush ID stage
output logic flush_ex_o, // flush EX stage
input exception ex_i, // we got an exception, flush the pipeline
input branchpredict resolved_branch_i, // we got a resolved branch, check if we need to flush the front-end
input logic flush_csr_i // we got an instruction which altered the CSR, flush the pipeline
input logic eret_i, // return from exception
input exception ex_i, // we got an exception, flush the pipeline
input branchpredict resolved_branch_i, // we got a resolved branch, check if we need to flush the front-end
input logic flush_csr_i // we got an instruction which altered the CSR, flush the pipeline
);
// flush branch prediction
assign flush_bp_o = 1'b0;
@ -62,7 +63,8 @@ module controller (
// Exception
// ------------
if (ex_i.valid) begin
// don't flush pcgen as we want to take the exception
// don't flush pcgen as we want to take the exception, flush pcgen is not a flush signal
// for the PC GEN stage but instead tells it to take the PC we gave it
flush_pcgen_o = 1'b0;
flush_if_o = 1'b1;
flush_id_o = 1'b1;
@ -79,6 +81,17 @@ module controller (
flush_ex_o = 1'b1;
end
// ----------------------
// Return from exception
// ----------------------
if (eret_i) begin
// don't flush pcgen as we want to take the exception
flush_pcgen_o = 1'b0;
flush_if_o = 1'b1;
flush_id_o = 1'b1;
flush_ex_o = 1'b1;
end
end
// flush on exception
endmodule