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Ethernet preparation, fpga fixes

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This commit is contained in:
Florian Zaruba 2018-11-20 19:02:52 +01:00
parent bb821300f1
commit db4f99e2ad
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GPG key ID: E742FFE8EC38A792
18 changed files with 129 additions and 158 deletions
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6
fpga/constraints/genesys-2.xdc
View file

@ -54,10 +54,10 @@ set_property -dict {PACKAGE_PIN AJ13 IOSTANDARD LVCMOS15} [get_ports { eth_rxd[3
set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS15} [get_ports { eth_txck }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS15} [get_ports { eth_mdc }]; #IO_L23P_T3_33 Sch=eth_mdc
set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS15} [get_ports { eth_mdio }]; #IO_L23N_T3_33 Sch=eth_mdio
set_property -dict {PACKAGE_PIN AH11 IOSTANDARD LVCMOS15} [get_ports { eth_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl
#set_property -dict { PACKAGE_PIN AK15 IOSTANDARD LVCMOS18 } [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb
#set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS15 } [get_ports { eth_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl
#set_property -dict { PACKAGE_PIN AK16 IOSTANDARD LVCMOS18 } [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb
# set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS18} [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb
# set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVCMOS18} [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb
## SD Card
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS33} [get_ports spi_clk_o]

17
fpga/scripts/run.tcl
View file

@ -22,6 +22,7 @@ set_property board_part $::env(XILINX_BOARD) [current_project]
# set number of threads to 8 (maximum, unfortunately)
set_param general.maxThreads 8
set_msg_config -id {[Synth 8-5858]} -new_severity "info"
# hard-coded to Genesys 2 for the moment
add_files -fileset constrs_1 -norecurse constraints/genesys-2.xdc
@ -37,7 +38,7 @@ source scripts/add_sources.tcl
set_property top ariane_xilinx [current_fileset]
if {$board eq "genesys2"} {
if {$::env(BOARD) eq "genesys2"} {
read_verilog -sv {src/genesysii.svh}
set file "src/genesysii.svh"
} else {
@ -80,14 +81,14 @@ wait_on_run impl_1
open_run impl_1
# output Verilog netlist + SDC for timing simulation
write_verilog -force -mode funcsim work-fpga/$project_funcsim.v
write_verilog -force -mode timesim work-fpga/$project_timesim.v
write_sdf -force work-fpga/$project_timesim.sdf
write_verilog -force -mode funcsim work-fpga/${project}_funcsim.v
write_verilog -force -mode timesim work-fpga/${project}_timesim.v
write_sdf -force work-fpga/${project}_timesim.sdf
# reports
exec mkdir -p reports/
exec rm -rf reports/*
check_timing -file reports/$project.check_timing.rpt
report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/$project.timing_WORST_100.rpt
report_timing -nworst 1 -delay_type max -sort_by group -file reports/$project.timing.rpt
report_utilization -hierarchical -file reports/$project.utilization.rpt
check_timing -file reports/${project}.check_timing.rpt
report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/${project}.timing_WORST_100.rpt
report_timing -nworst 1 -delay_type max -sort_by group -file reports/${project}.timing.rpt
report_utilization -hierarchical -file reports/${project}.utilization.rpt

3
fpga/sourceme.sh
View file

@ -5,9 +5,8 @@ if [ -z "${BOARD}" ]; then
export BOARD="genesys2"
fi
echo -n "Configuring for "
if [ "$BOARD" = "genesys2" ]; then
echo -n "Configuring for "
echo "Genesys II"
export XILINX_PART="xc7k325tffg900-2"
export XILINX_BOARD="digilentinc.com:genesys2:part0:1.1"

41
fpga/src/ariane_leds.sv
View file

@ -1,41 +0,0 @@
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Status LEDs
module ariane_leds (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
output logic [7:0] led_o,
input logic [3:0] pc_asserted_i,
input logic [1:0] commit_valid_i,
input logic dmactive_i
);
logic [31:0] cnt_d, cnt_q;
always_comb begin
cnt_d = cnt_q;
led_o = '0;
led_o[0] = pc_asserted_i[0];
led_o[1] = pc_asserted_i[1];
led_o[2] = pc_asserted_i[2];
led_o[3] = pc_asserted_i[3];
led_o[4] = commit_valid_i[0];
led_o[5] = commit_valid_i[1];
end
always_ff @(posedge clk_i or negedge rst_ni) begin : proc_
if (~rst_ni) begin
cnt_q <= 0;
end else begin
cnt_q <= cnt_d + 1;
end
end
endmodule

6
fpga/src/ariane_peripherals_xilinx.sv
View file

@ -282,6 +282,9 @@ module ariane_peripherals #(
// ---------------
// 3. SPI
// ---------------
assign spi.b_user = 1'b0;
assign spi.r_user = 1'b0;
if (InclSPI) begin : gen_spi
logic [31:0] s_axi_spi_awaddr;
logic [7:0] s_axi_spi_awlen;
@ -474,6 +477,9 @@ module ariane_peripherals #(
// ---------------
// 4. Ethernet
// ---------------
assign ethernet.b_user = 1'b0;
assign ethernet.r_user = 1'b0;
if (InclEthernet) begin : gen_ethernet
wire mdio_i, mdio_o, mdio_t;
logic [31:0] s_axi_eth_awaddr;

104
fpga/src/ariane_xilinx.sv
View file

@ -8,7 +8,9 @@
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Xilinx FPGA top-level
// Description: Xilinx FPGA top-level
// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
module ariane_xilinx (
`ifdef GENESYSII
input logic sys_clk_p ,
@ -102,13 +104,6 @@ AXI_BUS #(
.AXI_USER_WIDTH ( AxiUserWidth )
) slave[NBSlave-1:0]();
AXI_BUS #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidthMaster ),
.AXI_USER_WIDTH ( AxiUserWidth )
) dummy_slave();
AXI_BUS #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
@ -220,6 +215,7 @@ dmi_jtag i_dmi_jtag (
.clk_i ( clk ),
.rst_ni ( rst_n ),
.dmi_rst_no ( ), // keep open
.testmode_i ( test_en ),
.dmi_req_valid_o ( debug_req_valid ),
.dmi_req_ready_i ( debug_req_ready ),
.dmi_req_o ( debug_req ),
@ -264,7 +260,7 @@ dm_top #(
.dmi_resp_o ( debug_resp )
);
assign axi_sba_resp = '0;
axi_connect i_axi_connect_ariane (.axi_req_i(axi_sba_req), .axi_resp_o(axi_sba_resp), .master(slave[1]));
// ---------------
// Core
@ -287,7 +283,7 @@ ariane #(
.axi_resp_i ( axi_ariane_resp )
);
axi_connect i_axi_connect_ariane (.axi_req_i(axi_ariane_req), .axi_resp_o(axi_ariane_resp), .master(slave[0]));
axi_connect i_axi_connect_sba (.axi_req_i(axi_ariane_req), .axi_resp_o(axi_ariane_resp), .master(slave[0]));
// ---------------
// CLINT
@ -309,6 +305,7 @@ clint #(
) i_clint (
.clk_i ( clk ),
.rst_ni ( ndmreset_n ),
.testmode_i ( test_en ),
.slave ( master[ariane_soc::CLINT] ),
.rtc_i ( rtc ),
.timer_irq_o ( timer_irq ),
@ -389,45 +386,45 @@ ariane_peripherals #(
// ---------------
// DDR
// ---------------
logic [3:0] s_axi_awid;
logic [63:0] s_axi_awaddr;
logic [7:0] s_axi_awlen;
logic [2:0] s_axi_awsize;
logic [1:0] s_axi_awburst;
logic [0:0] s_axi_awlock;
logic [3:0] s_axi_awcache;
logic [2:0] s_axi_awprot;
logic [3:0] s_axi_awregion;
logic [3:0] s_axi_awqos;
logic s_axi_awvalid;
logic s_axi_awready;
logic [63:0] s_axi_wdata;
logic [7:0] s_axi_wstrb;
logic s_axi_wlast;
logic s_axi_wvalid;
logic s_axi_wready;
logic [3:0] s_axi_bid;
logic [1:0] s_axi_bresp;
logic s_axi_bvalid;
logic s_axi_bready;
logic [3:0] s_axi_arid;
logic [63:0] s_axi_araddr;
logic [7:0] s_axi_arlen;
logic [2:0] s_axi_arsize;
logic [1:0] s_axi_arburst;
logic [0:0] s_axi_arlock;
logic [3:0] s_axi_arcache;
logic [2:0] s_axi_arprot;
logic [3:0] s_axi_arregion;
logic [3:0] s_axi_arqos;
logic s_axi_arvalid;
logic s_axi_arready;
logic [3:0] s_axi_rid;
logic [63:0] s_axi_rdata;
logic [1:0] s_axi_rresp;
logic s_axi_rlast;
logic s_axi_rvalid;
logic s_axi_rready;
logic [AxiIdWidthSlaves-1:0] s_axi_awid;
logic [AxiAddrWidth-1:0] s_axi_awaddr;
logic [7:0] s_axi_awlen;
logic [2:0] s_axi_awsize;
logic [1:0] s_axi_awburst;
logic [0:0] s_axi_awlock;
logic [3:0] s_axi_awcache;
logic [2:0] s_axi_awprot;
logic [3:0] s_axi_awregion;
logic [3:0] s_axi_awqos;
logic s_axi_awvalid;
logic s_axi_awready;
logic [AxiDataWidth-1:0] s_axi_wdata;
logic [AxiDataWidth/8-1:0] s_axi_wstrb;
logic s_axi_wlast;
logic s_axi_wvalid;
logic s_axi_wready;
logic [AxiIdWidthSlaves-1:0] s_axi_bid;
logic [1:0] s_axi_bresp;
logic s_axi_bvalid;
logic s_axi_bready;
logic [AxiIdWidthSlaves-1:0] s_axi_arid;
logic [AxiAddrWidth-1:0] s_axi_araddr;
logic [7:0] s_axi_arlen;
logic [2:0] s_axi_arsize;
logic [1:0] s_axi_arburst;
logic [0:0] s_axi_arlock;
logic [3:0] s_axi_arcache;
logic [2:0] s_axi_arprot;
logic [3:0] s_axi_arregion;
logic [3:0] s_axi_arqos;
logic s_axi_arvalid;
logic s_axi_arready;
logic [AxiIdWidthSlaves-1:0] s_axi_rid;
logic [AxiDataWidth-1:0] s_axi_rdata;
logic [1:0] s_axi_rresp;
logic s_axi_rlast;
logic s_axi_rvalid;
logic s_axi_rready;
assign master[ariane_soc::DRAM].r_user = '0;
assign master[ariane_soc::DRAM].b_user = '0;
@ -533,15 +530,6 @@ fan_ctrl i_fan_ctrl (
.fan_pwm_o ( fan_pwm )
);
ariane_leds i_ariane_leds (
.clk_i ( clk ),
.rst_ni ( rst_n ),
.led_o ( led ),
.pc_asserted_i ( pc_asserted ),
.dmactive_i ( dmactive ),
.commit_valid_i ( '0 )
);
xlnx_mig_7_ddr3 i_ddr (
.sys_clk_p,
.sys_clk_n,

10
fpga/src/bootrom/ariane.dts
View file

@ -31,7 +31,7 @@
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x1800000>;
reg = <0x0 0x80000000 0x0 0x8000000>;
};
L26: soc {
#address-cells = <2>;
@ -70,19 +70,19 @@
reg-shift = <2>; // regs are spaced on 32 bit boundary
reg-io-width = <4>; // only 32-bit access are supported
};
xlnx_axi_ethernetlite: ethernet@12000000 {
xlnx_axi_ethernetlite: ethernet@30000000 {
compatible = "xlnx,axi-ethernetlite-3.0", "xlnx,xps-ethernetlite-1.00.a";
device_type = "network";
interrupt-parent = <&PLIC0>;
interrupts = <2 0>;
local-mac-address = [00 0a 35 00 01 22];
phy-handle = <&phy0>;
reg = <0x0 0x20000000 0x0 0x10000>;
reg = <0x0 0x30000000 0x0 0x10000>;
xlnx,duplex = <0x1>;
xlnx,include-global-buffers = <0x1>;
xlnx,include-internal-loopback = <0x0>;
xlnx,include-mdio = <0x1>;
xlnx,instance = "axi_ethernetlite_inst";
xlnx,instance = "i_xlnx_axi_ethernetlite";
xlnx,rx-ping-pong = <0x1>;
xlnx,s-axi-id-width = <0x4>;
xlnx,tx-ping-pong = <0x1>;
@ -96,7 +96,7 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
compatible = "realtek,RTL8211E";
compatible = "ethernet-phy-id001c.c915";
device_type = "ethernet-phy";
reg = <0x1>;
};

BIN
fpga/src/bootrom/bootrom.elf
View file

Binary file not shown.

40
fpga/src/bootrom/bootrom.h
View file

@ -1,6 +1,6 @@
// Auto-generated code
const int reset_vec_size = 672;
const int reset_vec_size = 674;
uint32_t reset_vec[reset_vec_size] = {
0x0010041b,
@ -36,15 +36,15 @@ uint32_t reset_vec[reset_vec_size] = {
0x00000000,
0x00000000,
0xedfe0dd0,
0xfc090000,
0x040a0000,
0x38000000,
0xd0070000,
0xd8070000,
0x28000000,
0x11000000,
0x10000000,
0x00000000,
0x2c020000,
0x98070000,
0xa0070000,
0x00000000,
0x00000000,
0x00000000,
@ -194,7 +194,7 @@ uint32_t reset_vec[reset_vec_size] = {
0x00000000,
0x00000080,
0x00000000,
0x00008001,
0x00000008,
0x02000000,
0x01000000,
0x00636f73,
@ -385,7 +385,7 @@ uint32_t reset_vec[reset_vec_size] = {
0x01000000,
0x65687465,
0x74656e72,
0x30323140,
0x30303340,
0x30303030,
0x00000030,
0x03000000,
@ -432,7 +432,7 @@ uint32_t reset_vec[reset_vec_size] = {
0x10000000,
0x67000000,
0x00000000,
0x00000020,
0x00000030,
0x00000000,
0x00000100,
0x03000000,
@ -452,14 +452,14 @@ uint32_t reset_vec[reset_vec_size] = {
0xab010000,
0x01000000,
0x03000000,
0x16000000,
0x18000000,
0xbd010000,
0x5f697861,
0x65687465,
0x74656e72,
0x6574696c,
0x736e695f,
0x00000074,
0x6c785f69,
0x615f786e,
0x655f6978,
0x72656874,
0x6c74656e,
0x00657469,
0x03000000,
0x04000000,
0xcb010000,
@ -503,12 +503,14 @@ uint32_t reset_vec[reset_vec_size] = {
0x7968702d,
0x00003040,
0x03000000,
0x11000000,
0x19000000,
0x1b000000,
0x6c616572,
0x2c6b6574,
0x384c5452,
0x45313132,
0x65687465,
0x74656e72,
0x7968702d,
0x3064692d,
0x2e633130,
0x35313963,
0x00000000,
0x03000000,
0x0d000000,

BIN
fpga/src/bootrom/bootrom.img
View file

Binary file not shown.

31
fpga/src/bootrom/bootrom.sv
View file

@ -20,7 +20,7 @@ module bootrom (
input logic [63:0] addr_i,
output logic [63:0] rdata_o
);
localparam int RomSize = 336;
localparam int RomSize = 337;
const logic [RomSize-1:0][63:0] mem = {
64'h00000000_0065646f,
@ -106,9 +106,10 @@ module bootrom (
64'h74656e72_65687465,
64'h5b000000_0d000000,
64'h03000000_00000000,
64'h45313132_384c5452,
64'h2c6b6574_6c616572,
64'h1b000000_11000000,
64'h35313963_2e633130,
64'h3064692d_7968702d,
64'h74656e72_65687465,
64'h1b000000_19000000,
64'h03000000_00003040,
64'h7968702d_74656e72,
64'h65687465_01000000,
@ -130,11 +131,11 @@ module bootrom (
64'hdd010000_04000000,
64'h03000000_01000000,
64'hcb010000_04000000,
64'h03000000_00000074,
64'h736e695f_6574696c,
64'h74656e72_65687465,
64'h5f697861_bd010000,
64'h16000000_03000000,
64'h03000000_00657469,
64'h6c74656e_72656874,
64'h655f6978_615f786e,
64'h6c785f69_bd010000,
64'h18000000_03000000,
64'h01000000_ab010000,
64'h04000000_03000000,
64'h00000000_8c010000,
@ -144,7 +145,7 @@ module bootrom (
64'h01000000_64010000,
64'h04000000_03000000,
64'h00000100_00000000,
64'h00000020_00000000,
64'h00000030_00000000,
64'h67000000_10000000,
64'h03000000_03000000,
64'h59010000_04000000,
@ -167,7 +168,7 @@ module bootrom (
64'h6978612c_786e6c78,
64'h1b000000_37000000,
64'h03000000_00000030,
64'h30303030_30323140,
64'h30303030_30303340,
64'h74656e72_65687465,
64'h01000000_02000000,
64'h04000000_3a010000,
@ -263,7 +264,7 @@ module bootrom (
64'h00000000_04000000,
64'h03000000_00636f73,
64'h01000000_02000000,
64'h00008001_00000000,
64'h00000008_00000000,
64'h00000080_00000000,
64'h67000000_10000000,
64'h03000000_00007972,
@ -338,11 +339,11 @@ module bootrom (
64'h00000000_01000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h98070000_2c020000,
64'ha0070000_2c020000,
64'h00000000_10000000,
64'h11000000_28000000,
64'hd0070000_38000000,
64'hfc090000_edfe0dd0,
64'hd8070000_38000000,
64'h040a0000_edfe0dd0,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,

2
fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl
View file

@ -8,7 +8,7 @@ set_property board_part $boardName [current_project]
create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name $ipName
set_property -dict [list CONFIG.ADDR_WIDTH {64} CONFIG.ID_WIDTH {5}] [get_ips $ipName]
set_property -dict [list CONFIG.ADDR_WIDTH {64} CONFIG.DATA_WIDTH {64} CONFIG.ID_WIDTH {5}] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]

6
fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj
View file

@ -1,7 +1,7 @@
<?xml version='1.0' encoding='UTF-8'?>
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<Project NoOfControllers="1" >
<ModuleName>mig_7series_0</ModuleName>
<ModuleName>xlnx_mig_7_ddr3</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>OFF</Debug_En>
@ -152,9 +152,9 @@
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
<C0_S_AXI_ID_WIDTH>5</C0_S_AXI_ID_WIDTH>
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
</AXIParameters>
</Controller>
</Project>
</Project>

2
src/axi_node

@ -1 +1 @@
Subproject commit b960c6101c976d687e6e0e66c12daf74808bc2b8
Subproject commit 6338af6ee3065c4de22b555a67f64755745b7129

1
src/branch_unit.sv
View file

@ -38,7 +38,6 @@ module branch_unit (
automatic logic [63:0] jump_base;
jump_base = (fu_data_i.operator == JALR) ? fu_data_i.operand_a : pc_i;
target_address = 64'b0;
resolve_branch_o = 1'b0;
resolved_branch_o.target_address = 64'b0;
resolved_branch_o.is_taken = 1'b0;

2
src/clint/axi_lite_interface.sv
View file

@ -62,9 +62,11 @@ module axi_lite_interface #(
slave.aw_ready = 1'b0;
slave.w_ready = 1'b0;
slave.b_valid = 1'b0;
slave.b_user = 1'b0;
slave.ar_ready = 1'b1;
slave.r_valid = 1'b0;
slave.r_user = 1'b0;
address_o = '0;
we_o = 1'b0;

14
src/commit_stage.sv
View file

@ -56,6 +56,20 @@ module commit_stage #(
output logic sfence_vma_o // flush TLBs and pipeline
);
// ila_0 i_ila_commit (
// .clk(clk_i), // input wire clk
// .probe0(commit_instr_i[0].pc), // input wire [63:0] probe0
// .probe1(commit_instr_i[1].pc), // input wire [63:0] probe1
// .probe2(commit_instr_i[0].valid), // input wire [0:0] probe2
// .probe3(commit_instr_i[1].valid), // input wire [0:0] probe3
// .probe4(commit_ack_o[0]), // input wire [0:0] probe4
// .probe5(commit_ack_o[0]), // input wire [0:0] probe5
// .probe6(1'b0), // input wire [0:0] probe6
// .probe7(1'b0), // input wire [0:0] probe7
// .probe8(1'b0), // input wire [0:0] probe8
// .probe9(1'b0) // input wire [0:0] probe9
// );
// TODO make these parametric with NR_COMMIT_PORTS
assign waddr_o[0] = commit_instr_i[0].rd[4:0];
assign waddr_o[1] = commit_instr_i[1].rd[4:0];

2
tb/ariane_soc_pkg.sv
View file

@ -38,8 +38,8 @@ package ariane_soc;
localparam logic[63:0] UARTLength = 64'h1000;
localparam logic[63:0] SPILength = 64'h800000;
localparam logic[63:0] EthernetLength = 64'h10000;
localparam logic[63:0] DRAMLength = 64'h8000000; // 128 MByte of DDR
localparam logic[63:0] SRAMLength = 64'h1800000; // 24 MByte of SRAM
localparam logic[63:0] DRAMLength = 64'h80000000; // 2 GByte of DDR
// Instantiate AXI protocol checkers
localparam bit GenProtocolChecker = 1'b0;