Define a new param to constraint mtvec to be in direct mode only (#2226)

core/csr_regfile.sv

@@ -1349,10 +1349,12 @@ module csr_regfile
         end
 
         riscv::CSR_MTVEC: begin
-          mtvec_d = {csr_wdata[CVA6Cfg.XLEN-1:2], 1'b0, csr_wdata[0]};
+          logic DirVecOnly;
+          DirVecOnly = CVA6Cfg.DirectVecOnly ? 1'b0 : csr_wdata[0];
+          mtvec_d = {csr_wdata[CVA6Cfg.XLEN-1:2], 1'b0, DirVecOnly};
           // we are in vector mode, this implementation requires the additional
           // alignment constraint of 64 * 4 bytes
-          if (csr_wdata[0]) mtvec_d = {csr_wdata[CVA6Cfg.XLEN-1:8], 7'b0, csr_wdata[0]};
+          if (DirVecOnly) mtvec_d = {csr_wdata[CVA6Cfg.XLEN-1:8], 7'b0, DirVecOnly};
         end
         riscv::CSR_MCOUNTEREN: begin
           if (CVA6Cfg.RVU) mcounteren_d = {{CVA6Cfg.XLEN - 32{1'b0}}, csr_wdata[31:0]};

core/include/build_config_pkg.sv

@@ -92,6 +92,7 @@ package build_config_pkg;
     cfg.BHTEntries = CVA6Cfg.BHTEntries;
     cfg.DmBaseAddress = CVA6Cfg.DmBaseAddress;
     cfg.TvalEn = CVA6Cfg.TvalEn;
+    cfg.DirectVecOnly = CVA6Cfg.DirectVecOnly;
     cfg.NrPMPEntries = CVA6Cfg.NrPMPEntries;
     cfg.PMPCfgRstVal = CVA6Cfg.PMPCfgRstVal;
     cfg.PMPAddrRstVal = CVA6Cfg.PMPAddrRstVal;

core/include/config_pkg.sv

@@ -94,6 +94,8 @@ package config_pkg;
     logic [63:0]                 ExceptionAddress;
     // Tval Support Enable
     bit                          TvalEn;
+    // MTVEC CSR supports only direct mode
+    bit                          DirectVecOnly;
     // PMP entries number
     int unsigned                 NrPMPEntries;
     // PMP CSR configuration reset values
@@ -267,6 +269,7 @@ package config_pkg;
 
     logic [63:0]                 DmBaseAddress;
     bit                          TvalEn;
+    bit                          DirectVecOnly;
     int unsigned                 NrPMPEntries;
     logic [15:0][63:0]           PMPCfgRstVal;
     logic [15:0][63:0]           PMPAddrRstVal;

core/include/cv32a60x_config_pkg.sv

@@ -112,6 +112,7 @@ package cva6_config_pkg;
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
+      DirectVecOnly: bit'(0),
       NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries),
       PMPCfgRstVal: {16{64'h0}},
       PMPAddrRstVal: {16{64'h0}},

core/include/cv32a65x_config_pkg.sv

@@ -60,6 +60,7 @@ package cva6_config_pkg;
       BHTEntries: unsigned'(32),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(0),
+      DirectVecOnly: bit'(1),
       NrPMPEntries: unsigned'(8),
       PMPCfgRstVal: {16{64'h0}},
       PMPAddrRstVal: {16{64'h0}},

core/include/cv32a6_embedded_config_pkg.sv

@@ -111,6 +111,7 @@ package cva6_config_pkg;
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
+      DirectVecOnly: bit'(0),
       NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries),
       PMPCfgRstVal: {16{64'h0}},
       PMPAddrRstVal: {16{64'h0}},

core/include/cv32a6_ima_sv32_fpga_config_pkg.sv

@@ -112,6 +112,7 @@ package cva6_config_pkg;
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
       DmBaseAddress: 64'h0,
       TvalEn: unsigned'(CVA6ConfigTvalEn),
+      DirectVecOnly: bit'(0),
       NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries),
       PMPCfgRstVal: {16{64'h0}},
       PMPAddrRstVal: {16{64'h0}},

core/include/cv32a6_imac_sv0_config_pkg.sv

@@ -112,6 +112,7 @@ package cva6_config_pkg;
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
       DmBaseAddress: 64'h0,
       TvalEn: unsigned'(CVA6ConfigTvalEn),
+      DirectVecOnly: bit'(0),
       NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries),
       PMPCfgRstVal: {16{64'h0}},
       PMPAddrRstVal: {16{64'h0}},

core/include/cv32a6_imac_sv32_config_pkg.sv

@@ -112,6 +112,7 @@ package cva6_config_pkg;
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
+      DirectVecOnly: bit'(0),
       NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries),
       PMPCfgRstVal: {16{64'h0}},
       PMPAddrRstVal: {16{64'h0}},

core/include/cv32a6_imafc_sv32_config_pkg.sv

@@ -112,6 +112,7 @@ package cva6_config_pkg;
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
+      DirectVecOnly: bit'(0),
       NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries),
       PMPCfgRstVal: {16{64'h0}},
       PMPAddrRstVal: {16{64'h0}},

core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv

@@ -112,6 +112,7 @@ package cva6_config_pkg;
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
+      DirectVecOnly: bit'(0),
       NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries),
       PMPCfgRstVal: {16{64'h0}},
       PMPAddrRstVal: {16{64'h0}},

core/include/cv64a6_imafdc_sv39_config_pkg.sv

@@ -112,6 +112,7 @@ package cva6_config_pkg;
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
+      DirectVecOnly: bit'(0),
       NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries),
       PMPCfgRstVal: {16{64'h0}},
       PMPAddrRstVal: {16{64'h0}},

core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv

@@ -119,6 +119,7 @@ package cva6_config_pkg;
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
+      DirectVecOnly: bit'(0),
       NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries),
       PMPCfgRstVal: {16{64'h0}},
       PMPAddrRstVal: {16{64'h0}},

core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv

@@ -112,6 +112,7 @@ package cva6_config_pkg;
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
+      DirectVecOnly: bit'(0),
       NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries),
       PMPCfgRstVal: {16{64'h0}},
       PMPAddrRstVal: {16{64'h0}},

core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv

@@ -112,6 +112,7 @@ package cva6_config_pkg;
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
+      DirectVecOnly: bit'(0),
       NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries),
       PMPCfgRstVal: {16{64'h0}},
       PMPAddrRstVal: {16{64'h0}},

core/include/cv64a6_imafdch_sv39_config_pkg.sv

@@ -112,6 +112,7 @@ package cva6_config_pkg;
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
+      DirectVecOnly: bit'(0),
       NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries),
       PMPCfgRstVal: {16{64'h0}},
       PMPAddrRstVal: {16{64'h0}},

core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv

@@ -112,6 +112,7 @@ package cva6_config_pkg;
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
+      DirectVecOnly: bit'(0),
       NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries),
       PMPCfgRstVal: {16{64'h0}},
       PMPAddrRstVal: {16{64'h0}},

core/include/cv64a6_imafdcv_sv39_config_pkg.sv

@@ -112,6 +112,7 @@ package cva6_config_pkg;
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
+      DirectVecOnly: bit'(0),
       NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries),
       PMPCfgRstVal: {16{64'h0}},
       PMPAddrRstVal: {16{64'h0}},

core/include/cv64a6_mmu_config_pkg.sv

@@ -64,6 +64,7 @@ package cva6_config_pkg;
       BHTEntries: unsigned'(32),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(0),
+      DirectVecOnly: bit'(1),
       NrPMPEntries: unsigned'(64),
       PMPCfgRstVal: {16{64'h0}},
       PMPAddrRstVal: {16{64'h0}},