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doc: update MVENDORID CSR value (fix #1735) (#1753)

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André Sintzoff 2024-01-10 10:30:48 +00:00 • committed by GitHub
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4
docs/csr-from-ip-xact/cv32a60x/csr.rst
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@ -3661,13 +3661,13 @@ This register provids the JEDEC manufacturer ID of the provider of the core.
* - 31:7
- bank
- Bank
- 0xC0
- 0xC
- read-only
- Contain encoding for number of one\-byte continuation codes discarding the parity bit\.
* - 6:0
- offset
- Offset
- 0x20
- 0x2
- read-only
- Contain encording for the final byte discarding the parity bit\.

4
docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.md
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@ -1118,8 +1118,8 @@ Instructions-retired counter for RDINSTRET instruction. Shadow of minstreth.
This register provids the JEDEC manufacturer ID of the provider of the core.
| BIT | NAME | displayName |Reset| RIGHT | Description |
| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- |
| 31:7 | bank | Bank | 0xC0 | read-only | Contain encoding for number of one\-byte continuation codes discarding the parity bit\.|
| 6:0 | offset | Offset | 0x20 | read-only | Contain encording for the final byte discarding the parity bit\.|
| 31:7 | bank | Bank | 0xC | read-only | Contain encoding for number of one\-byte continuation codes discarding the parity bit\.|
| 6:0 | offset | Offset | 0x2 | read-only | Contain encording for the final byte discarding the parity bit\.|
## MARCHID : Machine Architecture ID Register
### *AddressOffset*: 'hF12

4
docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.yaml
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@ -3604,7 +3604,7 @@ component:
bitOffset: '7'
resets:
reset:
value: '0xC0'
value: '0xC'
mask: '0x1ffffff'
bitWidth: '25'
volatile: 'true'
@ -3615,7 +3615,7 @@ component:
bitOffset: '0'
resets:
reset:
value: '0x20'
value: '0x2'
mask: '0x7f'
bitWidth: '7'
volatile: 'true'