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Added ADDW, SUB and SUBW ALU sequences

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This commit is contained in:
Florian Zaruba 2017-04-09 13:25:03 +02:00
parent 4ffb7ae4aa
commit ddc3cff3f8
6 changed files with 68 additions and 5 deletions
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2
tb/sequences/add_sequence.svh
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@ -1,6 +1,6 @@
class add_sequence extends basic_sequence;
`uvm_object_utils(basic_sequence);
`uvm_object_utils(add_sequence);
function new(string name = "add");
super.new(name);

16
tb/sequences/addw_sequence.svh Normal file
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@ -0,0 +1,16 @@
class addw_sequence extends basic_sequence;
`uvm_object_utils(addw_sequence);
function new(string name = "addw");
super.new(name);
endfunction : new
function alu_op get_operator();
return ADDW;
endfunction : get_operator
task body();
super.body();
endtask : body
endclass : addw_sequence

3
tb/sequences/basic_sequence.svh
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@ -12,11 +12,12 @@ virtual class basic_sequence extends fu_if_seq;
fu_if_seq_item command;
command = fu_if_seq_item::type_id::create("command");
`uvm_info("ALU Sequence", $sformatf("Starting %s sequence", get_operator().name))
for(int i = 0; i <= 100; i++) begin
start_item(command);
if(~command.randomize())
`uvm_warning("ALU Basic Sequence", "Randomization constraints can not be met.")
`uvm_warning("ALU Basic Sequence", "Randomization constraints can not be met.")
command.operator = get_operator();
finish_item(command);

16
tb/sequences/sub_sequence.svh Normal file
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@ -0,0 +1,16 @@
class sub_sequence extends basic_sequence;
`uvm_object_utils(sub_sequence);
function new(string name = "sub");
super.new(name);
endfunction : new
function alu_op get_operator();
return SUB;
endfunction : get_operator
task body();
super.body();
endtask : body
endclass : sub_sequence

16
tb/sequences/subw_sequence.svh Normal file
View file

@ -0,0 +1,16 @@
class subw_sequence extends basic_sequence;
`uvm_object_utils(subw_sequence);
function new(string name = "addw");
super.new(name);
endfunction : new
function alu_op get_operator();
return SUBW;
endfunction : get_operator
task body();
super.body();
endtask : body
endclass : subw_sequence

20
tb/test/alu_test.svh
View file

@ -8,7 +8,10 @@ class alu_test extends alu_test_base;
`uvm_component_utils(alu_test)
fibonacci_sequence fibonacci;
add_sequence add_sequence;
add_sequence add_sequence;
addw_sequence addw_sequence;
subw_sequence subw_sequence;
sub_sequence sub_sequence;
//------------------------------------------
// Methods
@ -27,8 +30,19 @@ class alu_test extends alu_test_base;
phase.raise_objection(this, "alu_test");
//fibonacci_sequence fibonacci;
super.run_phase(phase);
add_sequence = new("add");
add_sequence.start(sequencer_h);
add_sequence = new("add");
add_sequence.start(sequencer_h);
addw_sequence = new("addw");
addw_sequence.start(sequencer_h);
subw_sequence = new("subw");
subw_sequence.start(sequencer_h);
sub_sequence = new("sub");
sub_sequence.start(sequencer_h);
fibonacci = new("fibonacci");
fibonacci.start(sequencer_h);
// Testlogic goes here