mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-20 12:17:19 -04:00
Add big Olimex debug adapter
This commit is contained in:
parent
411f645a61
commit
e0e61df549
3 changed files with 47 additions and 3 deletions
|
@ -1,8 +1,8 @@
|
|||
adapter_khz 100
|
||||
adapter_khz 1000
|
||||
|
||||
interface ftdi
|
||||
ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
|
||||
ftdi_vid_pid 0x15ba 0x002a
|
||||
# ftdi_device_desc "Olimex Ltd. ARM-USB-OCD-H JTAG+RS232"
|
||||
ftdi_vid_pid 0x15ba 0x002b
|
||||
|
||||
ftdi_layout_init 0x0808 0x0a1b
|
||||
ftdi_layout_signal nSRST -oe 0x0200
|
||||
|
|
29
fpga/ariane_tiny.cfg
Normal file
29
fpga/ariane_tiny.cfg
Normal file
|
@ -0,0 +1,29 @@
|
|||
adapter_khz 1000
|
||||
|
||||
interface ftdi
|
||||
ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
|
||||
ftdi_vid_pid 0x15ba 0x002a
|
||||
|
||||
ftdi_layout_init 0x0808 0x0a1b
|
||||
ftdi_layout_signal nSRST -oe 0x0200
|
||||
ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
|
||||
ftdi_layout_signal LED -data 0x0800
|
||||
|
||||
set _CHIPNAME riscv
|
||||
jtag newtap $_CHIPNAME cpu -irlen 5
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
|
||||
|
||||
gdb_report_data_abort enable
|
||||
gdb_report_register_access_error enable
|
||||
|
||||
riscv set_reset_timeout_sec 120
|
||||
riscv set_command_timeout_sec 120
|
||||
|
||||
# prefer to use sba for system bus access
|
||||
riscv set_prefer_sba off
|
||||
|
||||
init
|
||||
halt
|
||||
echo "Ready for Remote Connections"
|
15
fpga/src/genesysii.svh
Normal file
15
fpga/src/genesysii.svh
Normal file
|
@ -0,0 +1,15 @@
|
|||
// Copyright 2018 ETH Zurich and University of Bologna.
|
||||
// Copyright and related rights are licensed under the Solderpad Hardware
|
||||
// License, Version 0.51 (the "License"); you may not use this file except in
|
||||
// compliance with the License. You may obtain a copy of the License at
|
||||
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
|
||||
// or agreed to in writing, software, hardware and materials distributed under
|
||||
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
|
||||
// specific language governing permissions and limitations under the License.
|
||||
|
||||
// Description: Set global FPGA degines
|
||||
// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
|
||||
|
||||
`define GENESYSII
|
||||
`define FPGA_TARGET_XILINX
|
Loading…
Add table
Add a link
Reference in a new issue