Aad IPI to Ariane

CHANGELOG.md

@@ -14,6 +14,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 - Two AXI interfaces on top level, one for bypassing and one for actual cache-able regions
 - Performance Counters
 - Hardware multiplication (full M-Extension)
+- Support for inter processor interrupts (IPI)
 
 ### Changed
 

src/ariane.sv

@@ -52,6 +52,7 @@ module ariane (
         AXI_BUS.Master                         bypass_if,
         // Interrupt inputs
         input  logic [1:0]                     irq_i,        // level sensitive IR lines, mip & sip
+        input  logic                           ipi_i,        // inter-processor interrupts
         input  logic [4:0]                     irq_id_i,
         output logic                           irq_ack_o,
         input  logic                           irq_sec_i,

src/csr_regfile.sv

@@ -68,6 +68,7 @@ module csr_regfile #(
     output logic [ASID_WIDTH-1:0] asid_o,
     // external interrupts
     input  logic [1:0]            irq_i,                      // external interrupt in
+    input  logic                  ipi_i,                      // inter processor interrupt -> connected to machine mode sw
     // Visualization Support
     output logic                  tvm_o,                      // trap virtual memory
     output logic                  tw_o,                       // timeout wait
@@ -385,6 +386,8 @@ module csr_regfile #(
         // Machine Mode External Interrupt Pending
         mip_d[11] = mie_q[11] & irq_i[1];
         mip_d[9] = mie_q[9] & irq_i[0];
+        // Machine software interrupt
+        mip_d[3] = mie_q[3] & ipi_i;
         // Timer interrupt pending, coming from platform timer
         mip_d[7] = time_irq_i;