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WIP: Remove timing loop

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This commit is contained in:
Florian Zaruba 2017-08-26 09:12:26 +02:00
parent 53e674aeb3
commit e2424c1cc2
1 changed files with 4 additions and 6 deletions
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10
src/csr_regfile.sv
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@ -467,12 +467,10 @@ module csr_regfile #(
csr_read = 1'b0;
end
endcase
// if we are retiring an exception do not modify anything
// if we are retiring an exception do not return from exception
if (ex_i.valid) begin
mret = 1'b0;
sret = 1'b0;
csr_we = 1'b0;
csr_read = 1'b0;
mret = 1'b0;
sret = 1'b0;
end
// ------------------------------
// Debug Multiplexer (Priority)
@ -679,7 +677,7 @@ module csr_regfile #(
// check that eret and ex are never valid together
assert property (
@(posedge clk_i) !(eret_o && ex_i.valid))
else $warning("eret and exception should never be valid at the same time");
else begin $error("eret and exception should never be valid at the same time"); $stop(); end
`endif
`endif
endmodule