github-mirrors/cva6
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva6.git synced 2025-04-20 12:17:19 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

🐛 Couple of LSU related fixes

Browse source
This commit is contained in:
Florian Zaruba 2017-05-30 12:28:23 +02:00
parent a60ca39621
commit e29a923ca2
7 changed files with 47 additions and 42 deletions
Download patch file Download diff file Expand all files Collapse all files

3
src/csr_buffer.sv
View file

@ -49,7 +49,8 @@ module csr_buffer (
// control logic, scoreboard signals
assign csr_trans_id_o = trans_id_i;
assign csr_valid_o = csr_reg_q.valid | csr_valid_i;
// CSR instructions for this post buffer are single cycle
assign csr_valid_o = csr_valid_i;
assign csr_result_o = operand_a_i;
assign csr_ready_o = (csr_reg_q.valid && ~commit_i) ? 1'b0 : 1'b1;
assign csr_addr_o = csr_reg_q.csr_address;

2
src/load_unit.sv
View file

@ -62,7 +62,7 @@ module load_unit (
typedef struct packed {
logic [TRANS_ID_BITS-1:0] trans_id;
logic [2:0] address_offset;
fu_t operator;
fu_op operator;
} rvalid_entry_t;
// queue control signal

26
src/lsu.sv
View file

@ -191,17 +191,17 @@ module lsu #(
.lsu_paddr_o ( mmu_paddr ),
.lsu_exception_o ( mmu_exception ),
// connecting PTW to D$ IF (aka mem arbiter
.data_if_address_index_o ( address_index_i [0] ),
.data_if_address_tag_o ( address_tag_i [0] ),
.data_if_data_wdata_o ( data_wdata_i [0] ),
.data_if_data_req_o ( data_req_i [0] ),
.data_if_data_we_o ( data_we_i [0] ),
.data_if_data_be_o ( data_be_i [0] ),
.data_if_kill_req_o ( kill_req_i [0] ),
.data_if_tag_valid_o ( tag_valid_i [0] ),
.data_if_data_gnt_i ( data_gnt_o [0] ),
.data_if_data_rvalid_i ( data_rvalid_o [0] ),
.data_if_data_rdata_i ( data_rdata_o [0] ),
.address_index_o ( address_index_i [0] ),
.address_tag_o ( address_tag_i [0] ),
.data_wdata_o ( data_wdata_i [0] ),
.data_req_o ( data_req_i [0] ),
.data_we_o ( data_we_i [0] ),
.data_be_o ( data_be_i [0] ),
.kill_req_o ( kill_req_i [0] ),
.tag_valid_o ( tag_valid_i [0] ),
.data_gnt_i ( data_gnt_o [0] ),
.data_rvalid_i ( data_rvalid_o [0] ),
.data_rdata_i ( data_rdata_o [0] ),
.*
);
// ------------------
@ -340,12 +340,12 @@ module lsu #(
unique case (operator)
// all loads go here
LD, LW, LWU, LH, LHU, LB, LBU: begin
ld_valid_i = lsu_valid_i;
ld_valid_i = 1'b1;
op = LD_OP;
end
// all stores go here
SD, SW, SH, SB: begin
st_valid_i = lsu_valid_i;
st_valid_i = 1'b1;
op = ST_OP;
end
// not relevant for the LSU

32
src/mmu.sv
View file

@ -63,17 +63,17 @@ module mmu #(
input logic instr_if_data_rvalid_i,
input logic [31:0] instr_if_data_rdata_i,
// Data memory/cache
output logic [11:0] data_if_address_index_o,
output logic [43:0] data_if_address_tag_o,
output logic [63:0] data_if_data_wdata_o,
output logic data_if_data_req_o,
output logic data_if_data_we_o,
output logic [7:0] data_if_data_be_o,
output logic data_if_kill_req_o,
output logic data_if_tag_valid_o,
input logic data_if_data_gnt_i,
input logic data_if_data_rvalid_i,
input logic [63:0] data_if_data_rdata_i
output logic [11:0] address_index_o,
output logic [43:0] address_tag_o,
output logic [63:0] data_wdata_o,
output logic data_req_o,
output logic data_we_o,
output logic [7:0] data_be_o,
output logic kill_req_o,
output logic tag_valid_o,
input logic data_gnt_i,
input logic data_rvalid_i,
input logic [63:0] data_rdata_i
);
// assignments necessary to use interfaces here
// only done for the few signals of the instruction interface
@ -171,16 +171,6 @@ module mmu #(
.ptw_error_o ( ptw_error ),
.enable_translation_i ( enable_translation_i ),
.address_o ( ), // TODO
.data_wdata_o ( ), // TODO
.data_req_o ( ), // TODO
.data_we_o ( ), // TODO
.data_be_o ( ), // TODO
.data_tag_status_o ( ), // TODO
.data_gnt_i ( ), // TODO
.data_rvalid_i ( ), // TODO
.data_rdata_i ( ), // TODO
.itlb_update_o ( itlb_update ),
.dtlb_update_o ( dtlb_update ),
.update_content_o ( update_content ),

15
src/ptw.sv
View file

@ -34,12 +34,14 @@ module ptw #(
output logic ptw_error_o, // set when an error occured
input logic enable_translation_i,
// memory port
output logic [63:0] address_o,
output logic [11:0] address_index_o,
output logic [43:0] address_tag_o,
output logic [63:0] data_wdata_o,
output logic data_req_o,
output logic data_we_o,
output logic [7:0] data_be_o,
output logic [1:0] data_tag_status_o,
output logic kill_req_o,
output logic tag_valid_o,
input logic data_gnt_i,
input logic data_rvalid_i,
input logic [63:0] data_rdata_i,
@ -97,7 +99,14 @@ module ptw #(
// 4 byte aligned physical pointer
logic[45:0] ptw_pptr_q, ptw_pptr_n;
// directly output the correct physical address
assign address_o = {ptw_pptr_q, 4'b0};
// ------
// TODO
// -------
// assign address_o = {ptw_pptr_q, 4'b0}; TODO
assign address_index_o = '0;
assign address_tag_o = '0;
assign tag_valid_o = '0;
assign kill_req_o = '0;
// update the correct page table level
assign update_is_2M_o = (ptw_lvl_q == LVL2);
assign update_is_1G_o = (ptw_lvl_q == LVL1);

6
tb/common/dp_ram.sv
View file

@ -40,7 +40,7 @@ module dp_ram
if (en_a_i && we_a_i) begin
for (int i = 0; i < DATA_WIDTH/8; i++) begin
if (be_a_i[i])
mem[addr_a_i][i] <= wdata_a_i[i +: 8];
mem[addr_a_i][i] <= wdata_a_i[i*8 +: 8];
end
end
@ -49,11 +49,11 @@ module dp_ram
if (en_b_i && we_b_i) begin
for (int i = 0; i < DATA_WIDTH/8; i++) begin
if (be_b_i[i])
mem[addr_b_i][i] <= wdata_b_i[i +: 8];
mem[addr_b_i][i] <= wdata_b_i[i*8 +: 8];
end
end
end
// output port two combinatorially since we need to mimic a cache interface
// output port 2: combinatorially since we need to mimic a cache interface
assign rdata_b_o = mem[addr_b_i];
endmodule

5
test/add_test.S
View file

@ -12,6 +12,11 @@
csrw mstatus, x7
add x9, x7, x8
csrr x1, mstatus
addi x7, x0, 256
lui x8, 0xDEAD
sd x8, 0(x7)
add x6, x4, x5
ld x9, 0(x7)
nop
L0: jal x0, L1
nop