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Updates to match the latest version of RISCV-DV (#1576)

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Jalali 2023-10-30 14:10:58 +01:00 • committed by GitHub
parent 4b67475fa4
commit e2a5250473
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9 changed files with 322 additions and 181 deletions
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4
verif/env/corev-dv/cva6_asm_program_gen.sv vendored
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@ -110,10 +110,6 @@ class cva6_asm_program_gen_c extends riscv_asm_program_gen;
// Program end
gen_program_end(hart);
if (!cfg_cva6.bare_program_mode) begin
if (!riscv_instr_pkg::support_pmp) begin
// Privileged mode switch routine
gen_privileged_mode_switch_routine(hart);
end
// Generate debug rom section
if (riscv_instr_pkg::support_debug_mode) begin
gen_debug_rom(hart);

33
verif/env/corev-dv/target/rv32imac/riscv_core_setting.sv vendored
View file

@ -30,7 +30,7 @@ privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE};
riscv_instr_name_t unsupported_instr[];
// ISA supported by the processor
riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C, RV32A};
riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C, RV32A, RV32X};
// Interrupt mode support
mtvec_mode_t supported_interrupt_mode[$] = {DIRECT, VECTORED};
@ -42,6 +42,9 @@ int max_interrupt_vector_num = 16;
// Physical memory protection support
bit support_pmp = 0;
// Enhanced physical memory protection support
bit support_epmp = 0;
// Debug mode support
bit support_debug_mode = 0;
@ -54,11 +57,35 @@ bit support_sfence = 0;
// Support unaligned load/store
bit support_unaligned_load_store = 1'b1;
// GPR setting
parameter int NUM_FLOAT_GPR = 32;
parameter int NUM_GPR = 32;
parameter int NUM_VEC_GPR = 32;
// ----------------------------------------------------------------------------
// Vector extension configuration
// ----------------------------------------------------------------------------
// Parameter for vector extension
parameter int VECTOR_EXTENSION_ENABLE = 0;
parameter int VLEN = 512;
parameter int ELEN = 64;
parameter int SLEN = 64;
// Maximum size of a single vector element
parameter int ELEN = 32;
// Minimum size of a sub-element, which must be at most 8-bits.
parameter int SELEN = 8;
// Maximum size of a single vector element (encoded in vsew format)
parameter int VELEN = int'($ln(ELEN)/$ln(2)) - 3;
// Maxium LMUL supported by the core
parameter int MAX_LMUL = 8;
// ----------------------------------------------------------------------------
// Multi-harts configuration
// ----------------------------------------------------------------------------
// Number of harts
parameter int NUM_HARTS = 1;

132
verif/env/corev-dv/target/rv32imc/riscv_core_setting.sv vendored
View file

@ -1,132 +0,0 @@
/*
* Copyright 2019 Google LLC
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
//-----------------------------------------------------------------------------
// Processor feature configuration
//-----------------------------------------------------------------------------
// XLEN
parameter int XLEN = 32;
// Parameter for SATP mode, set to BARE if address translation is not supported
parameter satp_mode_t SATP_MODE = BARE;
// Supported Privileged mode
privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE};
// Unsupported instructions
riscv_instr_name_t unsupported_instr[];
// ISA supported by the processor
riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C, RV32X};
// Interrupt mode support
mtvec_mode_t supported_interrupt_mode[$] = {DIRECT, VECTORED};
// The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is
// supported
int max_interrupt_vector_num = 16;
// Physical memory protection support
bit support_pmp = 0;
// Debug mode support
bit support_debug_mode = 0;
// Support delegate trap to user mode
bit support_umode_trap = 0;
// Support sfence.vma instruction
bit support_sfence = 0;
// Support unaligned load/store
bit support_unaligned_load_store = 1'b1;
// Parameter for vector extension
parameter int VECTOR_EXTENSION_ENABLE = 0;
parameter int VLEN = 512;
parameter int ELEN = 64;
parameter int SLEN = 64;
// Number of harts
parameter int NUM_HARTS = 1;
// ----------------------------------------------------------------------------
// Previleged CSR implementation
// ----------------------------------------------------------------------------
// Implemented previlieged CSR list
`ifdef DSIM
privileged_reg_t implemented_csr[] = {
`else
const privileged_reg_t implemented_csr[] = {
`endif
// Machine mode mode CSR
MVENDORID, // Vendor ID
MARCHID, // Architecture ID
MIMPID, // Implementation ID
MHARTID, // Hardware thread ID
MSTATUS, // Machine status
MISA, // ISA and extensions
MIE, // Machine interrupt-enable register
MTVEC, // Machine trap-handler base address
MCOUNTEREN, // Machine counter enable
MSCRATCH, // Scratch register for machine trap handlers
MEPC, // Machine exception program counter
MCAUSE, // Machine trap cause
MTVAL, // Machine bad address or instruction
MIP // Machine interrupt pending
};
// ----------------------------------------------------------------------------
// Supported interrupt/exception setting, used for functional coverage
// ----------------------------------------------------------------------------
`ifdef DSIM
interrupt_cause_t implemented_interrupt[] = {
`else
const interrupt_cause_t implemented_interrupt[] = {
`endif
U_SOFTWARE_INTR,
S_SOFTWARE_INTR,
M_SOFTWARE_INTR,
U_TIMER_INTR,
S_TIMER_INTR,
M_TIMER_INTR,
U_EXTERNAL_INTR,
S_EXTERNAL_INTR,
M_EXTERNAL_INTR
};
`ifdef DSIM
exception_cause_t implemented_exception[] = {
`else
const exception_cause_t implemented_exception[] = {
`endif
INSTRUCTION_ADDRESS_MISALIGNED,
INSTRUCTION_ACCESS_FAULT,
ILLEGAL_INSTRUCTION,
BREAKPOINT,
LOAD_ADDRESS_MISALIGNED,
LOAD_ACCESS_FAULT,
STORE_AMO_ADDRESS_MISALIGNED,
STORE_AMO_ACCESS_FAULT,
ECALL_UMODE,
ECALL_SMODE,
ECALL_MMODE,
INSTRUCTION_PAGE_FAULT,
LOAD_PAGE_FAULT,
STORE_AMO_PAGE_FAULT
};

182
verif/env/corev-dv/target/rv32imcb/riscv_core_setting.sv vendored Normal file
View file

@ -0,0 +1,182 @@
/*
* Copyright 2019 Google LLC
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
//-----------------------------------------------------------------------------
// Processor feature configuration
//-----------------------------------------------------------------------------
// XLEN
parameter int XLEN = 32;
// Parameter for SATP mode, set to BARE if address translation is not supported
parameter satp_mode_t SATP_MODE = BARE;
// Supported Privileged mode
privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE};
// Unsupported instructions
riscv_instr_name_t unsupported_instr[];
// ISA supported by the processor
riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C, RV32B, RV32X};
// Interrupt mode support
mtvec_mode_t supported_interrupt_mode[$] = {DIRECT, VECTORED};
// The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is
// supported
int max_interrupt_vector_num = 16;
// Physical memory protection support
bit support_pmp = 0;
// Enhanced physical memory protection support
bit support_epmp = 0;
// Debug mode support
bit support_debug_mode = 0;
// Support delegate trap to user mode
bit support_umode_trap = 0;
// Support sfence.vma instruction
bit support_sfence = 0;
// Support unaligned load/store
bit support_unaligned_load_store = 1'b1;
// GPR setting
parameter int NUM_FLOAT_GPR = 32;
parameter int NUM_GPR = 32;
parameter int NUM_VEC_GPR = 32;
// ----------------------------------------------------------------------------
// Vector extension configuration
// ----------------------------------------------------------------------------
// Parameter for vector extension
parameter int VECTOR_EXTENSION_ENABLE = 0;
parameter int VLEN = 512;
// Maximum size of a single vector element
parameter int ELEN = 32;
// Minimum size of a sub-element, which must be at most 8-bits.
parameter int SELEN = 8;
// Maximum size of a single vector element (encoded in vsew format)
parameter int VELEN = int'($ln(ELEN)/$ln(2)) - 3;
// Maxium LMUL supported by the core
parameter int MAX_LMUL = 8;
// ----------------------------------------------------------------------------
// Multi-harts configuration
// ----------------------------------------------------------------------------
// Number of harts
parameter int NUM_HARTS = 1;
// ----------------------------------------------------------------------------
// Previleged CSR implementation
// ----------------------------------------------------------------------------
// Implemented previlieged CSR list
`ifdef DSIM
privileged_reg_t implemented_csr[] = {
`else
const privileged_reg_t implemented_csr[] = {
`endif
// Machine mode mode CSR
MVENDORID, // Vendor ID
MSTATUS, // Machine status
MSTATUSH, // Additional machine status register, RV32 only
MISA, // ISA and extensions
MIE, // Machine interrupt-enable register
MTVEC, // Machine trap-handler base address
MSCRATCH, // Scratch register for machine trap handlers
MEPC, // Machine exception program counter
MCAUSE, // Machine trap cause
MTVAL, // Machine bad address or instruction
MIP, // Machine interrupt pending
MCYCLE, // Machine cycle counter
MCYCLEH, // Upper 32 bits of MCYCLE, RV32I only
MINSTRETH, // Upper 32 bits of MINSTRET, RV32I only
MINSTRET, // Machine instructions-retired counter
// Machine Memory Protection
PMPCFG0, // Physical memory protection configuration
PMPCFG1, // Physical memory protection configuration, RV32 only
PMPCFG2, // Physical memory protection configuration
PMPCFG3, // Physical memory protection configuration, RV32 only
PMPADDR0, // Physical memory protection address register
PMPADDR1, // Physical memory protection address register
PMPADDR2, // Physical memory protection address register
PMPADDR3, // Physical memory protection address register
PMPADDR4, // Physical memory protection address register
PMPADDR5, // Physical memory protection address register
PMPADDR6, // Physical memory protection address register
PMPADDR7, // Physical memory protection address register
PMPADDR8, // Physical memory protection address register
PMPADDR9, // Physical memory protection address register
PMPADDR10, // Physical memory protection address register
PMPADDR11, // Physical memory protection address register
PMPADDR12, // Physical memory protection address register
PMPADDR13, // Physical memory protection address register
PMPADDR14, // Physical memory protection address register
PMPADDR15, // Physical memory protection address register
// Unprivileged Counter/Timers
CYCLE, // Cycle counter for RDCYCLE instruction
INSTRET, // Instructions-retired counter for RDINSTRET instruction
CYCLEH, // Upper 32 bits of CYCLE, RV32I only
INSTRETH // Upper 32 bits of INSTRET, RV32I only
};
// Implementation-specific custom CSRs
bit [11:0] custom_csr[] = {
};
// ----------------------------------------------------------------------------
// Supported interrupt/exception setting, used for functional coverage
// ----------------------------------------------------------------------------
`ifdef DSIM
interrupt_cause_t implemented_interrupt[] = {
`else
const interrupt_cause_t implemented_interrupt[] = {
`endif
M_SOFTWARE_INTR,
M_TIMER_INTR,
M_EXTERNAL_INTR
};
`ifdef DSIM
exception_cause_t implemented_exception[] = {
`else
const exception_cause_t implemented_exception[] = {
`endif
INSTRUCTION_ADDRESS_MISALIGNED,
INSTRUCTION_ACCESS_FAULT,
ILLEGAL_INSTRUCTION,
BREAKPOINT,
LOAD_ADDRESS_MISALIGNED,
LOAD_ACCESS_FAULT,
STORE_AMO_ADDRESS_MISALIGNED,
STORE_AMO_ACCESS_FAULT,
ECALL_MMODE,
INSTRUCTION_PAGE_FAULT,
LOAD_PAGE_FAULT,
STORE_AMO_PAGE_FAULT
};

2
verif/regress/dv-generated-tests.sh
View file

@ -111,7 +111,7 @@ printf "+=======================================================================
j=0
while [[ $j -lt ${#TEST_NAME[@]} ]];do
cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/
python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imc/ --mabi ilp32 --isa rv32imc --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300
python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300
n=0
echo "Generate the test: ${TEST_NAME[j]}"
#this while loop detects the failed tests from the log file and remove them

2
verif/regress/dv-generated-xif-tests.sh
View file

@ -74,7 +74,7 @@ printf "+=======================================================================
j=0
while [[ $j -lt ${#TEST_NAME[@]} ]];do
cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/
python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imc/ --mabi ilp32 --isa rv32imc --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300
python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300
n=0
echo "Generate the test: ${TEST_NAME[j]}"
#this while loop detects the failed tests from the log file and remove them

4
verif/regress/install-riscv-dv.sh
View file

@ -21,9 +21,9 @@ export TB_PATH=$ROOT_PROJECT/verif/tb/core
export TESTS_PATH=$ROOT_PROJECT/verif/tests
if [ -z "$DV_REPO" ]; then
export DV_REPO="https://github.com/google/riscv-dv.git"
export DV_REPO="https://github.com/chipsalliance/riscv-dv.git"
export DV_BRANCH="master"
export DV_HASH="96c1ee6f371f2754c45b4831fcab95f6671689d9"
export DV_HASH="f0c570d11236f94f9c5449870223a5ac717cc580"
export DV_PATCH=
fi
echo "Repo: " $DV_REPO

6
verif/regress/smoke-gen_tests.sh
View file

@ -27,9 +27,9 @@ fi
cd verif/sim/
cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/
python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_arithmetic_basic_test_comp --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300
python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_load_store_test --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300
python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_unaligned_load_store_test --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300
python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_arithmetic_basic_test_comp --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300
python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_load_store_test --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300
python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_unaligned_load_store_test --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300
make clean_all
cd -

138
verif/sim/cva6.py
View file

@ -18,6 +18,7 @@ Regression script for RISC-V random instruction generator
import argparse
import os
import random
import re
import sys
import logging
@ -36,6 +37,38 @@ from types import SimpleNamespace
LOGGER = logging.getLogger()
class SeedGen:
'''An object that will generate a pseudo-random seed for test iterations'''
def __init__(self, start_seed, fixed_seed, seed_yaml):
# These checks are performed with proper error messages at argument parsing
# time, but it can't hurt to do a belt-and-braces check here too.
assert fixed_seed is None or start_seed is None
self.fixed_seed = fixed_seed
self.start_seed = start_seed
self.rerun_seed = {} if seed_yaml is None else read_yaml(seed_yaml)
def get(self, test_id, test_iter):
'''Get the seed to use for the given test and iteration'''
if test_id in self.rerun_seed:
# Note that test_id includes the iteration index (well, the batch index,
# at any rate), so this makes sense even if test_iter > 0.
return self.rerun_seed[test_id]
if self.fixed_seed is not None:
# Checked at argument parsing time
assert test_iter == 0
return self.fixed_seed
if self.start_seed is not None:
return self.start_seed + test_iter
# If the user didn't specify seeds in some way, we generate a random seed
# every time
return random.getrandbits(31)
def get_generator_cmd(simulator, simulator_yaml, cov, exp, debug_cmd):
""" Setup the compile and simulation command for the generator
@ -197,7 +230,7 @@ def run_csr_test(cmd_list, cwd, csr_file, isa, iterations, lsf_cmd,
run_cmd(cmd, timeout_s, debug_cmd = debug_cmd)
def do_simulate(sim_cmd, test_list, cwd, sim_opts, seed_yaml, seed, csr_file,
def do_simulate(sim_cmd, test_list, cwd, sim_opts, seed_gen, csr_file,
isa, end_signature_addr, lsf_cmd, timeout_s, log_suffix,
batch_size, output_dir, verbose, check_return_code, debug_cmd):
"""Run the instruction generator
@ -207,8 +240,7 @@ def do_simulate(sim_cmd, test_list, cwd, sim_opts, seed_yaml, seed, csr_file,
test_list : List of assembly programs to be compiled
cwd : Filesystem path to RISCV-DV repo
sim_opts : Simulation options for the generator
seed_yaml : Seed specification from a prior regression
seed : Seed to the instruction generator
seed_gen : A SeedGen seed generator
csr_file : YAML file containing description of all CSRs
isa : Processor supported ISA subset
end_signature_addr : Address that tests will write pass/fail signature to at end of test
@ -224,9 +256,7 @@ def do_simulate(sim_cmd, test_list, cwd, sim_opts, seed_yaml, seed, csr_file,
sim_cmd = re.sub("<out>", os.path.abspath(output_dir), sim_cmd)
sim_cmd = re.sub("<cwd>", cwd, sim_cmd)
sim_cmd = re.sub("<sim_opts>", sim_opts, sim_cmd)
rerun_seed = {}
if seed_yaml:
rerun_seed = read_yaml(seed_yaml)
logging.info("Running RISC-V instruction generator")
sim_seed = {}
for test in test_list:
@ -244,10 +274,7 @@ def do_simulate(sim_cmd, test_list, cwd, sim_opts, seed_yaml, seed, csr_file,
logging.info("Running %s with %0d batches" % (test['test'], batch_cnt))
for i in range(0, batch_cnt):
test_id = '%0s_%0d' % (test['test'], i)
if test_id in rerun_seed:
rand_seed = rerun_seed[test_id]
else:
rand_seed = get_seed(seed)
rand_seed = seed_gen.get(test_id, i * batch_cnt)
if i < batch_cnt - 1:
test_cnt = batch_size
else:
@ -283,17 +310,15 @@ def do_simulate(sim_cmd, test_list, cwd, sim_opts, seed_yaml, seed, csr_file,
debug_cmd = debug_cmd)
def gen(test_list, cfg, output_dir, cwd):
def gen(test_list, argv, output_dir, cwd):
"""Run the instruction generator
Args:
test_list : List of assembly programs to be compiled
cfg : Loaded configuration dictionary.
argv : Configuration arguments
output_dir : Output directory of the ELF files
cwd : Filesystem path to RISCV-DV repo
"""
# Convert key dictionary to argv variable
argv= SimpleNamespace(**cfg)
check_return_code = True
if argv.simulator == "ius":
@ -317,7 +342,8 @@ def gen(test_list, cfg, output_dir, cwd):
argv.cmp_opts, output_dir, argv.debug, argv.lsf_cmd)
# Run the instruction generator
if not argv.co:
do_simulate(sim_cmd, test_list, cwd, argv.sim_opts, argv.seed_yaml, argv.seed, argv.csr_yaml,
seed_gen = SeedGen(argv.start_seed, argv.seed, argv.seed_yaml)
do_simulate(sim_cmd, test_list, cwd, argv.sim_opts, seed_gen, argv.csr_yaml,
argv.isa, argv.end_signature_addr, argv.lsf_cmd, argv.gen_timeout, argv.log_suffix,
argv.batch_size, output_dir, argv.verbose, check_return_code, argv.debug)
@ -727,7 +753,20 @@ def save_regr_report(report):
logging.info("ISS regression report is saved to %s" % report)
def setup_parser():
def read_seed(arg):
'''Read --seed or --seed_start'''
try:
seed = int(arg)
if seed < 0:
raise ValueError('bad seed')
return seed
except ValueError:
raise argparse.ArgumentTypeError('Bad seed ({}): '
'must be a non-negative integer.'
.format(arg))
def parse_args(cwd):
"""Create a command line parser.
Returns: The created parser.
@ -744,8 +783,6 @@ def setup_parser():
help="Regression testlist", dest="testlist")
parser.add_argument("-tn", "--test", type=str, default="all",
help="Test name, 'all' means all tests in the list", dest="test")
parser.add_argument("--seed", type=int, default=-1,
help="Randomization seed, default -1 means random seed")
parser.add_argument("-i", "--iterations", type=int, default=0,
help="Override the iteration count in the test list", dest="iterations")
parser.add_argument("-si", "--simulator", type=str, default="vcs",
@ -795,9 +832,6 @@ def setup_parser():
help="RTL simulator setting YAML")
parser.add_argument("--csr_yaml", type=str, default="",
help="CSR description file")
parser.add_argument("--seed_yaml", type=str, default="",
help="Rerun the generator with the seed specification \
from a prior regression")
parser.add_argument("-ct", "--custom_target", type=str, default="",
help="Directory name of the custom target")
parser.add_argument("-cs", "--core_setting_dir", type=str, default="",
@ -838,8 +872,47 @@ def setup_parser():
help="Run test with a specific seed")
parser.add_argument("--isa_extension", type=str, default="",
help="Choose additional z, s, x extensions")
return parser
rsg = parser.add_argument_group('Random seeds',
'To control random seeds, use at most one '
'of the --start_seed, --seed or --seed_yaml '
'arguments. Since the latter two only give '
'a single seed for each test, they imply '
'--iterations=1.')
rsg.add_argument("--start_seed", type=read_seed,
help=("Randomization seed to use for first iteration of "
"each test. Subsequent iterations use seeds "
"counting up from there. Cannot be used with "
"--seed or --seed_yaml."))
rsg.add_argument("--seed", type=read_seed,
help=("Randomization seed to use for each test. "
"Implies --iterations=1. Cannot be used with "
"--start_seed or --seed_yaml."))
rsg.add_argument("--seed_yaml", type=str,
help=("Rerun the generator with the seed specification "
"from a prior regression. Implies --iterations=1. "
"Cannot be used with --start_seed or --seed."))
args = parser.parse_args()
if args.seed is not None and args.start_seed is not None:
logging.error('--start_seed and --seed are mutually exclusive.')
sys.exit(RET_FAIL)
if args.seed is not None:
if args.iterations == 0:
args.iterations = 1
elif args.iterations > 1:
logging.error('--seed is incompatible with setting --iterations '
'greater than 1.')
sys.exit(RET_FAIL)
# We've parsed all the arguments from the command line; default values
# can be set in the config file. Read that here.
load_config(args, cwd)
return args
def load_config(args, cwd):
"""
@ -948,19 +1021,19 @@ def load_config(args, cwd):
sys.exit("mabi and isa must be specified for custom target %0s" % args.custom_target)
if not args.testlist:
args.testlist = args.custom_target + "/testlist.yaml"
# Create loaded configuration dictionary.
cfg = vars(args)
return cfg
def main():
"""This is the main entry point."""
try:
parser = setup_parser()
args = parser.parse_args()
global issrun_opts
global test_iteration
global log_format
cwd = os.path.dirname(os.path.realpath(__file__))
os.environ["RISCV_DV_ROOT"] = cwd + "/dv"
os.environ["CVA6_DV_ROOT"] = cwd + "/../env/corev-dv"
args = parse_args(cwd)
if args.axi_active == "yes":
args.issrun_opts = args.issrun_opts + " +uvm_set_config_int=*uvm_test_top,force_axi_mode,1"
elif args.axi_active == "no":
@ -985,9 +1058,6 @@ def main():
isspostrun_opts = "\""+args.isspostrun_opts+"\""
global isscomp_opts
isscomp_opts = "\""+args.isscomp_opts+"\""
cwd = os.path.dirname(os.path.realpath(__file__))
os.environ["RISCV_DV_ROOT"] = cwd + "/dv"
os.environ["CVA6_DV_ROOT"] = cwd + "/../env/corev-dv"
setup_logging(args.verbose)
logg = logging.getLogger()
#Check gcc version
@ -1013,8 +1083,6 @@ def main():
fh.setFormatter(formatter)
logg.addHandler(fh)
# Load configuration from the command line and the configuration file.
cfg = load_config(args, cwd)
# Create output directory
output_dir = create_output(args.o, args.noclean, cwd+"/out_")
@ -1097,7 +1165,7 @@ def main():
if test_executed ==0:
if not args.co:
process_regression_list(args.testlist, args.test, args.iterations, matched_list, cwd)
logging.info('CVA6 Configuration is %s'% cfg["hwconfig_opts"])
logging.info('CVA6 Configuration is %s'% args.hwconfig_opts)
for entry in list(matched_list):
yaml_needs = entry["needs"] if "needs" in entry else []
if yaml_needs:
@ -1105,7 +1173,7 @@ def main():
for i in range(len(yaml_needs)):
needs.update(yaml_needs[i])
for keys in needs.keys():
if cfg["hwconfig_opts"][keys] != needs[keys]:
if args.hwconfig_opts[keys] != needs[keys]:
logging.info('Removing test %s CVA6 configuration can not run it' % entry['test'])
matched_list.remove(entry)
break
@ -1195,7 +1263,7 @@ def main():
sys.exit(RET_FAIL)
# Run remaining tests using the instruction generator
gen(matched_list, cfg, output_dir, cwd)
gen(matched_list, args, output_dir, cwd)
if not args.co:
# Compile the assembly program to ELF, convert to plain binary