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Merge branch 'fpga_dev' of github.com:pulp-platform/ariane into fpga_dev

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Florian Zaruba 2018-10-29 12:06:37 +01:00
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169
fpga/ariane.srcs/sources_1/ip/axi_quad_spi_0/axi_quad_spi_0.xci Normal file
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@ -0,0 +1,169 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>axi_quad_spi_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_quad_spi" spirit:version="3.2"/>
<spirit:configurableElementValues>
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6
fpga/constraints/genesys-2.xdc
View file

@ -58,3 +58,9 @@ set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports fan_pwm]
#set_property -dict { PACKAGE_PIN AK15 IOSTANDARD LVCMOS18 } [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb
#set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS15 } [get_ports { eth_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl
#set_property -dict { PACKAGE_PIN AK16 IOSTANDARD LVCMOS18 } [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb
## SD Card
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS33} [get_ports spi_clk_o]
set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS33} [get_ports spi_ss]
set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS33} [get_ports spi_miso]
set_property -dict {PACKAGE_PIN R29 IOSTANDARD LVCMOS33} [get_ports spi_mosi]

204
fpga/src/ariane_peripherals.sv
View file

@ -10,17 +10,24 @@
// Xilinx Peripehrals
module ariane_peripherals #(
parameter AxiAddrWidth = -1,
parameter AxiDataWidth = -1
)(
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
AXI_BUS.in plic,
AXI_BUS.in uart,
output logic [1:0] irq_o,
parameter AxiAddrWidth = -1,
parameter AxiDataWidth = -1
) (
input logic clk_i , // Clock
input logic rst_ni , // Asynchronous reset active low
AXI_BUS.in plic ,
AXI_BUS.in uart ,
AXI_BUS.in spi ,
output logic [1:0] irq_o ,
// UART
input logic rx_i,
output logic tx_o
input logic rx_i ,
output logic tx_o ,
// SPI
output logic spi_clk_o ,
output logic spi_mosi ,
input logic spi_miso ,
output logic spi_ss ,
output logic spi_ip2intc_irtp
);
// ---------------
@ -174,6 +181,9 @@ module ariane_peripherals #(
.SOUT ( tx_o )
);
// ---------------
// Ethernet
// ---------------
// xlnx_axi_ethernetlite i_xlnx_axi_ethernetlite (
// );
@ -236,4 +246,178 @@ module ariane_peripherals #(
// // set floating - power management event
// assign eth_pme_b = 1'b1;
// ---------------
// SPI
// ---------------
logic [31:0] s_axi_spi_awaddr;
logic [7:0] s_axi_spi_awlen;
logic [2:0] s_axi_spi_awsize;
logic [1:0] s_axi_spi_awburst;
logic [0:0] s_axi_spi_awlock;
logic [3:0] s_axi_spi_awcache;
logic [2:0] s_axi_spi_awprot;
logic [3:0] s_axi_spi_awregion;
logic [3:0] s_axi_spi_awqos;
logic s_axi_spi_awvalid;
logic s_axi_spi_awready;
logic [31:0] s_axi_spi_wdata;
logic [3:0] s_axi_spi_wstrb;
logic s_axi_spi_wlast;
logic s_axi_spi_wvalid;
logic s_axi_spi_wready;
logic [1:0] s_axi_spi_bresp;
logic s_axi_spi_bvalid;
logic s_axi_spi_bready;
logic [31:0] s_axi_spi_araddr;
logic [7:0] s_axi_spi_arlen;
logic [2:0] s_axi_spi_arsize;
logic [1:0] s_axi_spi_arburst;
logic [0:0] s_axi_spi_arlock;
logic [3:0] s_axi_spi_arcache;
logic [2:0] s_axi_spi_arprot;
logic [3:0] s_axi_spi_arregion;
logic [3:0] s_axi_spi_arqos;
logic s_axi_spi_arvalid;
logic s_axi_spi_arready;
logic [31:0] s_axi_spi_rdata;
logic [1:0] s_axi_spi_rresp;
logic s_axi_spi_rlast;
logic s_axi_spi_rvalid;
logic s_axi_spi_rready;
axi_dwidth_converter_0 i_axi_dwidth_converter_spi (
.s_axi_aclk ( clk_i ),
.s_axi_aresetn ( rst_ni ),
.s_axi_awid ( spi.aw_id ),
.s_axi_awaddr ( spi.aw_addr[31:0] ),
.s_axi_awlen ( spi.aw_len ),
.s_axi_awsize ( spi.aw_size ),
.s_axi_awburst ( spi.aw_burst ),
.s_axi_awlock ( spi.aw_lock ),
.s_axi_awcache ( spi.aw_cache ),
.s_axi_awprot ( spi.aw_prot ),
.s_axi_awregion ( spi.aw_region ),
.s_axi_awqos ( spi.aw_qos ),
.s_axi_awvalid ( spi.aw_valid ),
.s_axi_awready ( spi.aw_ready ),
.s_axi_wdata ( spi.w_data ),
.s_axi_wstrb ( spi.w_strb ),
.s_axi_wlast ( spi.w_last ),
.s_axi_wvalid ( spi.w_valid ),
.s_axi_wready ( spi.w_ready ),
.s_axi_bid ( spi.b_id ),
.s_axi_bresp ( spi.b_resp ),
.s_axi_bvalid ( spi.b_valid ),
.s_axi_bready ( spi.b_ready ),
.s_axi_arid ( spi.ar_id ),
.s_axi_araddr ( spi.ar_addr[31:0] ),
.s_axi_arlen ( spi.ar_len ),
.s_axi_arsize ( spi.ar_size ),
.s_axi_arburst ( spi.ar_burst ),
.s_axi_arlock ( spi.ar_lock ),
.s_axi_arcache ( spi.ar_cache ),
.s_axi_arprot ( spi.ar_prot ),
.s_axi_arregion ( spi.ar_region ),
.s_axi_arqos ( spi.ar_qos ),
.s_axi_arvalid ( spi.ar_valid ),
.s_axi_arready ( spi.ar_ready ),
.s_axi_rid ( spi.r_id ),
.s_axi_rdata ( spi.r_data ),
.s_axi_rresp ( spi.r_resp ),
.s_axi_rlast ( spi.r_last ),
.s_axi_rvalid ( spi.r_valid ),
.s_axi_rready ( spi.r_ready ),
.m_axi_awaddr ( s_axi_spi_awaddr ),
.m_axi_awlen ( s_axi_spi_awlen ),
.m_axi_awsize ( s_axi_spi_awsize ),
.m_axi_awburst ( s_axi_spi_awburst ),
.m_axi_awlock ( s_axi_spi_awlock ),
.m_axi_awcache ( s_axi_spi_awcache ),
.m_axi_awprot ( s_axi_spi_awprot ),
.m_axi_awregion ( s_axi_spi_awregion ),
.m_axi_awqos ( s_axi_spi_awqos ),
.m_axi_awvalid ( s_axi_spi_awvalid ),
.m_axi_awready ( s_axi_spi_awready ),
.m_axi_wdata ( s_axi_spi_wdata ),
.m_axi_wstrb ( s_axi_spi_wstrb ),
.m_axi_wlast ( s_axi_spi_wlast ),
.m_axi_wvalid ( s_axi_spi_wvalid ),
.m_axi_wready ( s_axi_spi_wready ),
.m_axi_bresp ( s_axi_spi_bresp ),
.m_axi_bvalid ( s_axi_spi_bvalid ),
.m_axi_bready ( s_axi_spi_bready ),
.m_axi_araddr ( s_axi_spi_araddr ),
.m_axi_arlen ( s_axi_spi_arlen ),
.m_axi_arsize ( s_axi_spi_arsize ),
.m_axi_arburst ( s_axi_spi_arburst ),
.m_axi_arlock ( s_axi_spi_arlock ),
.m_axi_arcache ( s_axi_spi_arcache ),
.m_axi_arprot ( s_axi_spi_arprot ),
.m_axi_arregion ( s_axi_spi_arregion ),
.m_axi_arqos ( s_axi_spi_arqos ),
.m_axi_arvalid ( s_axi_spi_arvalid ),
.m_axi_arready ( s_axi_spi_arready ),
.m_axi_rdata ( s_axi_spi_rdata ),
.m_axi_rresp ( s_axi_spi_rresp ),
.m_axi_rlast ( s_axi_spi_rlast ),
.m_axi_rvalid ( s_axi_spi_rvalid ),
.m_axi_rready ( s_axi_spi_rready )
);
axi_quad_spi_0 i_axi_spi (
.ext_spi_clk ( clk_i ),
.s_axi4_aclk ( clk_i ),
.s_axi4_aresetn ( rst_ni ),
.s_axi4_awaddr ( s_axi_spi_awaddr[23:0] ),
.s_axi4_awlen ( s_axi_spi_awlen ),
.s_axi4_awsize ( s_axi_spi_awsize ),
.s_axi4_awburst ( s_axi_spi_awburst ),
.s_axi4_awlock ( s_axi_spi_awlock ),
.s_axi4_awcache ( s_axi_spi_awcache ),
.s_axi4_awprot ( s_axi_spi_awprot ),
.s_axi4_awvalid ( s_axi_spi_awvalid ),
.s_axi4_awready ( s_axi_spi_awready ),
.s_axi4_wdata ( s_axi_spi_wdata ),
.s_axi4_wstrb ( s_axi_spi_wstrb ),
.s_axi4_wlast ( s_axi_spi_wlast ),
.s_axi4_wvalid ( s_axi_spi_wvalid ),
.s_axi4_wready ( s_axi_spi_wready ),
.s_axi4_bresp ( s_axi_spi_bresp ),
.s_axi4_bvalid ( s_axi_spi_bvalid ),
.s_axi4_bready ( s_axi_spi_bready ),
.s_axi4_araddr ( s_axi_spi_araddr[23:0] ),
.s_axi4_arlen ( s_axi_spi_arlen ),
.s_axi4_arsize ( s_axi_spi_arsize ),
.s_axi4_arburst ( s_axi_spi_arburst ),
.s_axi4_arlock ( s_axi_spi_arlock ),
.s_axi4_arcache ( s_axi_spi_arcache ),
.s_axi4_arprot ( s_axi_spi_arprot ),
.s_axi4_arvalid ( s_axi_spi_arvalid ),
.s_axi4_arready ( s_axi_spi_arready ),
.s_axi4_rdata ( s_axi_spi_rdata ),
.s_axi4_rresp ( s_axi_spi_rresp ),
.s_axi4_rlast ( s_axi_spi_rlast ),
.s_axi4_rvalid ( s_axi_spi_rvalid ),
.s_axi4_rready ( s_axi_spi_rready ),
.io0_i ( '0 ),
.io0_o ( spi_mosi ),
.io0_t ( '0 ),
.io1_i ( spi_miso ),
.io1_o ( ),
.io1_t ( '0 ),
.ss_i ( '0 ),
.ss_o ( spi_ss ),
.ss_t ( '0 ),
.ip2intc_irpt ( spi_ip2intc_irtp ),
.cfgclk ( spi_clk_o ),
.cfgmclk ( ),
.eos ( ),
.preq ( )
);
endmodule

35
fpga/src/ariane_xilinx.sv
View file

@ -40,7 +40,14 @@ module ariane_xilinx (
output logic [7:0] led,
input logic [7:0] sw,
output logic fan_pwm
output logic fan_pwm,
// SPI
output logic spi_mosi,
input logic spi_miso,
output logic spi_ss,
output logic spi_clk_o
//output logic spi_ip2intc_irtp
);
localparam NBSlave = 4; // debug, Instruction fetch, data bypass, data
@ -263,6 +270,7 @@ axi_node_intf_wrap #(
ariane_soc::CLINTBase,
ariane_soc::PLICBase,
ariane_soc::UARTBase,
ariane_soc::SPIBase,
ariane_soc::DRAMBase
}),
.end_addr_i ({
@ -271,6 +279,7 @@ axi_node_intf_wrap #(
ariane_soc::CLINTBase + ariane_soc::CLINTLength,
ariane_soc::PLICBase + ariane_soc::PLICLength,
ariane_soc::UARTBase + ariane_soc::UARTLength,
ariane_soc::SPIBase + ariane_soc::SPILength,
ariane_soc::DRAMBase + ariane_soc::DRAMLength
})
);
@ -404,16 +413,22 @@ bootrom i_bootrom (
// Peripherals
// ---------------
ariane_peripherals #(
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth )
.AxiAddrWidth(AxiAddrWidth),
.AxiDataWidth(AxiDataWidth)
) i_ariane_peripherals (
.clk_i ( clk ),
.rst_ni ( ndmreset_n ),
.plic ( master[ariane_soc::PLIC] ),
.uart ( master[ariane_soc::UART] ),
.irq_o ( irq ),
.rx_i ( rx ),
.tx_o ( tx )
.clk_i (clk ),
.rst_ni (ndmreset_n ),
.plic (master[ariane_soc::PLIC]),
.uart (master[ariane_soc::UART]),
.spi (master[ariane_soc::SPI] ),
.irq_o (irq ),
.rx_i (rx ),
.tx_o (tx ),
.spi_clk_o (spi_clk_o ),
.spi_mosi (spi_mosi ),
.spi_miso (spi_miso ),
.spi_ss (spi_ss ),
.spi_ip2intc_irtp( )
);
// ---------------------

16
tb/ariane_soc_pkg.sv
View file

@ -12,17 +12,19 @@
// Description: Contains SoC information as constants
package ariane_soc;
localparam NB_PERIPHERALS = 6;
localparam NB_PERIPHERALS = 7;
localparam NumTargets = 2;
localparam NumSources = 1;
typedef enum int unsigned {
DRAM = 0,
UART = 1,
PLIC = 2,
CLINT = 3,
ROM = 4,
Debug = 5
SPI = 1,
UART = 2,
PLIC = 3,
CLINT = 4,
ROM = 5,
Debug = 6
} axi_slaves_t;
typedef enum logic [63:0] {
@ -31,6 +33,7 @@ package ariane_soc;
CLINTBase = 64'h0200_0000,
PLICBase = 64'h0C00_0000,
UARTBase = 64'h1000_0000,
SPIBase = 64'h2000_0000,
DRAMBase = 64'h8000_0000
} soc_bus_start_t;
@ -39,5 +42,6 @@ package ariane_soc;
localparam logic[63:0] CLINTLength = 64'hC0000;
localparam logic[63:0] PLICLength = 64'h3FF_FFFF;
localparam logic[63:0] UARTLength = 64'h10000;
localparam logic[63:0] SPILength = 64'h1000;
localparam logic[63:0] DRAMLength = 64'h8000000;
endpackage