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Merge remote-tracking branch 'origin' into riscv-compliant-debug

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Florian Zaruba 2018-07-24 17:08:37 -07:00
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@ -19,7 +19,7 @@ git clone https://github.com/pulp-platform/ariane.git
git submodule update --init --recursive
```
The Verilator testbench relies on our forked version of `riscv-fesvr` which can be found [here](https://github.com/pulp-platform/riscv-fesvr). Follow the README there and make sure that your compiler and linker is aware of the library (e.g.: add it to your path if it is in a non-default directory).
The Verilator testbench relies on our forked version of `riscv-fesvr` which can be found [here](https://github.com/riscv/riscv-fesvr). Follow the README there and make sure that your compiler and linker is aware of the library (e.g.: add it to your path if it is in a non-default directory).
Build the Verilator model of Ariane by using the Makefile:
```
@ -34,8 +34,6 @@ obj_dir/Variane_wrapped -p rv64um-v-divuw
The Verilator testbench makes use of the `riscv-fesvr`. That means that bare `riscv-tests` can be run on the simulator.
> Due to the way the C++ testbench is constructed we need a slightly altered version of the `riscv-fesvr` which can be found [here](https://github.com/pulp-platform/riscv-fesvr).
### Running custom C-code
It is possible to cross compile and run your own C-code or benchmarks on Ariane. The following steps need to be followed to compile and run:
@ -60,8 +58,6 @@ obj_dir/Variane_wrapped -p hello.riscv
While developing Ariane it has become evident that, in order to support Linux, the atomic extension is going to be mandatory. While the core is currently booting Linux by emulating Atomics in BBL (in a single core environment this is trivially met by disabling interrupts) this is not the behavior which is intended. For that reason we are going to fully support all atomic extensions in the very near future.
Furthermore, we have major IPC improvements planned. Specifically this will resolve about the way branches and jumps are currently handled in the core.
## Going Beyond
The core has been developed with a full licensed version of QuestaSim. If you happen to have this simulator available yourself here is how you could run the core with it. You need to generate **both** an `elf` file and a `hex` file, most easily this can be done by calling: