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Simplify the Verilog "inside" (from @flaviens) (#2776)
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Hi! Some tools like morty struggle with this expression. I suggest this very simple rewrite. No need for fancy constructs here.
Thanks @flaviens for this contribution
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JeanRochCoulon 2025-02-19 09:45:30 +01:00 • committed by GitHub
parent be7c8746c6
commit e4c28b0b03
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9
core/cva6.sv
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@ -1385,10 +1385,11 @@ module cva6
.inval_valid_i (inval_valid),
.inval_ready_o (inval_ready)
);
end else if (CVA6Cfg.DCacheType inside {
config_pkg::HPDCACHE_WT,
config_pkg::HPDCACHE_WB,
config_pkg::HPDCACHE_WT_WB})
end else if (
CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WT ||
CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WB ||
CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WT_WB
)
begin : gen_cache_hpd
cva6_hpdcache_subsystem #(
.CVA6Cfg (CVA6Cfg),