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CVXIF DV-PLAN : Add dv plan for custom instructions
This commit is contained in:
Ayoub Jalali
parent
18bccb863e
commit
e5a35cf1b7
3 changed files with 1016 additions and 0 deletions
402
cva6/docs/VerifPlans/CVXIF/VP_IP003.yml
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402
cva6/docs/VerifPlans/CVXIF/VP_IP003.yml
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@ -0,0 +1,402 @@
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!Feature
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next_elt_id: 8
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name: Custom Instructions
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id: 3
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display_order: 3
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subfeatures: !!omap
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- 000_CUS_ADD: !Subfeature
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name: 000_CUS_ADD
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tag: VP_CVXIF_F003_S000
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next_elt_id: 4
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display_order: 0
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items: !!omap
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- '000': !VerifItem
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name: '000'
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tag: VP_CVXIF_F003_S000_I000
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description: "cus_add rd, rs1, rs2\nrd = rs1 + rs2\ncus_add works in all privilege\
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\ modes"
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reqt_doc: ./custom_instruction.rst
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ref_mode: page
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ref_page: ''
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ref_section: ''
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ref_viewer: firefox
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verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
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All possible rs2 registers are used.\nAll possible rd registers are used.\n\
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All possible register combinations where rs1 == rd are used\nAll possible\
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\ register combinations where rs2 == rd are used"
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pfc: 3
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test_type: 3
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cov_method: 1
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cores: 56
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coverage_loc: ''
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comments: ''
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- '001': !VerifItem
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name: '001'
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tag: VP_CVXIF_F003_S000_I001
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description: "cus_add rd, rs1, rs2\nrd = rs1 + rs2\ncus_add works in all privilege\
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\ modes"
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reqt_doc: ./custom_instruction.rst
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ref_mode: page
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ref_page: ''
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ref_section: ''
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ref_viewer: firefox
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verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\
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\ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\
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\ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
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pfc: -1
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test_type: -1
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cov_method: -1
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cores: 56
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coverage_loc: ''
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comments: ''
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- '002': !VerifItem
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name: '002'
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tag: VP_CVXIF_F003_S000_I002
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description: "cus_add rd, rs1, rs2\nrd = rs1 + rs2\ncus_add works in all privilege\
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\ modes"
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reqt_doc: ./custom_instruction.rst
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ref_mode: page
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ref_page: ''
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ref_section: ''
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ref_viewer: firefox
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verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
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\ rd are toggled"
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pfc: -1
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test_type: -1
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cov_method: -1
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cores: 56
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coverage_loc: ''
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comments: ''
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- 001_CUS_NOP: !Subfeature
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name: 001_CUS_NOP
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tag: VP_CVXIF_F003_S001
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next_elt_id: 1
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display_order: 1
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items: !!omap
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- '000': !VerifItem
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name: '000'
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tag: VP_CVXIF_F003_S001_I000
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description: No operation Instruction
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reqt_doc: ./custom_instruction.rst
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ref_mode: page
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ref_page: ''
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ref_section: ''
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ref_viewer: firefox
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verif_goals: Instruction executed
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pfc: 3
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test_type: 3
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cov_method: 1
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cores: 56
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coverage_loc: ''
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comments: ''
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- 003_CUS_S_ADD: !Subfeature
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name: 003_CUS_S_ADD
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tag: VP_CVXIF_F003_S003
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next_elt_id: 3
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display_order: 3
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items: !!omap
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- '000': !VerifItem
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name: '000'
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tag: VP_CVXIF_F003_S003_I000
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description: "cus_s_add rd, rs1, rs2\nrd = rs1 + rs2\ncus_s_add works in supervisor\
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\ privilege mode"
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reqt_doc: ./custom_instruction.rst
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ref_mode: page
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ref_page: ''
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ref_section: ''
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ref_viewer: firefox
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verif_goals: "Register operands:\n\nif (mode == s)\nAll possible rs1 registers\
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\ are used.\nAll possible rs2 registers are used.\nAll possible rd registers\
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\ are used.\nAll possible register combinations where rs1 == rd are used\n\
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All possible register combinations where rs2 == rd are used\n\nelse if (mode\
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\ != s)\nillegal exception raised on hte CPU"
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pfc: 3
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test_type: 3
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cov_method: 1
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cores: 56
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coverage_loc: ''
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comments: ''
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- '001': !VerifItem
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name: '001'
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tag: VP_CVXIF_F003_S003_I001
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description: "cus_s_add rd, rs1, rs2\nrd = rs1 + rs2\ncus_s_add works in supervisor\
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\ privilege mode"
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reqt_doc: ./custom_instruction.rst
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ref_mode: page
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ref_page: ''
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ref_section: ''
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ref_viewer: firefox
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verif_goals: "Input operands:\n\nif (mode == s)\nrs1 value is +ve, -ve and\
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\ zero\nrs2 value is +ve, -ve and zero\nAll combinations of rs1 and rs2\
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\ +ve, -ve, and zero values are used\nAll bits of rs1 are toggled\nAll bits\
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\ of rs2 are toggled\n\nelse if (mode != s)\nillegal exception raised on\
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\ the CPU"
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pfc: -1
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test_type: -1
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cov_method: -1
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cores: 56
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coverage_loc: ''
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comments: ''
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- '002': !VerifItem
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name: '002'
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tag: VP_CVXIF_F003_S003_I002
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description: "cus_s_add rd, rs1, rs2\nrd = rs1 + rs2\ncus_s_add works in supervisor\
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\ privilege mode"
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reqt_doc: ./custom_instruction.rst
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ref_mode: page
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ref_page: ''
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ref_section: ''
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ref_viewer: firefox
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verif_goals: "Output operands:\n\nif (mode == s)\nrd value is +ve, -ve and\
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\ zero\nAll bits of rd are toggled\n\nelse if (mode != s)\nillegal exception\
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\ raised on the CPU"
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pfc: -1
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test_type: -1
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cov_method: -1
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cores: 56
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coverage_loc: ''
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comments: ''
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- 004_CUS_U_ADD: !Subfeature
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name: 004_CUS_U_ADD
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tag: VP_CVXIF_F003_S004
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next_elt_id: 3
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display_order: 4
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items: !!omap
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- '000': !VerifItem
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name: '000'
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tag: VP_CVXIF_F003_S004_I000
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description: "cus_u_add rd, rs1, rs2\nrd = rs1 + rs2\ncus_u_add works in User\
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\ privilege mode"
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reqt_doc: ./custom_instruction.rst
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ref_mode: page
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ref_page: ''
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ref_section: ''
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ref_viewer: firefox
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verif_goals: "Register operands:\n\nif (mode == u)\nAll possible rs1 registers\
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\ are used.\nAll possible rs2 registers are used.\nAll possible rd registers\
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\ are used.\nAll possible register combinations where rs1 == rd are used\n\
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All possible register combinations where rs2 == rd are used\n\nelse if (mode\
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\ != u)\nillegal exception raised on hte CPU"
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pfc: 3
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test_type: 3
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cov_method: 1
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cores: 56
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coverage_loc: ''
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comments: ''
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- '001': !VerifItem
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name: '001'
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tag: VP_CVXIF_F003_S004_I001
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description: "cus_u_add rd, rs1, rs2\nrd = rs1 + rs2\ncus_u_add works in User\
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\ privilege mode"
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reqt_doc: ./custom_instruction.rst
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ref_mode: page
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ref_page: ''
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ref_section: ''
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ref_viewer: firefox
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verif_goals: "Input operands:\n\nif (mode == u)\nrs1 value is +ve, -ve and\
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\ zero\nrs2 value is +ve, -ve and zero\nAll combinations of rs1 and rs2\
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\ +ve, -ve, and zero values are used\nAll bits of rs1 are toggled\nAll bits\
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\ of rs2 are toggled\n\nelse if (mode != u)\nillegal exception raised on\
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\ the CPU"
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pfc: -1
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test_type: -1
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cov_method: -1
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cores: 56
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coverage_loc: ''
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comments: ''
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- '002': !VerifItem
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name: '002'
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tag: VP_CVXIF_F003_S004_I002
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description: "cus_u_add rd, rs1, rs2\nrd = rs1 + rs2\ncus_u_add works in User\
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\ privilege mode"
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reqt_doc: ./custom_instruction.rst
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ref_mode: page
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ref_page: ''
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ref_section: ''
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ref_viewer: firefox
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verif_goals: "Output operands:\n\nif (mode == u)\nrd value is +ve, -ve and\
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\ zero\nAll bits of rd are toggled\n\nelse if (mode != u)\nillegal exception\
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\ raised on the CPU"
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pfc: -1
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test_type: -1
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cov_method: -1
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cores: 56
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coverage_loc: ''
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comments: ''
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- 005_CUS_ADD_MULTI: !Subfeature
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name: 005_CUS_ADD_MULTI
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tag: VP_CVXIF_F003_S005
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next_elt_id: 4
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display_order: 5
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items: !!omap
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- '000': !VerifItem
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name: '000'
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tag: VP_CVXIF_F003_S005_I000
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description: "cus_add_multi rd, rs1, rs2\nrd = rs1 + rs2\ncus_add_multi works\
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\ in all privilege modes"
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reqt_doc: ./custom_instruction.rst
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ref_mode: page
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ref_page: ''
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ref_section: ''
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ref_viewer: firefox
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verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
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All possible rs2 registers are used.\nAll possible rd registers are used.\n\
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All possible register combinations where rs1 == rd are used\nAll possible\
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\ register combinations where rs2 == rd are used"
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pfc: 3
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test_type: 3
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cov_method: 1
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cores: 56
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coverage_loc: ''
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comments: ''
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- '001': !VerifItem
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name: '001'
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tag: VP_CVXIF_F003_S005_I001
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description: "cus_add_multi rd, rs1, rs2\nrd = rs1 + rs2\ncus_add_multi works\
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\ in all privilege modes"
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reqt_doc: ./custom_instruction.rst
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ref_mode: page
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ref_page: ''
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ref_section: ''
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ref_viewer: firefox
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verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\
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\ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\
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\ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
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pfc: -1
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test_type: -1
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cov_method: -1
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cores: 56
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coverage_loc: ''
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comments: ''
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- '002': !VerifItem
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name: '002'
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tag: VP_CVXIF_F003_S005_I002
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description: "cus_add_multi rd, rs1, rs2\nrd = rs1 + rs2\ncus_add_multi works\
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\ in all privilege modes"
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reqt_doc: ./custom_instruction.rst
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ref_mode: page
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ref_page: ''
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ref_section: ''
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ref_viewer: firefox
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verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
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\ rd are toggled"
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pfc: -1
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test_type: -1
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cov_method: -1
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cores: 56
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coverage_loc: ''
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comments: ''
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- '003': !VerifItem
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name: '003'
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tag: VP_CVXIF_F003_S005_I003
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description: "cus_add_multi rd, rs1, rs2\nrd = rs1 + rs2\ncus_add_multi works\
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\ in all privilege modes"
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reqt_doc: ./custom_instruction.rst
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ref_mode: page
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ref_page: ''
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ref_section: ''
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ref_viewer: firefox
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verif_goals: Check all delays from min to max
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pfc: 3
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test_type: 3
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cov_method: 1
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cores: 56
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coverage_loc: ''
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comments: ''
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- 006_CUS_EXC: !Subfeature
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name: 006_CUS_EXC
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tag: VP_CVXIF_F003_S006
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next_elt_id: 1
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display_order: 6
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items: !!omap
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- '000': !VerifItem
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name: '000'
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tag: VP_CVXIF_F003_S006_I000
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description: "cus_exc imm[5:0]\nmcause[5:0] = imm[5:0]\ncus_exc raise an exception\
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\ on the CPU base on the imm value"
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reqt_doc: ./custom_instruction.rst
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ref_mode: page
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ref_page: ''
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ref_section: ''
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ref_viewer: firefox
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verif_goals: Check all possible imm value
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pfc: -1
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test_type: -1
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cov_method: -1
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cores: 56
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coverage_loc: ''
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comments: ''
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- 007_CUS_ADD_RS3: !Subfeature
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name: 007_CUS_ADD_RS3
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tag: VP_CVXIF_F003_S007
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next_elt_id: 3
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display_order: 7
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items: !!omap
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- '000': !VerifItem
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name: '000'
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tag: VP_CVXIF_F003_S007_I000
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description: "cus_add_rs3 rd, rs1, rs2, rs3\nrd = rs1 + rs2 + rs3\ncus_add_rs3\
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\ works in all privilege modes\n\nX_NUM_RS == 3"
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reqt_doc: ./custom_instruction.rst
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ref_mode: page
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ref_page: ''
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ref_section: ''
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ref_viewer: firefox
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verif_goals: "Register operands:\n\nif (X_NUM_RS == 3)\nAll possible rs1 registers\
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\ are used.\nAll possible rs2 registers are used.\nAll possible rs3 registers\
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\ are used.\nAll possible rd registers are used.\nAll possible register\
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\ combinations where rs1 == rd are used\nAll possible register combinations\
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\ where rs2 == rd are used\nAll possible register combinations where rs3\
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\ == rd are used\n\n\nelse if (X_NUM_RS != 3)\nillegal exception raised\
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\ on the CPU"
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pfc: 3
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test_type: 3
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cov_method: 1
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cores: 56
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coverage_loc: ''
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comments: ''
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- '001': !VerifItem
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name: '001'
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tag: VP_CVXIF_F003_S007_I001
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description: "cus_add_rs3 rd, rs1, rs2, rs3\nrd = rs1 + rs2 + rs3\ncus_add_rs3\
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\ works in all privilege modes\n\nX_NUM_RS == 3"
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reqt_doc: ./custom_instruction.rst
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ref_mode: page
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ref_page: ''
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ref_section: ''
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ref_viewer: firefox
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verif_goals: "Input operands:\n\nif (X_NUS_RS == 3)\nrs1 value is +ve, -ve\
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\ and zero\nrs2 value is +ve, -ve and zero\nrs3 value is +ve, -ve and zero\n\
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||||
All combinations of rs1, rs2 and rs3 +ve, -ve, and zero values are used\n\
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All bits of rs1 are toggled\nAll bits of rs2 are toggled\nAll bits of rs3\
|
||||
\ are toggled\n\nelse if (X_NUM_RS != 3)\nillegal exception raised on the\
|
||||
\ CPU"
|
||||
pfc: -1
|
||||
test_type: -1
|
||||
cov_method: -1
|
||||
cores: -1
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||||
coverage_loc: ''
|
||||
comments: ''
|
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- '002': !VerifItem
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name: '002'
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tag: VP_CVXIF_F003_S007_I002
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description: "cus_add_rs3 rd, rs1, rs2, rs3\nrd = rs1 + rs2 + rs3\ncus_add_rs3\
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\ works in all privilege modes\n\nX_NUM_RS == 3"
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reqt_doc: ./custom_instruction.rst
|
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ref_mode: page
|
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ref_page: ''
|
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ref_section: ''
|
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ref_viewer: firefox
|
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verif_goals: "Output operands:\n\nif (X_NUM_RS == 3)\nrd value is +ve, -ve\
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\ and zero\nAll bits of rd are toggled\n\nelse if (X_NUM_RS != 3)\nillegal\
|
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\ exception raised on the CPU"
|
||||
pfc: -1
|
||||
test_type: -1
|
||||
cov_method: -1
|
||||
cores: 56
|
||||
coverage_loc: ''
|
||||
comments: ''
|
||||
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
|
||||
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
|
||||
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
|
||||
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'
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||||
100
cva6/docs/VerifPlans/CVXIF/custom_instruction.rst
Normal file
100
cva6/docs/VerifPlans/CVXIF/custom_instruction.rst
Normal file
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@ -0,0 +1,100 @@
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..
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||||
Copyright (c) 2023 OpenHW Group
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||||
|
||||
Copyright (c) 2023 Thales DIS SAS
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||||
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SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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||||
|
||||
..
|
||||
|
||||
Custom Instruction to challenge CV-X-IF protocol
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
This section describes some custom instruction, for stress or challenge the CV-X-IF protocol for the 3 implemented interfaces, it's just to interact with the cvxif agent.
|
||||
All instructions use opcode `CUSTOM_3`(0x7b, 0b111_1011).
|
||||
|
||||
- **CUS_ADD**: Custom Add
|
||||
|
||||
**Format**: cus_add rd, rs1, rs2 -> |0000000|rs2|rs1|001|rd|111_1011|
|
||||
|
||||
**Description**: add register rs1 to rs2, and store the result in rd (works for all privilege modes).
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] + x[rs2]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: Illegal instruction exception is raised if rs_valid != 2'b11 && rs_valid != 3'b111.
|
||||
|
||||
- **CUS_NOP**: Custom No Operation
|
||||
|
||||
**Format**: cus_nop -> |0000000000000000000000000|111_1011|
|
||||
|
||||
**Description**: do nothing, it's just a hint instruction.
|
||||
|
||||
**Pseudocode**: cus_nop
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **CUS_ADD_RS3**: Custom Add
|
||||
|
||||
**Format**: cus_add_rs3 rd, rs1, rs2, rs3 -> |rs3|01|rs2|rs1|000|rd|111_1011|
|
||||
|
||||
**Description**: add register rs1 to rs2 then the result to rs3, and store the result in register rd (works for all privilege modes).
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] + x[rs2] + x[rs3]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: Illegal instruction exception is raised if rs_valid != 3'b111.
|
||||
|
||||
- **CUS_S_ADD**: Custom Supervisor Add
|
||||
|
||||
**Format**: add rd, rs1, rs2 -> |0000110|rs2|rs1|000|rd|111_1011|
|
||||
|
||||
**Description**: add register rs1 to rs2, and store the result in register rd (works only in Supervisor mode).
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] + x[rs2]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: Illegal instruction exception is raised if the privilege mode isn't Supervisor mode, or rs_valid != 2'b11 && rs_valid != 3'b111.
|
||||
|
||||
- **CUS_U_ADD**: Custom User Add
|
||||
|
||||
**Format**: add rd, rs1, rs2 -> |0000010|rs2|rs1|000|rd|111_1011|
|
||||
|
||||
**Description**: add register rs1 to rs2, and store the result in register rd (works only in User mode).
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] + x[rs2]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: Illegal instruction exception is raised if the privilege mode isn't User mode, or rs_valid != 2'b11 && rs_valid != 3'b111.
|
||||
|
||||
- **CUS_ADD_MULTI**: Custom Multicycle Add
|
||||
|
||||
**Format**: addi rd, rs1, rs2 -> |0001000|rs2|rs1|000|rd|111_1011|
|
||||
|
||||
**Description**: add register rs1 to rs2, and store the result in rd (works for all privilege mode).
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] + x[rs2]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: Illegal instruction exception is raised if rs_valid != 2'b11 && rs_valid != 3'b111.
|
||||
|
||||
- **CUS_EXC**: Custom Exception
|
||||
|
||||
**Format**: cus_exc imm[5:0] -> |1100000|000000000001|imm|111_1011|
|
||||
|
||||
**Description**: raise an exception.
|
||||
|
||||
**Pseudocode**: mcause[5:0] = imm[5:0]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: raise an exception based on the value on the immediate field.
|
||||
|
||||
When a CV-X-IF exception is raised, mcause[5:0] of the corresponding CORE-V hart is assumed set to exccode[5:0] of CV-X-IF.
|
||||
|
|
@ -558,3 +558,517 @@
|
|||
|
||||
*(none)*
|
||||
|
||||
## Feature: Custom Instructions
|
||||
|
||||
### Sub-feature: 000_CUS_ADD
|
||||
|
||||
#### Item: 000
|
||||
|
||||
* **Requirement location:** ./custom_instruction.rst
|
||||
* **Feature Description**
|
||||
|
||||
cus_add rd, rs1, rs2
|
||||
rd = rs1 + rs2
|
||||
cus_add works in all privilege modes
|
||||
* **Verification Goals**
|
||||
|
||||
Register operands:
|
||||
|
||||
All possible rs1 registers are used.
|
||||
All possible rs2 registers are used.
|
||||
All possible rd registers are used.
|
||||
All possible register combinations where rs1 == rd are used
|
||||
All possible register combinations where rs2 == rd are used
|
||||
* **Pass/Fail Criteria:** Check RM
|
||||
* **Test Type:** Constrained Random
|
||||
* **Coverage Method:** Functional Coverage
|
||||
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
|
||||
* **Unique verification tag:** VP_CVXIF_F003_S000_I000
|
||||
* **Link to Coverage:**
|
||||
* **Comments**
|
||||
|
||||
*(none)*
|
||||
|
||||
#### Item: 001
|
||||
|
||||
* **Requirement location:** ./custom_instruction.rst
|
||||
* **Feature Description**
|
||||
|
||||
cus_add rd, rs1, rs2
|
||||
rd = rs1 + rs2
|
||||
cus_add works in all privilege modes
|
||||
* **Verification Goals**
|
||||
|
||||
Input operands:
|
||||
|
||||
rs1 value is +ve, -ve and zero
|
||||
rs2 value is +ve, -ve and zero
|
||||
All combinations of rs1 and rs2 +ve, -ve, and zero values are used
|
||||
All bits of rs1 are toggled
|
||||
All bits of rs2 are toggled
|
||||
* **Pass/Fail Criteria:** NDY (Not Defined Yet)
|
||||
* **Test Type:** NDY (Not Defined Yet)
|
||||
* **Coverage Method:** NDY (Not Defined Yet)
|
||||
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
|
||||
* **Unique verification tag:** VP_CVXIF_F003_S000_I001
|
||||
* **Link to Coverage:**
|
||||
* **Comments**
|
||||
|
||||
*(none)*
|
||||
|
||||
#### Item: 002
|
||||
|
||||
* **Requirement location:** ./custom_instruction.rst
|
||||
* **Feature Description**
|
||||
|
||||
cus_add rd, rs1, rs2
|
||||
rd = rs1 + rs2
|
||||
cus_add works in all privilege modes
|
||||
* **Verification Goals**
|
||||
|
||||
Output result:
|
||||
|
||||
rd value is +ve, -ve and zero
|
||||
All bits of rd are toggled
|
||||
* **Pass/Fail Criteria:** NDY (Not Defined Yet)
|
||||
* **Test Type:** NDY (Not Defined Yet)
|
||||
* **Coverage Method:** NDY (Not Defined Yet)
|
||||
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
|
||||
* **Unique verification tag:** VP_CVXIF_F003_S000_I002
|
||||
* **Link to Coverage:**
|
||||
* **Comments**
|
||||
|
||||
*(none)*
|
||||
|
||||
### Sub-feature: 001_CUS_NOP
|
||||
|
||||
#### Item: 000
|
||||
|
||||
* **Requirement location:** ./custom_instruction.rst
|
||||
* **Feature Description**
|
||||
|
||||
No operation Instruction
|
||||
* **Verification Goals**
|
||||
|
||||
Instruction executed
|
||||
* **Pass/Fail Criteria:** Check RM
|
||||
* **Test Type:** Constrained Random
|
||||
* **Coverage Method:** Functional Coverage
|
||||
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
|
||||
* **Unique verification tag:** VP_CVXIF_F003_S001_I000
|
||||
* **Link to Coverage:**
|
||||
* **Comments**
|
||||
|
||||
*(none)*
|
||||
|
||||
### Sub-feature: 003_CUS_S_ADD
|
||||
|
||||
#### Item: 000
|
||||
|
||||
* **Requirement location:** ./custom_instruction.rst
|
||||
* **Feature Description**
|
||||
|
||||
cus_s_add rd, rs1, rs2
|
||||
rd = rs1 + rs2
|
||||
cus_s_add works in supervisor privilege mode
|
||||
* **Verification Goals**
|
||||
|
||||
Register operands:
|
||||
|
||||
if (mode == s)
|
||||
All possible rs1 registers are used.
|
||||
All possible rs2 registers are used.
|
||||
All possible rd registers are used.
|
||||
All possible register combinations where rs1 == rd are used
|
||||
All possible register combinations where rs2 == rd are used
|
||||
|
||||
else if (mode != s)
|
||||
illegal exception raised on hte CPU
|
||||
* **Pass/Fail Criteria:** Check RM
|
||||
* **Test Type:** Constrained Random
|
||||
* **Coverage Method:** Functional Coverage
|
||||
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
|
||||
* **Unique verification tag:** VP_CVXIF_F003_S003_I000
|
||||
* **Link to Coverage:**
|
||||
* **Comments**
|
||||
|
||||
*(none)*
|
||||
|
||||
#### Item: 001
|
||||
|
||||
* **Requirement location:** ./custom_instruction.rst
|
||||
* **Feature Description**
|
||||
|
||||
cus_s_add rd, rs1, rs2
|
||||
rd = rs1 + rs2
|
||||
cus_s_add works in supervisor privilege mode
|
||||
* **Verification Goals**
|
||||
|
||||
Input operands:
|
||||
|
||||
if (mode == s)
|
||||
rs1 value is +ve, -ve and zero
|
||||
rs2 value is +ve, -ve and zero
|
||||
All combinations of rs1 and rs2 +ve, -ve, and zero values are used
|
||||
All bits of rs1 are toggled
|
||||
All bits of rs2 are toggled
|
||||
|
||||
else if (mode != s)
|
||||
illegal exception raised on the CPU
|
||||
* **Pass/Fail Criteria:** NDY (Not Defined Yet)
|
||||
* **Test Type:** NDY (Not Defined Yet)
|
||||
* **Coverage Method:** NDY (Not Defined Yet)
|
||||
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
|
||||
* **Unique verification tag:** VP_CVXIF_F003_S003_I001
|
||||
* **Link to Coverage:**
|
||||
* **Comments**
|
||||
|
||||
*(none)*
|
||||
|
||||
#### Item: 002
|
||||
|
||||
* **Requirement location:** ./custom_instruction.rst
|
||||
* **Feature Description**
|
||||
|
||||
cus_s_add rd, rs1, rs2
|
||||
rd = rs1 + rs2
|
||||
cus_s_add works in supervisor privilege mode
|
||||
* **Verification Goals**
|
||||
|
||||
Output operands:
|
||||
|
||||
if (mode == s)
|
||||
rd value is +ve, -ve and zero
|
||||
All bits of rd are toggled
|
||||
|
||||
else if (mode != s)
|
||||
illegal exception raised on the CPU
|
||||
* **Pass/Fail Criteria:** NDY (Not Defined Yet)
|
||||
* **Test Type:** NDY (Not Defined Yet)
|
||||
* **Coverage Method:** NDY (Not Defined Yet)
|
||||
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
|
||||
* **Unique verification tag:** VP_CVXIF_F003_S003_I002
|
||||
* **Link to Coverage:**
|
||||
* **Comments**
|
||||
|
||||
*(none)*
|
||||
|
||||
### Sub-feature: 004_CUS_U_ADD
|
||||
|
||||
#### Item: 000
|
||||
|
||||
* **Requirement location:** ./custom_instruction.rst
|
||||
* **Feature Description**
|
||||
|
||||
cus_u_add rd, rs1, rs2
|
||||
rd = rs1 + rs2
|
||||
cus_u_add works in User privilege mode
|
||||
* **Verification Goals**
|
||||
|
||||
Register operands:
|
||||
|
||||
if (mode == u)
|
||||
All possible rs1 registers are used.
|
||||
All possible rs2 registers are used.
|
||||
All possible rd registers are used.
|
||||
All possible register combinations where rs1 == rd are used
|
||||
All possible register combinations where rs2 == rd are used
|
||||
|
||||
else if (mode != u)
|
||||
illegal exception raised on hte CPU
|
||||
* **Pass/Fail Criteria:** Check RM
|
||||
* **Test Type:** Constrained Random
|
||||
* **Coverage Method:** Functional Coverage
|
||||
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
|
||||
* **Unique verification tag:** VP_CVXIF_F003_S004_I000
|
||||
* **Link to Coverage:**
|
||||
* **Comments**
|
||||
|
||||
*(none)*
|
||||
|
||||
#### Item: 001
|
||||
|
||||
* **Requirement location:** ./custom_instruction.rst
|
||||
* **Feature Description**
|
||||
|
||||
cus_u_add rd, rs1, rs2
|
||||
rd = rs1 + rs2
|
||||
cus_u_add works in User privilege mode
|
||||
* **Verification Goals**
|
||||
|
||||
Input operands:
|
||||
|
||||
if (mode == u)
|
||||
rs1 value is +ve, -ve and zero
|
||||
rs2 value is +ve, -ve and zero
|
||||
All combinations of rs1 and rs2 +ve, -ve, and zero values are used
|
||||
All bits of rs1 are toggled
|
||||
All bits of rs2 are toggled
|
||||
|
||||
else if (mode != u)
|
||||
illegal exception raised on the CPU
|
||||
* **Pass/Fail Criteria:** NDY (Not Defined Yet)
|
||||
* **Test Type:** NDY (Not Defined Yet)
|
||||
* **Coverage Method:** NDY (Not Defined Yet)
|
||||
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
|
||||
* **Unique verification tag:** VP_CVXIF_F003_S004_I001
|
||||
* **Link to Coverage:**
|
||||
* **Comments**
|
||||
|
||||
*(none)*
|
||||
|
||||
#### Item: 002
|
||||
|
||||
* **Requirement location:** ./custom_instruction.rst
|
||||
* **Feature Description**
|
||||
|
||||
cus_u_add rd, rs1, rs2
|
||||
rd = rs1 + rs2
|
||||
cus_u_add works in User privilege mode
|
||||
* **Verification Goals**
|
||||
|
||||
Output operands:
|
||||
|
||||
if (mode == u)
|
||||
rd value is +ve, -ve and zero
|
||||
All bits of rd are toggled
|
||||
|
||||
else if (mode != u)
|
||||
illegal exception raised on the CPU
|
||||
* **Pass/Fail Criteria:** NDY (Not Defined Yet)
|
||||
* **Test Type:** NDY (Not Defined Yet)
|
||||
* **Coverage Method:** NDY (Not Defined Yet)
|
||||
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
|
||||
* **Unique verification tag:** VP_CVXIF_F003_S004_I002
|
||||
* **Link to Coverage:**
|
||||
* **Comments**
|
||||
|
||||
*(none)*
|
||||
|
||||
### Sub-feature: 005_CUS_ADD_MULTI
|
||||
|
||||
#### Item: 000
|
||||
|
||||
* **Requirement location:** ./custom_instruction.rst
|
||||
* **Feature Description**
|
||||
|
||||
cus_add_multi rd, rs1, rs2
|
||||
rd = rs1 + rs2
|
||||
cus_add_multi works in all privilege modes
|
||||
* **Verification Goals**
|
||||
|
||||
Register operands:
|
||||
|
||||
All possible rs1 registers are used.
|
||||
All possible rs2 registers are used.
|
||||
All possible rd registers are used.
|
||||
All possible register combinations where rs1 == rd are used
|
||||
All possible register combinations where rs2 == rd are used
|
||||
* **Pass/Fail Criteria:** Check RM
|
||||
* **Test Type:** Constrained Random
|
||||
* **Coverage Method:** Functional Coverage
|
||||
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
|
||||
* **Unique verification tag:** VP_CVXIF_F003_S005_I000
|
||||
* **Link to Coverage:**
|
||||
* **Comments**
|
||||
|
||||
*(none)*
|
||||
|
||||
#### Item: 001
|
||||
|
||||
* **Requirement location:** ./custom_instruction.rst
|
||||
* **Feature Description**
|
||||
|
||||
cus_add_multi rd, rs1, rs2
|
||||
rd = rs1 + rs2
|
||||
cus_add_multi works in all privilege modes
|
||||
* **Verification Goals**
|
||||
|
||||
Input operands:
|
||||
|
||||
rs1 value is +ve, -ve and zero
|
||||
rs2 value is +ve, -ve and zero
|
||||
All combinations of rs1 and rs2 +ve, -ve, and zero values are used
|
||||
All bits of rs1 are toggled
|
||||
All bits of rs2 are toggled
|
||||
* **Pass/Fail Criteria:** NDY (Not Defined Yet)
|
||||
* **Test Type:** NDY (Not Defined Yet)
|
||||
* **Coverage Method:** NDY (Not Defined Yet)
|
||||
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
|
||||
* **Unique verification tag:** VP_CVXIF_F003_S005_I001
|
||||
* **Link to Coverage:**
|
||||
* **Comments**
|
||||
|
||||
*(none)*
|
||||
|
||||
#### Item: 002
|
||||
|
||||
* **Requirement location:** ./custom_instruction.rst
|
||||
* **Feature Description**
|
||||
|
||||
cus_add_multi rd, rs1, rs2
|
||||
rd = rs1 + rs2
|
||||
cus_add_multi works in all privilege modes
|
||||
* **Verification Goals**
|
||||
|
||||
Output result:
|
||||
|
||||
rd value is +ve, -ve and zero
|
||||
All bits of rd are toggled
|
||||
* **Pass/Fail Criteria:** NDY (Not Defined Yet)
|
||||
* **Test Type:** NDY (Not Defined Yet)
|
||||
* **Coverage Method:** NDY (Not Defined Yet)
|
||||
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
|
||||
* **Unique verification tag:** VP_CVXIF_F003_S005_I002
|
||||
* **Link to Coverage:**
|
||||
* **Comments**
|
||||
|
||||
*(none)*
|
||||
|
||||
#### Item: 003
|
||||
|
||||
* **Requirement location:** ./custom_instruction.rst
|
||||
* **Feature Description**
|
||||
|
||||
cus_add_multi rd, rs1, rs2
|
||||
rd = rs1 + rs2
|
||||
cus_add_multi works in all privilege modes
|
||||
* **Verification Goals**
|
||||
|
||||
Check all delays from min to max
|
||||
* **Pass/Fail Criteria:** Check RM
|
||||
* **Test Type:** Constrained Random
|
||||
* **Coverage Method:** Functional Coverage
|
||||
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
|
||||
* **Unique verification tag:** VP_CVXIF_F003_S005_I003
|
||||
* **Link to Coverage:**
|
||||
* **Comments**
|
||||
|
||||
*(none)*
|
||||
|
||||
### Sub-feature: 006_CUS_EXC
|
||||
|
||||
#### Item: 000
|
||||
|
||||
* **Requirement location:** ./custom_instruction.rst
|
||||
* **Feature Description**
|
||||
|
||||
cus_exc imm[5:0]
|
||||
mcause[5:0] = imm[5:0]
|
||||
cus_exc raise an exception on the CPU base on the imm value
|
||||
* **Verification Goals**
|
||||
|
||||
Check all possible imm value
|
||||
* **Pass/Fail Criteria:** NDY (Not Defined Yet)
|
||||
* **Test Type:** NDY (Not Defined Yet)
|
||||
* **Coverage Method:** NDY (Not Defined Yet)
|
||||
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
|
||||
* **Unique verification tag:** VP_CVXIF_F003_S006_I000
|
||||
* **Link to Coverage:**
|
||||
* **Comments**
|
||||
|
||||
*(none)*
|
||||
|
||||
### Sub-feature: 007_CUS_ADD_RS3
|
||||
|
||||
#### Item: 000
|
||||
|
||||
* **Requirement location:** ./custom_instruction.rst
|
||||
* **Feature Description**
|
||||
|
||||
cus_add_rs3 rd, rs1, rs2, rs3
|
||||
rd = rs1 + rs2 + rs3
|
||||
cus_add_rs3 works in all privilege modes
|
||||
|
||||
X_NUM_RS == 3
|
||||
* **Verification Goals**
|
||||
|
||||
Register operands:
|
||||
|
||||
if (X_NUM_RS == 3)
|
||||
All possible rs1 registers are used.
|
||||
All possible rs2 registers are used.
|
||||
All possible rs3 registers are used.
|
||||
All possible rd registers are used.
|
||||
All possible register combinations where rs1 == rd are used
|
||||
All possible register combinations where rs2 == rd are used
|
||||
All possible register combinations where rs3 == rd are used
|
||||
|
||||
|
||||
else if (X_NUM_RS != 3)
|
||||
illegal exception raised on the CPU
|
||||
* **Pass/Fail Criteria:** Check RM
|
||||
* **Test Type:** Constrained Random
|
||||
* **Coverage Method:** Functional Coverage
|
||||
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
|
||||
* **Unique verification tag:** VP_CVXIF_F003_S007_I000
|
||||
* **Link to Coverage:**
|
||||
* **Comments**
|
||||
|
||||
*(none)*
|
||||
|
||||
#### Item: 001
|
||||
|
||||
* **Requirement location:** ./custom_instruction.rst
|
||||
* **Feature Description**
|
||||
|
||||
cus_add_rs3 rd, rs1, rs2, rs3
|
||||
rd = rs1 + rs2 + rs3
|
||||
cus_add_rs3 works in all privilege modes
|
||||
|
||||
X_NUM_RS == 3
|
||||
* **Verification Goals**
|
||||
|
||||
Input operands:
|
||||
|
||||
if (X_NUS_RS == 3)
|
||||
rs1 value is +ve, -ve and zero
|
||||
rs2 value is +ve, -ve and zero
|
||||
rs3 value is +ve, -ve and zero
|
||||
All combinations of rs1, rs2 and rs3 +ve, -ve, and zero values are used
|
||||
All bits of rs1 are toggled
|
||||
All bits of rs2 are toggled
|
||||
All bits of rs3 are toggled
|
||||
|
||||
else if (X_NUM_RS != 3)
|
||||
illegal exception raised on the CPU
|
||||
* **Pass/Fail Criteria:** NDY (Not Defined Yet)
|
||||
* **Test Type:** NDY (Not Defined Yet)
|
||||
* **Coverage Method:** NDY (Not Defined Yet)
|
||||
* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
|
||||
* **Unique verification tag:** VP_CVXIF_F003_S007_I001
|
||||
* **Link to Coverage:**
|
||||
* **Comments**
|
||||
|
||||
*(none)*
|
||||
|
||||
#### Item: 002
|
||||
|
||||
* **Requirement location:** ./custom_instruction.rst
|
||||
* **Feature Description**
|
||||
|
||||
cus_add_rs3 rd, rs1, rs2, rs3
|
||||
rd = rs1 + rs2 + rs3
|
||||
cus_add_rs3 works in all privilege modes
|
||||
|
||||
X_NUM_RS == 3
|
||||
* **Verification Goals**
|
||||
|
||||
Output operands:
|
||||
|
||||
if (X_NUM_RS == 3)
|
||||
rd value is +ve, -ve and zero
|
||||
All bits of rd are toggled
|
||||
|
||||
else if (X_NUM_RS != 3)
|
||||
illegal exception raised on the CPU
|
||||
* **Pass/Fail Criteria:** NDY (Not Defined Yet)
|
||||
* **Test Type:** NDY (Not Defined Yet)
|
||||
* **Coverage Method:** NDY (Not Defined Yet)
|
||||
* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
|
||||
* **Unique verification tag:** VP_CVXIF_F003_S007_I002
|
||||
* **Link to Coverage:**
|
||||
* **Comments**
|
||||
|
||||
*(none)*
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue