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Design Spec initial commit: description of introduction, system and frontend (#949)

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JeanRochCoulon 2022-09-05 23:40:15 +02:00 • committed by GitHub
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#
# Copyright (c) 2020 OpenHW Group
#
# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# https://solderpad.org/licenses/
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
#
###############################################################################
#
# Minimal makefile for Sphinx documentation
#
# You can set these variables from the command line.
SPHINXOPTS =
SPHINXBUILD = sphinx-build
SOURCEDIR = source
BUILDDIR = build
# Put it first so that "make" without argument is like "make help".
help:
@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
.PHONY: help Makefile
# Catch-all target: route all unknown targets to Sphinx using the new
# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
%: Makefile
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)

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@ECHO OFF
pushd %~dp0
REM Command file for Sphinx documentation
if "%SPHINXBUILD%" == "" (
set SPHINXBUILD=sphinx-build
)
set SOURCEDIR=source
set BUILDDIR=build
if "%1" == "" goto help
%SPHINXBUILD% >NUL 2>NUL
if errorlevel 9009 (
echo.
echo.The 'sphinx-build' command was not found. Make sure you have Sphinx
echo.installed, then set the SPHINXBUILD environment variable to point
echo.to the full path of the 'sphinx-build' executable. Alternatively you
echo.may add the Sphinx directory to PATH.
echo.
echo.If you don't have Sphinx installed, grab it from
echo.http://sphinx-doc.org/
exit /b 1
)
%SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS%
goto end
:help
%SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS%
:end
popd

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sphinx
sphinx-rtd-theme
recommonmark
sphinxcontrib-svg2pdfconverter
sphinx_github_changelog

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# -*- coding: utf-8 -*-
#
# Copyright (c) 2020 OpenHW Group
#
# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# https://solderpad.org/licenses/
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
#
###############################################################################
#
# Configuration file for the Sphinx documentation builder.
#
# This file does only contain a selection of the most common options. For a
# full list see the documentation:
# http://www.sphinx-doc.org/en/master/config
# -- Path setup --------------------------------------------------------------
# If extensions (or modules to document with autodoc) are in another directory,
# add these directories to sys.path here. If the directory is relative to the
# documentation root, use os.path.abspath to make it absolute, like shown here.
#
# import os
# import sys
# sys.path.insert(0, os.path.abspath('.'))
# -- Project information -----------------------------------------------------
project = u'CORE-V CV32A6-step1 Design Specification'
copyright = u'2022, Thales Group'
author = u'Thales and OpenHW Group'
# The short X.Y version
version = u''
# The full version, including alpha/beta/rc tags
release = u''
# -- General configuration ---------------------------------------------------
# If your documentation needs a minimal Sphinx version, state it here.
#
# needs_sphinx = '1.0'
# Add any Sphinx extension module names here, as strings. They can be
# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
# ones.
extensions = [
'sphinx.ext.autodoc',
'sphinx.ext.todo',
'recommonmark',
'sphinxcontrib.inkscapeconverter',
'sphinx_github_changelog',
# 'sphinxcontrib.wavedrom',
]
#wavedrom_html_jsinline = False
# Add any paths that contain templates here, relative to this directory.
templates_path = ['ytemplates']
# The suffix(es) of source filenames.
# You can specify multiple suffix as a list of string:
#
# source_suffix = ['.rst', '.md']
source_suffix = '.rst'
# The master toctree document.
master_doc = 'index'
# The language for content autogenerated by Sphinx. Refer to documentation
# for a list of supported languages.
#
# This is also used if you do content translation via gettext catalogs.
# Usually you set "language" from the command line for these cases.
language = 'en'
# List of patterns, relative to source directory, that match files and
# directories to ignore when looking for source files.
# This pattern also affects html_static_path and html_extra_path.
exclude_patterns = []
# Numbering
numfig=True
numfig_format = {'figure': 'Figure %s', 'table': 'Table %s', 'code-block': 'Listing %s'}
# The name of the Pygments (syntax highlighting) style to use.
pygments_style = None
# -- Options for HTML output -------------------------------------------------
# The theme to use for HTML and HTML Help pages. See the documentation for
# a list of builtin themes.
#
#html_theme = 'alabaster'
html_theme = 'sphinx_rtd_theme'
# Theme options are theme-specific and customize the look and feel of a theme
# further. For a list of options available for each theme, see the
# documentation.
#
html_theme_options = {'style_nav_header_background': '#DDDDDD'}
html_logo = '../images/openhw-landscape.svg'
# Add any paths that contain custom static files (such as style sheets) here,
# relative to this directory. They are copied after the builtin static files,
# so a file named "default.css" will overwrite the builtin "default.css".
#html_static_path = ['ystatic']
# Set html_static_path to null on the advice of RTDs:
html_static_path = []
# Custom sidebar templates, must be a dictionary that maps document names
# to template names.
#
# The default sidebars (for documents that don't match any pattern) are
# defined by theme itself. Builtin themes are using these templates by
# default: ``['localtoc.html', 'relations.html', 'sourcelink.html',
# 'searchbox.html']``.
#
# html_sidebars = {}
# -- Options for HTMLHelp output ---------------------------------------------
# Output file base name for HTML help builder.
htmlhelp_basename = 'CORE-V_CV32A6-step1_DESIGN_SPEC'
# -- Options for LaTeX output ------------------------------------------------
latex_elements = {
# The paper size ('letterpaper' or 'a4paper').
#
# 'papersize': 'letterpaper',
# The font size ('10pt', '11pt' or '12pt').
#
# 'pointsize': '10pt',
# Additional stuff for the LaTeX preamble.
#
# 'preamble': '',
# Latex figure (float) alignment
#
# 'figure_align': 'htbp',
}
# Grouping the document tree into LaTeX files. List of tuples
# (source start file, target name, title,
# author, documentclass [howto, manual, or own class]).
latex_documents = [
(master_doc, 'CV32A6-step1_Design_Spec.tex', u'CORE-V-Docs Documentation',
u'Jean-Roch Coulon', 'manual'),
]
# -- Options for manual page output ------------------------------------------
# One entry per manual page. List of tuples
# (source start file, name, description, authors, manual section).
man_pages = [
(master_doc, 'CV32A6-step1_Design_Spec.tex', u'CORE-V-Docs Documentation',
[author], 1)
]
# -- Options for Texinfo output ----------------------------------------------
# Grouping the document tree into Texinfo files. List of tuples
# (source start file, target name, title, author,
# dir menu entry, description, category)
texinfo_documents = [
(master_doc, 'CV32A6-step1_Design_Spec.tex', u'CORE-V-Docs Documentation',
author, 'UserManual', 'User Manual for CV32A6-step1 CORE-V processor core.',
'Miscellaneous'),
]
# -- Options for Epub output -------------------------------------------------
# Bibliographic Dublin Core info.
epub_title = project
# The unique identifier of the text. This can be a ISBN number
# or the project homepage.
#
# epub_identifier = ''
# A unique identification for the text.
#
# epub_uid = ''
# A list of files that should not be packed into the epub file.
epub_exclude_files = ['search.html']
# -- Extension configuration -------------------------------------------------
# -- Options for todo extension ----------------------------------------------
# If true, `todo` and `todoList` produce output, else they produce nothing.
todo_include_todos = True

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..
Copyright 2021 Thales DIS design services SAS
Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
.. _CVA6_FRONTEND:
FRONTEND Sub-System
===================
Description
-----------
The FRONTEND sub-system implements two first stages of the cva6 pipeline, PC gen and Fetch stages.
PC gen stage is responsible for generating the next program counter hosting a Branch Target Buffer (BTB) a Branch History Table (BHT) and a Return Address Stack (RAS) to speculate on the branch target address.
Fetch stage requests data to the CACHE sub-system, realigns the data to store them in instruction queue and transmits the instructions to the DECODE sub-system. FRONTEND can fetch up to 2 instructions per cycles when C extension instructions is used, but as instruction queue limits the data rate, up to one instruction per cycle can be sent to DECODE.
The system is connected to:
* CACHES Sub-System provides fethed instructions to FRONTEND.
* DECODE Sub-System receives instructions from FRONTEND.
* CONTROLLER Sub-System can flush FRONTEND PC gen stage
* EXECUTE, CONTROLLER, CSR and COMMIT Sub-systems triggers PC jumping due to a branch mispredict, an exception, a return from exception, a debug entry or pipeline flush. They provides related PC next value.
* CSR Sub-system states about debug mode.
.. list-table:: FRONTEND interface signals
:header-rows: 1
* - Signal
- IO
- connection
- Type
- Description
* - ``clk_i``
- in
- SYSTEM
- logic
- System Clock
* - ``rst_ni``
- in
- SYSTEM
- logic
- Asynchronous reset active low
* - ``debug_mode_i``
- in
- CSR
- logic
- Debug mode state
* - ``flush_i``
- in
- CONTROLLER
- logic
- Fetch flush request
* - ``flush_bp_i``
- in
- stuck at zero
- logic
- flush branch prediction
* - ``boot_addr_i``
- in
- SYSTEM
- logic[VLEN-1:0]
- Next PC when reset
* - ``resolved_branch_i``
- in
- EXECUTE
- bp_resolve_t
- mispredict event and next PC
* - ``eret_i``
- in
- CSR
- logic
- Return from exception event
* - ``epc_i``
- in
- CSR
- logic[VLEN-1:0]
- Next PC when returning from exception
* - ``ex_valid_i``
- in
- COMMIT
- logic
- Exception event
* - ``trap_vector_base_i``
- in
- CSR
- logic[VLEN-1:0]
- Next PC when jumping into exception
* - ``set_pc_commit_i``
- in
- CONTROLLER
- logic
- Set the PC coming from COMMIT as next PC
* - ``pc_commit_i``
- in
- COMMIT
- logic[VLEN-1:0]
- Next PC when flushing pipeline
* - ``set_debug_pc_i``
- in
- CSR
- logic
- Debug event
* - ``icache_dreq_o``
- out
- CACHES
- icache_dreq_i_t
- Handshake between CACHE and FRONTEND (fetch)
* - ``icache_dreq_i``
- in
- CACHES
- icache_dreq_o_t
- Handshake between CACHE and FRONTEND (fetch)
* - ``fetch_entry_o``
- out
- DECODE
- fetch_entry_t
- Handshake's data between FRONTEND (fetch) and DECODE
* - ``fetch_entry_valid_o``
- out
- DECODE
- logic
- Handshake's valid between FRONTEND (fetch) and DECODE
* - ``fetch_entry_ready_i``
- in
- DECODE
- logic
- Handshake's ready between FRONTEND (fetch) and DECODE
Functionality
-------------
PC Generation stage
~~~~~~~~~~~~~~~~~~~
PC gen generates the next program counter. The next PC can originate from the following sources (listed in order of precedence):
* **Reset state:** At reset, the PC is assigned to the boot address.
* **Branch Predict:** Fetched instruction is predecoded thanks to instr_scan module. When instruction is a control flow, three cases need to be considered:
+ 1) If instruction is a JALR and BTB (Branch Target Buffer) returns a valid address, next PC is predicted by BTB. Else JALR is not considered as a control flow instruction, which will generate a mispredict.
+ 2) If instruction is a branch and BTH (Branch History table) returns a valid address, next PC is predicted by BHT. Else branch is not considered as an control flow instruction, which will generate a mispredict when branch is taken.
+ 3) If instruction is a RET and RAS (Return Address Stack) returns a valid address and RET has already been consummed by instruction queue. Else RET is considered as a control flow instruction but next PC is not predicted. A mispredict wil be generated.
Then the PC gen informs the Fetch stage that it performed a prediction on the PC. *In CV32A6-step1, Branch Prediction is simplified: no information is stored in BTB, BHT and RAS. JALR, branch and RET instructions are not considered as control flow instruction and will generates mispredict.*
* **Default:** PC + 4 is fetched. PC Gen always fetches on a word boundary (32-bit). Compressed instructions are handled by fetch stage.
* **Mispredict:** When a branch prediction is mispredicted, the EXECUTE feedbacks a misprediction. This can either be a 'real' mis-prediction or a branch which was not recognized as one. In any case we need to correct our action and start fetching from the correct address.
* **Replay instruction fetch:** When the instruction queue is full, the instr_queue module asks the fetch replay and provides the address to be replayed.
* **Return from environment call:** When CSR asks a return from an environment call, the PC is assigned to the successive PC to the one stored in the CSR [m-s]epc register.
* **Exception/Interrupt:** If an exception (or interrupt, which is in the context of RISC-V systems quite similar) is triggered by the COMMIT, the next PC Gen is assigned to the CSR trap vector base address. The trap vector base address can be different depending on whether the exception traps to S-Mode or M-Mode (user mode exceptions are currently not supported). It is the purpose of the CSR Unit to figure out where to trap to and present the correct address to PC Gen.
* **Pipeline Flush:** When a CSR with side-effects gets written the whole pipeline is flushed by CONTROLLER and FRONTEND starts fetching from the next instruction again in order to take the up-dated information into account (for example virtual memory base pointer changes). The PC related to the flush action is provided by the COMMIT. Moreover flush is also transmitted to the CACHES through the next fetch CACHES access and instruction queue is reset.
* **Debug:** Debug has the highest order of precedence as it can interrupt any control flow requests. It also the only source of control flow change which can actually happen simultaneously to any other of the forced control flow changes. The debug jump is requested by CSR. The address to be jumped into is HW coded. This debug feature is not supported by cv32a6-step1.
All program counters are logical addressed. If the logical to physical mapping changes a fence.vm instruction should used to flush the pipeline *and TLBs (MMU is not enabled in CV32A6-step1)*.
Fetch Stage
~~~~~~~~~~~
Fetch stage controls by handshake protocol the CACHE sub-system. Fetched data are 32-bit block with word aligned address. A granted fetch is realigned into instr_realign module to produce instructions. Then instructions are pushed into an internal instruction FIFO called instruction queue (instr_queue module). This module stores the instructions and related information which allow to identify the outstanding transactions. In the case CONTROLLER decides to flush the instruction queue, the outstanding transactions are discarded.
*The Fetch stage asks the MMU (MMU is not enabled in CV32A6-step1) to translate the requested address.*
Memory *and MMU (MMU is not enabled in CV32A6-step1)* can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults.
Architecture and Modules
------------------------
.. figure:: ../images/frontend_modules.png
:name: FRONTEND modules
:align: center
:alt:
FRONTEND modules
Instr_realign
~~~~~~~~~~~~~
.. list-table:: instr_realign interface signals
:header-rows: 1
* - Signal
- IO
- connection
- Type
- Description
* - ``clk_i``
- in
- SYSTEM
- logic
- System Clock
* - ``rst_ni``
- in
- SYSTEM
- logic
- Asynchronous reset active low
* - ``flush_i``
- in
- FRONTEND
- logic
- Instr_align Flush
* - ``valid_i``
- in
- CACHES (reg)
- logic
- 32-bit block is valid
* - ``address_i``
- in
- CACHES (reg)
- logic[VLEN-1:0]
- 32-bit block address
* - ``data_i``
- in
- CACHES (reg)
- logic[31:0]
- 32-bit block
* - ``valid_o``
- out
- FRONTEND
- logic[1:0]
- instruction is valid
* - ``addr_o``
- out
- FRONTEND
- logic[1:0][VLEN-1:0]
- Instruction address
* - ``instr_o``
- out
- instr_scan, instr_queue
- logic[1:0][31:0]
- Instruction
* - ``serving_unaligned_o``
- out
- FRONTEND
- logic
- Instruction is unaligned
The 32-bit aligned block coming from the CACHE sub-system enters the instr_realign module. This module extracts the instructions from the 32-bit blocks, up to two instructions because it is possible to fetch two instructions when C extension is used. If the instructions are not compressed, it is possible that the instruction is not aligned on the block size but rather interleaved with two cache blocks. In that case, two cache accesses are needed. The instr_realign module provides at maximum one instruction per cycle. Not complete instruction is stored in instr_realign module before being provided in the next cycles.
In case of mispredict, flush, replay or branch predict, the instr_realign is re-initialized, the internal register storing the instruction alignment state is reset.
Instr_queue
~~~~~~~~~~~
.. list-table:: instr_realign interface signals
:header-rows: 1
* - Signal
- IO
- connection
- Type
- Description
* - ``clk_i``
- in
- SYSTEM
- logic
- System Clock
* - ``rst_ni``
- in
- SYSTEM
- logic
- Asynchronous reset active low
* - ``flush_i``
- in
- CONTROLLER
- logic
- Fetch flush request
* - ``valid_i``
- in
- instr_realign
- logic[1:0]
- Instruction is valid
* - ``instr_i``
- in
- instr_realign
- logic[1:0][31:0]
- Instruction
* - ``addr_i``
- in
- instr_realign
- logic[1:0][VLEN-1:0]
- Instruction address
* - ``predict_address_i``
- in
- FRONTEND
- logic[VLEN-1:0]
- Instruction predict address
* - ``cf_type_i``
- in
- FRONTEND
- logic[1:0]
- Instruction control flow type
* - ``ready_o``
- out
- CACHES
- logic
- Handshake's ready between CACHE and FRONTEND (fetch stage)
* - ``consumed_o``
- out
- FRONTEND
- logic[1:0]
- Indicates instructions consummed, that is to say popped by DECODE
* - ``exception_i``
- in
- CACHES (reg)
- logic
- Exception
* - ``exception_addr_i``
- in
- CACHES (reg)
- logic[VLEN-1:0]
- Exception address
* - ``replay_o``
- out
- FRONTEND
- logic
- Replay instruction because one of the FIFO was already full
* - ``replay_addr_o``
- out
- FRONTEND
- logic[VLEN-1:0]
- Address at which to replay the fetch
* - ``fetch_entry_o``
- out
- DECODE
- fetch_entry_t
- Handshake's data between FRONTEND (fetch stage) and DECODE
* - ``fetch_entry_valid_o``
- out
- DECODE
- logic
- Handshake's valid between FRONTEND (fetch stage) and DECODE
* - ``fetch_entry_ready_i``
- in
- DECODE
- logic
- Handshake's ready between FRONTEND (fetch stage) and DECODE
The instr_queue receives 32bit block from CACHES to create a valid stream of instructions to be decoded (by DECODE), to be issued (by ISSUE) and executed (by EXECUTE). FRONTEND pushes in FIFO to store the instructions and related information needed in case of mispredict or exception: instructions, instruction control flow type, exception, exception address and predicted address. DECODE pops them when decode stage is ready and indicates to the FRONTEND the instruction has been consummed.
The instruction queue contains max 4 instructions.
In instruction queue, exception can only correspond to page-fault exception.
If the instruction queue is full, a replay request is sent to inform the fetch mechanism to replay the fetch.
The instruction queue can be flushed by CONTROLLER.
Instr_scan
~~~~~~~~~~
.. list-table:: instr_scan interface signals
:header-rows: 1
* - Signal
- IO
- Connection
- Type
- Description
* - ``instr_i``
- in
- instr_realign
- logic[31:0]
- Instruction to be predecoded
* - ``rvi_return_o``
- out
- FRONTEND
- logic
- Return instruction
* - ``rvi_call_o``
- out
- FRONTEND
- logic
- JAL instruction
* - ``rvi_branch_o``
- out
- FRONTEND
- logic
- Branch instruction
* - ``rvi_jalr_o``
- out
- FRONTEND
- logic
- JALR instruction
* - ``rvi_jump_o``
- out
- FRONTEND
- logic
- unconditional jump instruction
* - ``rvi_imm_o``
- out
- FRONTEND
- logic[VLEN-1:0]
- Instruction immediat
* - ``rvc_branch_o``
- out
- FRONTEND
- logic
- Branch compressed instruction
* - ``rvc_jump_o``
- out
- FRONTEND
- logic
- unconditional jump compressed instruction
* - ``rvc_jr_o``
- out
- FRONTEND
- logic
- JR compressed instruction
* - ``rvc_return_o``
- out
- FRONTEND
- logic
- Return compressed instruction
* - ``rvc_jalr_o``
- out
- FRONTEND
- logic
- JALR compressed instruction
* - ``rvc_call_o``
- out
- FRONTEND
- logic
- JAL compressed instruction
* - ``rvc_imm_o``
- out
- FRONTEND
- logic[VLEN-1:0]
- Instruction compressed immediat
The instr_scan module pre-decodes the fetched instructions, instructions could be compressed or not. The outputs are used by the branch prediction feature. The instr_scan module tells if the instruction is compressed and provides the intruction type: branch, jump, return, jalr, imm, call or others.
BHT - Branch History Table
~~~~~~~~~~~~~~~~~~~~~~~~~~
.. list-table:: BHT interface signals
:header-rows: 1
* - Signal
- IO
- Connection
- Type
- Description
* - ``clk_i``
- in
- SYSTEM
- logic
- System clock
* - ``rst_ni``
- in
- SYSTEM
- logic
- Asynchronous reset active low
* - ``flush_i``
- in
- stuck at zero
- logic
- Flush request
* - ``debug_mode_i``
- in
- CSR
- logic
- Debug mode state
* - ``vpc_i``
- in
- CACHES (reg)
- logic[VLEN-1:0]
- Virtual PC
* - ``bht_update_i``
- in
- EXECUTE
- bht_update_t
- Update btb with resolved address
* - ``bht_prediction_o``
- out
- FRONTEND
- bht_prediction_t
- Prediction from bht
When a branch instruction is resolved by the EXECUTE, the relative information is stored in the Branch History Table.
The information is stored in a 1024 entry table.
The Branch History table is a two-bit saturation counter that takes the virtual address of the current fetched instruction by the CACHE. It states whether the current branch request should be taken or not. The two bit counter is updated by the successive execution of the current instructions as shown in the following figure.
.. figure:: ../images/bht.png
:name: BHT saturation
:align: center
:alt:
BHT saturation
The BHT is not updated if processor is in debug mode.
When a branch instruction is pre-decoded by instr_scan module, the BHT informs whether the PC address is in the BHT. In this case, the BHT predicts whether the branch is taken and provides the corresponding target address.
The BTB is never flushed.
BTB - Branch Target Buffer
~~~~~~~~~~~~~~~~~~~~~~~~~~
.. list-table:: BTB interface signals
:header-rows: 1
* - Signal
- IO
- Connection
- Type
- Description
* - ``clk_i``
- in
- SYSTEM
- logic
- System clock
* - ``rst_ni``
- in
- SYSTEM
- logic
- Asynchronous reset active low
* - ``flush_i``
- in
- stuck at zero
- logic
- Flush request state
* - ``debug_mode_i``
- in
- CSR
- logic
- Debug mode
* - ``vpc_i``
- in
- CACHES (reg)
- logic
- Virtual PC
* - ``btb_update_i``
- in
- EXECUTE
- btb_update_t
- Update BTB with resolved address
* - ``btb_prediction_o``
- out
- FRONTEND
- btb_prediction_t
- BTB Prediction
When a unconditional jumps to a register (JALR instruction) is mispredicted by the EXECUTE, the relative information is stored into the BTB, that is to say the JALR PC and the target address.
The information is stored in a 8 entry table.
The BTB is not updated if processor is in debug mode.
When a branch instruction is pre-decoded by instr_scan module, the BTB informs whether the input PC address is in BTB. In this case, the BTB provides the corresponding target address.
The BTB is never flushed.
RAS - Return Address Stack
~~~~~~~~~~~~~~~~~~~~~~~~~~
.. list-table:: RAS interface signals
:header-rows: 1
* - Signal
- IO
- Connection
- Type
- Description
* - ``clk_i``
- in
- SYSTEM
- logic
- System clock
* - ``rst_ni``
- in
- SYSTEM
- logic
- Asynchronous reset active low
* - ``flush_i``
- in
- Stuck at zero
- logic
- Flush request
* - ``push_i``
- in
- FRONTEND
- logic
- Push address in RAS
* - ``pop_i``
- in
- FRONTEND
- logic
- Pop address from RAS
* - ``data_i``
- in
- FRONTEND
- logic[VLEN-1:0]
- Data to be pushed
* - ``data_o``
- out
- FRONTEND
- ras_t
- Popped data
When an unconditional jumps to a known target address (JAL instruction) is consummed by the instr_queue, the next pc after the JAL instruction and the return address are stored into a FIFO.
The RAS FIFO depth is 2.
When a branch instruction is pre-decoded by instr_scan module, the RAS informs whether the input PC address is in RAS. In this case, the RAS provides the corresponding target address.
The RAS is never flushed.

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..
Copyright (c) 2020 OpenHW Group
Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
https://solderpad.org/licenses/
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
.. _CVA6_GLOSSARY:
Glossary
========
* **VLEN**: Virtual address lengh
* **XLEN**: RISC-V processor data lengh
* **ALU**: Arithmetic/Logic Unit
* **ASIC**: Application-Specific Integrated Circuit
* **Byte**: 8-bit data item
* **CPU**: Central Processing Unit, processor
* **CSR**: Control and Status Register
* **Custom extension**: Non-Standard extension to the RISC-V base instruction set (RISC-V Instruction Set Manual, Volume I: User-Level ISA)
* **EXE**: Instruction Execute
* **FPGA**: Field Programmable Gate Array
* **FPU**: Floating Point Unit
* **Halfword**: 16-bit data item
* **Halfword aligned address**: An address is halfword aligned if it is divisible by 2
* **ID**: Instruction Decode
* **IF**: Instruction Fetch
* **ISA**: Instruction Set Architecture
* **KGE**: kilo gate equivalents (NAND2)
* **LSU**: Load Store Unit
* **M-Mode**: Machine Mode (RISC-V Instruction Set Manual, Volume II: Privileged Architecture)
* **OBI**: Open Bus Interface
* **PC**: Program Counter
* **PULP platform**: Parallel Ultra Low Power Platform (<https://pulp-platform.org>)
* **RV32C**: RISC-V Compressed (C extension)
* **RV32F**: RISC-V Floating Point (F extension)
* **SIMD**: Single Instruction/Multiple Data
* **Standard extension**: Standard extension to the RISC-V base instruction set (RISC-V Instruction Set Manual, Volume I: User-Level ISA)
* **WARL**: Write Any Values, Reads Legal Values
* **WB**: Write Back of instruction results
* **WLRL**: Write/Read Only Legal Values
* **Word**: 32-bit data item
* **Word aligned address**: An address is word aligned if it is divisible by 4
* **WPRI**: Reserved Writes Preserve Values, Reads Ignore Values

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..
Copyright 2022 Thales DIS design services SAS
Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
.. _CVA6_INTRO:
Introduction
=============
The objective of this document is to provide enough information to allow the RTL modification (by designers) and the RTL verification (by verificators). This document is not dedicated to CVA6 users looking at information to develop software like instructions or registers.
CVA6 is a 6-stage in-order and single issue processor core which implements the RISC-V instruction set. Many features in the RISC-V specification are optional, and CVA6 can be parameterized to enable or disable some of them. CVA6 can be configured as a 32- or 64-bit core (RV32 or RV64), called CV32A6 or CV64A6. This document describes the CV32A6 processor configuration which allows to connect coprocessor through CV-X-IF but without Linux support, called CV32A6-step1. It is a first step towards the verification of CV32A6.
The CVA6 architecture is illustrated in the following figure extracted from a paper written by F.Zaruba and L.Benini.
.. figure:: ../images/ariane_overview.png
:name: CVA6 Architecute
:align: center
:alt:
CVA6 Architecture
License
-------
| Copyright 2022 Thales
| Copyright 2018 ETH Zürich and University of Bologna
| SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
| Licensed under the Solderpad Hardware License v 2.1 (the “License”);
you may not use this file except in compliance with the License, or,
at your option, the Apache License version 2.0. You may obtain a copy
of the License at https://solderpad.org/licenses/SHL-2.1/.
| Unless required by applicable law or agreed to in writing, any work
distributed under the License is distributed on an “AS IS” BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
Standards Compliance
--------------------
To ease the reading, the reference to these specifications can be implicit in the requirements below. For the sake of precision, the requirements identify the versions of RISC-V extensions from these specifications.
* **[CVA6req]** “CVA6 requirement specification”, https://github.com/openhwgroup/cva6/blob/master/docs/specifications/cva6_requirement_specification.rst, HASH#767c465.
* **[RVunpriv]** “The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 20191213”, Editors Andrew Waterman and Krste Asanović, RISC-V Foundation, December 13, 2019.
* **[RVpriv]** “The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document Version 20211203”, Editors Andrew Waterman, Krste Asanović and John Hauser, RISC-V Foundation, December 4, 2021.
* **[RVdbg]** “RISC-V External Debug Support, Document Version 0.13.2”, Editors Tim Newsome and Megan Wachs, RISC-V Foundation, March 22, 2019.
* **[RVcompat]** “RISC-V Architectural Compatibility Test Framework”, https://github.com/riscv-non-isa/riscv-arch-test.
* **[AXI]** AXI Specification, https://developer.arm.com/documentation/ihi0022/hc.
* **[CV-X-IF]** Placeholder for the CV-X-IF coprocessor interface currently prepared at OpenHW Group; current version in https://docs.openhwgroup.org/projects/openhw-group-core-v-xif/.
* **[OpenPiton]** “OpenPiton Microarchitecture Specification”, Princeton University, https://parallel.princeton.edu/openpiton/docs/micro_arch.pdf.
CV32A6 is a standards-compliant 32-bit processor fully compliant with RISC-V specifications: [RVunpriv], [RVpriv] and [RVdbg] and passes [RVcompat] compatibility tests, as requested by [GEN-10] in [CVA6req].
Documentation framework
-----------------------
The framework of this document is inspired by the Common Criteria. The Common Criteria for Information Technology Security Evaluation (referred to as Common Criteria or CC) is an international standard (ISO/IEC 15408) for computer security certification.
Description of the framework:
* Processor is split into subsystem corresponding to the main modules of the design
* Subsystems can contain several modules
* Each subsystem is described in a chapter, which contains the following subchapters: “Description”, “Functionalities”, “Architecture and Modules” and "Registers" (if any)
* The subchapter “Description” describes the main features of the submodule, the interconnections between the current subsystem and the others and the inputs/outputs interface.
* The subchapter “Functionality” lists in details the subsystem functionalities. Please avoid using the RTL signal names to explain the functionalities.
* The subchapter “Architecture and Modules” provides a drawing to present the module hierarchy, then the functionalities covered by the module
* The subchapter “Registers” specifies the subsystem registers if any
Contributors
------------
| Jean-Roch Coulon
(`jean-roch.coulon@thalesgroup.com <mailto:jean-roch.coulon@thalesgroup.com>`__)
[TO BE COMPLETED]

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..
Copyright 2022 Thales DIS design services SAS
Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
.. _CVA6_SYSTEM:
CV32A6-step1 System
===================
Description
-----------
The CV32A6-step1 is a system composed of the subsystems and protocol interfaces as illustrated in the figure. The processor is a Harvard-based modern architecture. Instructions are issued in-order through the DECODE stage and executed out-of-order but committed in-order. The processor is Single issue, that means that at maximum one instruction per cycle can be issued to the EXECUTE stage.
The CV32A6 implements a 6-stage pipeline composed of PC Generation, Instruction Detch, Instruction Decode, Issue stage, Execute stage and Commit stage. At least 6 cycles are needed to execute one instruction.
.. list-table:: cv32a6-step1 interface signals
:header-rows: 1
* - Signal
- IO
- Type
- Description
* - ``clk_i``
- in
- logic
- system clock
* - ``rst_ni``
- in
- logic
- Asynchronous reset active low
* - ``boot_addr_i``
- in
- logic[VLEN-1:0]
- Reset boot address
* - ``hart_id_i``
- in
- logic[XLEN-1:0]
- Hart id in a multicore environment (reflected in a CSR)
* - ``irq_i``
- in
- logic[1:0]
- Level sensitive IR lines, mip & sip (async)
* - ``ipi_i``
- in
- logic
- Inter-processor interrupts (async)
* - ``time_irq_i``
- in
- logic
- Timer interrupt in (async)
* - ``debug_req_i``
- in
- logic
- Debug request (async)
* - ``rvfi_o``
- out
- trace_port_t
- RISC-V Formal Interface port (RVFI)
* - ``cvxif_req_o``
- out
- cvxif_req_t
- Coprocessor Interface request interface port (CV-X-IF)
* - ``cvxif_resp_i``
- in
- cvxif_resp_t
- Coprocessor Interface response interface port (CV-X-IF)
* - ``axi_req_o``
- out
- req_t
- AXI master request interface port
* - ``axi_resp_i``
- in
- resp_t
- AXI master response interface port
Functionality
-------------
CV32A6-step1 implements a configuration which allows to connect coprocessor through CV-X-IF coprocessor interface, but the lack of MMU, A extension and data cache prevent from executing Linux.
.. list-table:: CV32A6-step1 Standard Configuration
:header-rows: 1
* - Standard Extension
- Specification
- Configurability
* - **I**: RV32i Base Integer Instruction Set
- [RVunpriv]
- ON
* - **C**: Standard Extension for Compressed Instructions
- [RVunpriv]
- ON
* - **M**: Standard Extension for Integer Multiplication and Division
- [RVunpriv]
- ON
* - **A**: Standard Extension for Atomic transaction
- [RVunpriv]
- OFF
* - **F and D**: Single and Double Precision Floating-Point
- [RVunpriv]
- OFF
* - **Zicount**: Performance Counters
- [RVunpriv]
- OFF
* - **Zicsr**: Control and Status Register Instructions
- [RVpriv]
- ON
* - **Zifencei**: Instruction-Fetch Fence
- [RVunpriv]
- ON
* - **Privilege**: Standard privilege modes M, S and U
- [RVpriv]
- ON
* - **SV39, SV32, SV0**: MMU capability
- [RVpriv]
- OFF
* - **PMP**: Memory Protection Unit
- [RVpriv]
- OFF
* - **CSR**: Control and Status Registers
- [RVpriv]
- ON
* - **AXI**: AXI interface
- [CV-X-IF]
- ON
* - **TRI**: Translation Response Interface (TRI)
- [OpenPiton]
- OFF
.. list-table:: CV32A6-step1 Micro-Architecture Configuration
:header-rows: 1
* - Micro-architecture
- Specification
- Configurability
* - **I$**: Instruction cache
- current spec
- ON
* - **D$**: Data cache
- current spec
- OFF
* - **Rename**: register Renaming
- current spec
- OFF
* - **Double Commit**: out of order pipeline execute stage
- current spec
- ON
* - **BP**: Branch Prediction
- current spec
- ON with no info storage
CVA6 memory interface complies with AXI5 specification including the Atomic_Transactions property support as defined in [AXI] section E1.1.
CVA6 coprocessor interface complies with CV-X-IF protocol specification as defined in [CV-X-IF].
The CV32A4-step1 core is fully synthesizable. It has been designed mainly for ASIC designs, but FPGA synthesis is supported as well.
For ASIC synthesis, the whole design is completely synchronous and uses positive-edge triggered flip-flops. The core occupies an area of about 80 kGE. The clock frequency can be more than 1GHz depending of technology.
Architecture
------------
.. figure:: ../images/CVA6_subsystems.png
:name: CVA6 System
:align: center
:alt:
CV32A6-step1 System

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..
Copyright (c) 2022 Thales
Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
https://solderpad.org/licenses/
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
OpenHW Group CV32A6-step1 design Specification
==============================================
.. toctree::
:maxdepth: 3
:caption: Contents:
cva6_intro
cva6_system
cva6_frontend
cva6_glossary

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sphinx>=2.1.0
sphinx_rtd_theme
sphinx
sphinx-rtd-theme
recommonmark
sphinxcontrib-svg2pdfconverter
sphinx_github_changelog