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Functional coverage : no need for cvxif directed tests (#1969)
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parent
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commit
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2 changed files with 9 additions and 24 deletions
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@ -46,7 +46,7 @@ workflow:
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variables:
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GIT_SUBMODULE_STRATEGY: recursive
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DASHBOARD: cva6
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DV_TARGET: cv32a6_embedded
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DV_TARGET: cv32a65x
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default:
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tags: [$TAGS_RUNNER]
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@ -428,23 +428,6 @@ csr_embedded_tests:
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- mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage
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- python3 .gitlab-ci/scripts/report_pass.py
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directed_xif-tests:
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extends:
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- .verif_test
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variables:
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DASHBOARD_SORT_INDEX: 16
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DASHBOARD_JOB_CATEGORY: "Functional Coverage"
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parallel:
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matrix:
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- list_num: 0
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DASHBOARD_JOB_TITLE: "Directed tests"
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DASHBOARD_JOB_DESCRIPTION: "Execute directed tests to improve functional coverage of cvxif"
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script:
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- mkdir -p artifacts/coverage
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- source verif/regress/dv-generated-xif-tests.sh
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- mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage
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- python3 .gitlab-ci/scripts/report_pass.py
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.backend_test:
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stage: backend tests
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before_script:
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@ -508,7 +491,6 @@ code_coverage-report:
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- generated_tests
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- directed_isacov-tests
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- generated_xif_tests
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- directed_xif-tests
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- csr_embedded_tests
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variables:
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DASHBOARD_JOB_TITLE: "Report merge coverage"
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13
verif/env/uvme/uvme_cva6_cfg.sv
vendored
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verif/env/uvme/uvme_cva6_cfg.sv
vendored
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@ -83,12 +83,15 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
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soft sys_clk_period == uvme_cva6_sys_default_clk_period; // see uvme_cva6_constants.sv
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}
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constraint cvxif_feature { //CV32A60X do not support dual read & write also the memory interface
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cvxif_cfg.dual_read_write_support_x == 0;
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cvxif_cfg.load_store_support_x == 0;
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cvxif_cfg.seq_cus_instr_x2_enabled == 1;
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cvxif_cfg.reg_cus_crosses_enabled == 0;
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constraint cvxif_feature { //CV32A65X do not support dual read & write also the memory interface
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cvxif_cfg.dual_read_write_support_x == 0;
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cvxif_cfg.load_store_support_x == 0;
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cvxif_cfg.seq_cus_instr_x2_enabled == 1;
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cvxif_cfg.reg_cus_crosses_enabled == 0;
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cvxif_cfg.mode_s_supported == mode_s_supported;
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cvxif_cfg.mode_u_supported == mode_u_supported;
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}
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constraint cva6_riscv_cons {
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xlen == uvma_core_cntrl_pkg::MXL_32;
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ilen == 32;
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