mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-23 13:47:13 -04:00
Altera flow support (#2649)
Integration of bitstream generation for Altera APU in general flow. * Automatic generation of IPs and sources required for Altera FPGA * Adaptation of bootrom code (UART used in Altera is different and needs a different driver) * Generation of project for Quartus Pro adding required sources and constraints - Quartus Pro licence required by users * Configuration file for openocd connection with vJTAG tap
This commit is contained in:
AngelaGonzalezMarino
GitHub
parent
2155d0e9c4
commit
eab88770ec
24 changed files with 5540 additions and 15 deletions
77
Makefile
77
Makefile
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@ -40,7 +40,10 @@ torture-logs :=
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elf_file ?= tmp/riscv-tests/build/benchmarks/dhrystone.riscv
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# board name for bitstream generation. Currently supported: kc705, genesys2, nexys_video
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BOARD ?= genesys2
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ALTERA_BOARD ?= DK-DEV-AGF014E3ES
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ALTERA_FAMILY ?= "AGILEX"
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ALTERA_PART ?= AGFB014R24B2E2V
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PLATFORM = "PLAT_XILINX"
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# root path
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mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
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root-dir := $(dir $(mkfile_path))
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@ -166,17 +169,11 @@ src := $(if $(spike-tandem),verif/tb/core/uvma_core_cntrl_pkg.sv)
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$(wildcard corev_apu/fpga/src/axi_slice/src/*.sv) \
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$(wildcard corev_apu/src/axi_riscv_atomics/src/*.sv) \
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$(wildcard corev_apu/axi_mem_if/src/*.sv) \
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$(wildcard corev_apu/riscv-dbg/src/*.sv) \
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corev_apu/rv_plic/rtl/rv_plic_target.sv \
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corev_apu/rv_plic/rtl/rv_plic_gateway.sv \
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corev_apu/rv_plic/rtl/plic_regmap.sv \
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corev_apu/rv_plic/rtl/plic_top.sv \
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corev_apu/riscv-dbg/src/dmi_cdc.sv \
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corev_apu/riscv-dbg/src/dmi_jtag.sv \
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corev_apu/riscv-dbg/src/dmi_jtag_tap.sv \
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corev_apu/riscv-dbg/src/dm_csrs.sv \
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corev_apu/riscv-dbg/src/dm_mem.sv \
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corev_apu/riscv-dbg/src/dm_sba.sv \
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corev_apu/riscv-dbg/src/dm_top.sv \
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corev_apu/riscv-dbg/debug_rom/debug_rom.sv \
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corev_apu/register_interface/src/apb_to_reg.sv \
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vendor/pulp-platform/axi/src/axi_multicut.sv \
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@ -236,6 +233,52 @@ uart_src_sv:= corev_apu/fpga/src/apb_uart/src/slib_clock_div.sv \
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uart_src_sv := $(addprefix $(root-dir), $(uart_src_sv))
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fpga_src := $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/ariane-ethernet/*.sv) common/local/util/tc_sram_fpga_wrapper.sv common/local/util/hpdcache_sram_1rw.sv common/local/util/hpdcache_sram_wbyteenable_1rw.sv vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx32.sv vendor/pulp-platform/fpga-support/rtl/SyncSpRam.sv
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altera_src := $(shell find $(root-dir)/corev_apu/altera/src -type f \( -name "*.v" -o -name "*.sv" -o -name "*.svh" \) -print | sed 's|//|/|g')
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altera_src += $(src)
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altera_src += $(shell find $(root-dir)/corev_apu/fpga/src -type f \( -name "*.v" -o -name "*.sv" \) -print | sed 's|//|/|g')
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altera_src += $(shell find $(root-dir)core/cvfpu/src/common_cells/src/ -maxdepth 1 -type f \( -name "*.v" -o -name "*.sv" -o -name "*.vhd" -o -name "*.svh" \) -print)
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altera_axi_src := $(shell find $(root-dir)/vendor/pulp-platform/axi/src -type f \( -name "*.v" -o -name "*.sv" \) -print | sed 's|//|/|g')
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altera_src += $(root-dir)corev_apu/rv_plic/rtl/top_pkg.sv \
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$(root-dir)corev_apu/rv_plic/rtl/tlul_pkg.sv \
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$(root-dir)corev_apu/rv_plic/rtl/rv_plic_reg_top.sv \
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$(root-dir)corev_apu/rv_plic/rtl/rv_plic_reg_pkg.sv \
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$(root-dir)corev_apu/rv_plic/rtl/rv_plic.sv \
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$(root-dir)corev_apu/rv_plic/rtl/prim_subreg_ext.sv \
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$(root-dir)corev_apu/rv_plic/rtl/prim_subreg.sv \
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$(root-dir)vendor/pulp-platform/common_cells/src/cdc_fifo_gray.sv \
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$(root-dir)riscv-dbg/src/dm_obi_top.sv \
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$(root-dir)core/include/instr_tracer_pkg.sv \
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$(root-dir)core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv \
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$(root-dir)core/cache_subsystem/amo_alu.sv
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altera_filter := corev_apu/tb/ariane_testharness.sv \
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corev_apu/tb/ariane_peripherals.sv \
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corev_apu/tb/rvfi_tracer.sv \
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corev_apu/tb/common/uart.sv \
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corev_apu/tb/common/SimDTM.sv \
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corev_apu/tb/common/SimJTAG.sv \
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corev_apu/fpga/src/apb/src/apb_test.sv \
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corev_apu/fpga/src/ariane_xilinx.sv \
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corev_apu/fpga/ariane_peripherals_xilinx.sv \
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corev_apu/fpga/src/apb/test/tb_apb_cdc.sv \
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corev_apu/fpga/src/apb/test/tb_apb_regs.sv \
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corev_apu/fpga/src/apb/test/tb_apb_demux.sv \
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corev_apu/fpga/src/gpio/test/tb_gpio.sv \
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vendor/pulp-platform/axi/src/axi_test.sv \
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corev_apu/riscv-dbg/src/dm_pkg.sv \
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corev_apu/riscv-dbg/src/dmi_jtag_tap.sv \
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corev_apu/riscv-dbg/src/dmi_jtag.sv \
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corev_apu/fpga/src/apb_uart/src/reg_uart_wrap.sv
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altera_filter := $(addprefix $(root-dir), $(altera_filter))
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xil_debug_filter = $(addprefix $(root-dir), corev_apu/riscv-dbg/src/dm_obi_top.sv)
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xil_debug_filter += $(addprefix $(root-dir), corev_apu/riscv-dbg/src/dm_pkg.sv)
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xil_debug_filter += $(addprefix $(root-dir), corev_apu/riscv-dbg/src/dmi_vjtag_tap.sv)
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xil_debug_filter += $(addprefix $(root-dir), corev_apu/riscv-dbg/src/dmi_vjtag.sv)
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src := $(filter-out $(xil_debug_filter), $(src))
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fpga_src := $(addprefix $(root-dir), $(fpga_src)) src/bootrom/bootrom_$(XLEN).sv
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# look for testbenches
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@ -738,7 +781,7 @@ fpga_filter += $(addprefix $(root-dir), core/cache_subsystem/hpdcache/rtl/src/co
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fpga_filter += $(addprefix $(root-dir), core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wmask_1rw.sv)
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src/bootrom/bootrom_$(XLEN).sv:
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$(MAKE) -C corev_apu/fpga/src/bootrom BOARD=$(BOARD) XLEN=$(XLEN) bootrom_$(XLEN).sv
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$(MAKE) -C corev_apu/fpga/src/bootrom BOARD=$(BOARD) XLEN=$(XLEN) PLATFORM=$(PLATFORM) bootrom_$(XLEN).sv
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fpga: $(ariane_pkg) $(src) $(fpga_src) $(uart_src) $(src_flist)
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@echo "[FPGA] Generate sources"
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@ -750,6 +793,19 @@ fpga: $(ariane_pkg) $(src) $(fpga_src) $(uart_src) $(src_flist)
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@echo "[FPGA] Generate Bitstream"
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$(MAKE) -C corev_apu/fpga BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS)
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altera: PLATFORM := "PLAT_AGILEX"
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altera: $(ariane_pkg) $(src) $(fpga_src) $(src_flist)
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@echo "[FPGA] Generate sources"
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@echo $(ariane_pkg) > corev_apu/altera/sourcelist.txt
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@echo $(filter-out $(fpga_filter), $(src_flist)) >> corev_apu/altera/sourcelist.txt
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@echo $(filter-out $(fpga_filter) $(altera_filter), $(src)) >> corev_apu/altera/sourcelist.txt
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@echo $(filter-out $(altera_filter), $(fpga_src)) >> corev_apu/altera/sourcelist.txt
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@echo $(filter-out $(fpga_filter) $(altera_filter) $(uart_src_sv), $(altera_src)) >> corev_apu/altera/sourcelist.txt
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@echo $(filter-out $(fpga_filter) $(altera_filter), $(altera_axi_src)) >> corev_apu/altera/sourcelist.txt
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@echo "[FPGA] Generate Bitstream"
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$(MAKE) -C corev_apu/altera ALTERA_PART=$(ALTERA_PART) ALTERA_BOARD=$(ALTERA_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS)
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.PHONY: fpga
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build-spike:
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@ -762,6 +818,9 @@ clean:
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$(MAKE) -C corev_apu/fpga clean
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$(MAKE) -C corev_apu/fpga/src/bootrom BOARD=$(BOARD) XLEN=$(XLEN) clean
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clean-altera: clean
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$(MAKE) -C corev_apu/altera clean
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.PHONY:
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build sim sim-verilate clean \
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$(riscv-asm-tests) $(addsuffix _verilator,$(riscv-asm-tests)) \
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@ -29,6 +29,8 @@
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${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/SyncDpRam.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/AsyncDpRam.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/AsyncThreePortRam.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/SyncThreePortRam.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/SyncDpRam_ind_r_w.sv
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+incdir+${CVA6_REPO_DIR}/core/include/
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+incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/include/
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197
corev_apu/altera/Makefile
Normal file
197
corev_apu/altera/Makefile
Normal file
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@ -0,0 +1,197 @@
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# // Copyright (c) 2024 PlanV Technologies
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# // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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# // Copyright and related rights are licensed under the Solderpad Hardware
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# // License, Version 0.51 (the "License"); you may not use this file except in
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# // compliance with the License. You may obtain a copy of the License at
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# // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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# // or agreed to in writing, software, hardware and materials distributed under
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# // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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# // CONDITIONS OF ANY KIND, either express or implied. See the License for the
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# // specific language governing permissions and limitations under the License.
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# // Description: Makefile for Altera project
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# // Author: Mustafa Karadayi, PlanV Technology
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###################################################################
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# Project Configuration:
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#
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# Specify the name of the design (project) and the Quartus II
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# Settings File (.qsf)
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###################################################################
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PROJECT =Example-Project##mkdigitals ask for project name
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TOP_LEVEL_ENTITY = ####mkdigitals ask for the top level entity
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ASSIGNMENT_FILES = $(PROJECT).qpf $(PROJECT).qsf
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SOURCES_FILE = ./sourcelist.txt
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# Define the output bitstream file
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BITSTREAM := $(PROJECT).sof
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###################################################################
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# Part, Family, Boardfile DE1 or DE2
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## FAMILY COMES FROM THE CALLING MAKEFILE
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## PART COMES FROM THE CALLING MAKEFILE
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## BOARDFILE COMES FROM THE CALLING MAKEFILE ## mkdigitals ask if there is a board file
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###################################################################
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###################################################################
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# Setup your sources here
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SRCS = $(shell cat $(SOURCES_FILE))
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###################################################################
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# Main Targets
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#
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# all: build everything
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# clean: remove output files and database
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# program: program your device with the compiled design
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###################################################################
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all: create_project \
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write_settings \
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write_loc_constraints \
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write_io_standard_constraints \
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write_ip_files \
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write_search_paths \
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write_source_files \
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write_timing_constraints \
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generate_ips \
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sta
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clean:
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$(RM) -rf *.rpt *.chg smart.log *.htm *.eqn *.pin *.sof *.pof db incremental_db *.summary *.smsg *.jdi $(ASSIGNMENT_FILES)
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# Capture the Quartus version
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QUARTUS_VERSION := $(shell quartus_sh --version | grep -oP 'Version \K[0-9]+\.[0-9]+')
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CURRENT_DATETIME := $(shell date +"%H:%M:%S %B %d, %Y")
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create_project:
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@echo "Creating or regenerating $(PROJECT).qpf"
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@rm -f "$(PROJECT).qpf"
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@touch "$(PROJECT).qpf"
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@echo "QUARTUS_VERSION = \"$(QUARTUS_VERSION)\"" >> "$(PROJECT).qpf"
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@echo "DATE = \"$(CURRENT_DATETIME)\"" >> "$(PROJECT).qpf"
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@echo "PROJECT_REVISION = \"$(PROJECT)\"" >> "$(PROJECT).qpf"
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@echo "Creating or regenerating $(PROJECT).qsf"
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@rm -f "$(PROJECT).qsf"
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@touch "$(PROJECT).qsf"
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$(QSYS_PATH)qsys-script --script=ip/interconnect.tcl
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$(QSYS_PATH)qsys-generate interconnect.qsys --quartus_project=ip/interconnect --synthesis
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rm -f interconnect/*.v
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rm -f interconnect/*.vhd
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rm -f interconnect/synth/*.v
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write_settings:
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@echo "Reading from settings.csv and writing to $(PROJECT).qsf with modifications"
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@while IFS= read -r line; do \
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echo "set_global_assignment -name $$line" >> "$(PROJECT).qsf"; \
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done < settings.csv
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write_loc_constraints:
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@echo "Reading from loc_constraints.csv and writing to $(PROJECT).qsf with modifications"
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@while IFS= read -r line; do \
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echo "set_location_assignment $$line" >> "$(PROJECT).qsf"; \
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done < loc_constraints.csv
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write_io_standard_constraints:
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@echo "Reading from io_standard_constraints.csv and writing to $(PROJECT).qsf with modifications"
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@while IFS= read -r line; do \
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echo "set_instance_assignment -name $$line" >> "$(PROJECT).qsf"; \
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done < io_standard_constraints.csv
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write_ip_files:
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@echo "Reading from ip_files.csv and writing to $(PROJECT).qsf with modifications"
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@while IFS= read -r line; do \
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echo "set_global_assignment -name IP_FILE $$line" >> "$(PROJECT).qsf"; \
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done < ip_files.csv
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write_search_paths:
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@echo "Reading from search_paths.csv and writing to $(PROJECT).qsf with modifications"
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@while IFS= read -r line; do \
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echo "set_global_assignment -name SEARCH_PATH $$line" >> "$(PROJECT).qsf"; \
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done < search_paths.csv
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write_source_files:
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@find ./interconnect -type f -name "*.v" -o -name "*.sv" -o -name "*.svh" >> $(SOURCES_FILE)
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@echo $(var)
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@echo >> $(SOURCES_FILE)
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@echo "Reading from $(SOURCES_FILE) and writing to $(PROJECT).qsf with modifications"
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@while IFS= read -r line; do \
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for word in $$line; do \
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if echo "$$word" | grep -q "\.vhd$$"; then \
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echo "set_global_assignment -name VHDL_FILE $$word" >> "$(PROJECT).qsf"; \
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elif echo "$$word" | grep -q "\.v$$"; then \
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echo "set_global_assignment -name VERILOG_FILE $$word" >> "$(PROJECT).qsf"; \
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elif echo "$$word" | grep -q "\.sv$$"; then \
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echo "set_global_assignment -name SYSTEMVERILOG_FILE $$word" >> "$(PROJECT).qsf"; \
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elif echo "$$word" | grep -q "\.svh$$"; then \
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echo "set_global_assignment -name SYSTEMVERILOG_FILE $$word" >> "$(PROJECT).qsf"; \
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else \
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echo "set_global_assignment -name SOURCE_FILE $$word" >> "$(PROJECT).qsf"; \
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fi; \
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done; \
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done < $(SOURCES_FILE)
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write_timing_constraints:
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@echo "Generating constraints file list"
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find ./constraints -type f -name "*.sdc" -exec realpath {} \; | sed 's|^|set_global_assignment -name SDC_FILE |' >> "$(PROJECT).qsf"
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generate_ips:
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$(QSYS_PATH)qsys-script --script=ip/test_mm_ccb_0.tcl
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$(QSYS_PATH)qsys-script --script=ip/cva6_intel_jtag_uart_0.tcl
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$(QSYS_PATH)qsys-script --script=ip/ed_synth_emif_fm_0.tcl
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$(QSYS_PATH)qsys-script --script=ip/emif_cal.tcl
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$(QSYS_PATH)qsys-script --script=ip/iddr_intel.tcl
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$(QSYS_PATH)qsys-script --script=ip/io_pll.tcl
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$(QSYS_PATH)qsys-script --script=ip/iobuf.tcl
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$(QSYS_PATH)qsys-script --script=ip/oddr_intel.tcl
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$(QSYS_PATH)qsys-script --script=ip/vJTAG.tcl
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$(QUARTUS_PATH)quartus_ipgenerate --generate_project_ip_files $(PROJECT)
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map:
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@echo "Running Quartus Map"
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$(QUARTUS_PATH)quartus_syn $(PROJECT)
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fit: map
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@echo "Running Quartus Fit"
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$(QUARTUS_PATH)quartus_fit $(PROJECT)
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asm: fit
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@echo "Running Quartus Assembly"
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$(QUARTUS_PATH)quartus_asm $(PROJECT)
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sta: asm
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@echo "Running Quartus Timing Analysis"
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$(QUARTUS_PATH)quartus_sta $(PROJECT) --do_report_timing
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clean:
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@echo "Cleaning project files"
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rm -f $(PROJECT).qsf $(PROJECT).qpf $(PROJECT).map.rpt $(PROJECT).fit.rpt $(PROJECT).asm.rpt $(PROJECT).sta.rpt
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rm -f interconnect.qsys*
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rm -f *.backup
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rm -f *.hex
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rm -f *.txt
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rm -f *.ip
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rm -f ip/board.info
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rm -f ip/*.qpf
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rm -f ip/*.qsf
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rm -rf ip/dni
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rm -rf ip/.qsys_edit
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rm -rf ip/qdb
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rm -rf output_files
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rm -rf db incremental_db
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rm -rf qdb
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rm -rf tmp-clearbox
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rm -rf intel
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rm -rf dni
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rm -rf interconnect
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rm -rf ip/interconnect
|
||||
rm -rf cva6_intel_jtag_uart_0
|
||||
rm -rf ed_synth_emif_fm_0
|
||||
rm -rf emif_cal
|
||||
rm -rf iddr_intel
|
||||
rm -rf oddr_intel
|
||||
rm -rf test_mm_ccb_0
|
||||
rm -rf vJTAG
|
||||
rm -rf interconnect
|
||||
rm -rf io_pll
|
||||
rm -rf iobuf
|
||||
|
||||
$(QUARTUS_PATH)quartus_ipgenerate --clean $(PROJECT)
|
||||
|
||||
.PHONY: all write_search_paths write_source_files map fit asm sta clean
|
||||
47
corev_apu/altera/altera.cfg
Normal file
47
corev_apu/altera/altera.cfg
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
# * Copyright 2024 Thales AVS
|
||||
# * Copyright 2024 PlanV Technologies
|
||||
# * Copyright and related rights are licensed under the Solderpad Hardware
|
||||
# * License, Version 0.51 (the âÂÂLicenseâÂÂ); you may not use this file except in
|
||||
# * compliance with the License. You may obtain a copy of the License at
|
||||
# * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
|
||||
# * or agreed to in writing, software, hardware and materials distributed under
|
||||
# * this License is distributed on an âÂÂAS ISâ BASIS, WITHOUT WARRANTIES OR
|
||||
# * CONDITIONS OF ANY KIND, either express or implied. See the License for the
|
||||
# * specific language governing permissions and limitations under the License.
|
||||
# *
|
||||
# * Author: Nicolas Levasseur, Thales AVS
|
||||
# * Additional contributions by Angela Gonzalez, PlanV Technologies
|
||||
# * Date: 8.11.2024
|
||||
# * Description: Configuration file for openocd connection
|
||||
# *
|
||||
# */
|
||||
|
||||
adapter driver aji_client
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME agilex7
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME.fpga tap -irlen 10 -expected-id 0xC341A0DD
|
||||
#0xC341A0DD
|
||||
|
||||
# VJTAG ID :
|
||||
# -------------------------------------------------------
|
||||
# | 31 - 27 | 26 - 19 | 18 - 8 | 7 - 0 |
|
||||
# |-----------------------------------------------------|
|
||||
# | Node Version | Node ID | Node mfg_id | Node_inst_id |
|
||||
# -------------------------------------------------------
|
||||
# Info : node 0 idcode=00406E00 position_n=0 CVA6 core #0
|
||||
|
||||
vjtag create $_CHIPNAME.fpga.tap.cva6.0 -chain-position $_CHIPNAME.fpga.tap -expected-id 0x00406E00
|
||||
target create $_CHIPNAME.cva6.0 riscv -chain-position $_CHIPNAME.fpga.tap.cva6.0 -coreid 0
|
||||
|
||||
scan_chain
|
||||
|
||||
init
|
||||
|
||||
halt
|
||||
echo "Ready for Remote Connections"
|
||||
|
||||
7
corev_apu/altera/constraints/SDC1.sdc
Normal file
7
corev_apu/altera/constraints/SDC1.sdc
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
set_false_path -from [get_clocks {inst_ddr4|emif_fm_0_core_usr_clk}] -to [get_clocks {clocks|iopll_0_outclk0}]
|
||||
set_false_path -from [get_clocks {clocks|iopll_0_outclk0}] -to [get_clocks {inst_ddr4|emif_fm_0_core_usr_clk}]
|
||||
set_false_path -from [get_clocks {clocks|iopll_0_outclk0}] -to [get_clocks {clocks|iopll_0_refclk}]
|
||||
set_false_path -from [get_clocks {clocks|iopll_0_refclk}] -to [get_clocks {clocks|iopll_0_outclk0}]
|
||||
set_disable_timing [get_ports led[*]]
|
||||
set_false_path -hold -through [get_pins -hierarchical "*async*"]
|
||||
set_max_delay -through [get_pins -hierarchical "*async*"] 5.000
|
||||
7
corev_apu/altera/io_standard_constraints.csv
Normal file
7
corev_apu/altera/io_standard_constraints.csv
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
IO_STANDARD "1.2 V" -to cpu_resetn -entity cva6_altera
|
||||
IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to pll_ref_clk_p -entity cva6_altera
|
||||
IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to clk_ddr4_ch0_p -entity cva6_altera
|
||||
IO_STANDARD "1.2 V" -to led[3] -entity cva6_altera
|
||||
IO_STANDARD "1.2 V" -to led[2] -entity cva6_altera
|
||||
IO_STANDARD "1.2 V" -to led[1] -entity cva6_altera
|
||||
IO_STANDARD "1.2 V" -to led[0] -entity cva6_altera
|
||||
|
Can't render this file because it contains an unexpected character in line 1 and column 13.
|
70
corev_apu/altera/ip/cva6_intel_jtag_uart_0.tcl
Normal file
70
corev_apu/altera/ip/cva6_intel_jtag_uart_0.tcl
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
# Quartus Pro License required to use this file
|
||||
package require -exact qsys 24.1
|
||||
|
||||
# create the system "cva6_intel_jtag_uart_0"
|
||||
proc do_create_cva6_intel_jtag_uart_0 {} {
|
||||
# create the system
|
||||
create_system cva6_intel_jtag_uart_0
|
||||
set_project_property BOARD {default}
|
||||
set_project_property DEVICE {AGFB014R24B2E2V}
|
||||
set_project_property DEVICE_FAMILY {Agilex 7}
|
||||
set_project_property HIDE_FROM_IP_CATALOG {false}
|
||||
set_use_testbench_naming_pattern 0 {}
|
||||
|
||||
# add HDL parameters
|
||||
|
||||
# add the components
|
||||
add_instance jtag_uart_0 altera_avalon_jtag_uart 19.2.4
|
||||
set_instance_parameter_value jtag_uart_0 {allowMultipleConnections} {0}
|
||||
set_instance_parameter_value jtag_uart_0 {hubInstanceID} {0}
|
||||
set_instance_parameter_value jtag_uart_0 {readBufferDepth} {64}
|
||||
set_instance_parameter_value jtag_uart_0 {readIRQThreshold} {8}
|
||||
set_instance_parameter_value jtag_uart_0 {simInputCharacterStream} {}
|
||||
set_instance_parameter_value jtag_uart_0 {simInteractiveOptions} {NO_INTERACTIVE_WINDOWS}
|
||||
set_instance_parameter_value jtag_uart_0 {useRegistersForReadBuffer} {0}
|
||||
set_instance_parameter_value jtag_uart_0 {useRegistersForWriteBuffer} {0}
|
||||
set_instance_parameter_value jtag_uart_0 {useRelativePathForSimFile} {0}
|
||||
set_instance_parameter_value jtag_uart_0 {writeBufferDepth} {64}
|
||||
set_instance_parameter_value jtag_uart_0 {writeIRQThreshold} {8}
|
||||
set_instance_property jtag_uart_0 AUTO_EXPORT true
|
||||
|
||||
# add wirelevel expressions
|
||||
|
||||
# preserve ports for debug
|
||||
|
||||
# add the exports
|
||||
set_interface_property clk EXPORT_OF jtag_uart_0.clk
|
||||
set_interface_property reset EXPORT_OF jtag_uart_0.reset
|
||||
set_interface_property avalon_jtag_slave EXPORT_OF jtag_uart_0.avalon_jtag_slave
|
||||
set_interface_property irq EXPORT_OF jtag_uart_0.irq
|
||||
|
||||
# set values for exposed HDL parameters
|
||||
|
||||
# set the the module properties
|
||||
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
|
||||
<bonusData>
|
||||
<element __value="jtag_uart_0">
|
||||
<datum __value="_sortIndex" value="0" type="int" />
|
||||
</element>
|
||||
</bonusData>
|
||||
}
|
||||
set_module_property FILE {cva6_intel_jtag_uart_0.ip}
|
||||
set_module_property GENERATION_ID {0x00000000}
|
||||
set_module_property NAME {cva6_intel_jtag_uart_0}
|
||||
|
||||
# save the system
|
||||
sync_sysinfo_parameters
|
||||
save_system cva6_intel_jtag_uart_0
|
||||
}
|
||||
|
||||
proc do_set_exported_interface_sysinfo_parameters {} {
|
||||
load_system cva6_intel_jtag_uart_0.ip
|
||||
set_exported_interface_sysinfo_parameter_value clk clock_rate {300000000}
|
||||
save_system cva6_intel_jtag_uart_0.ip
|
||||
}
|
||||
|
||||
# create all the systems, from bottom up
|
||||
do_create_cva6_intel_jtag_uart_0
|
||||
|
||||
# set system info parameters on exported interface, from bottom up
|
||||
do_set_exported_interface_sysinfo_parameters
|
||||
1640
corev_apu/altera/ip/ed_synth_emif_fm_0.tcl
Normal file
1640
corev_apu/altera/ip/ed_synth_emif_fm_0.tcl
Normal file
File diff suppressed because it is too large
Load diff
66
corev_apu/altera/ip/emif_cal.tcl
Normal file
66
corev_apu/altera/ip/emif_cal.tcl
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
# Quartus Pro License required to use this file
|
||||
package require -exact qsys 24.1
|
||||
|
||||
# create the system "emif_cal"
|
||||
proc do_create_emif_cal {} {
|
||||
# create the system
|
||||
create_system emif_cal
|
||||
set_project_property BOARD {default}
|
||||
set_project_property DEVICE {AGFB014R24B2E2V}
|
||||
set_project_property DEVICE_FAMILY {Agilex 7}
|
||||
set_project_property HIDE_FROM_IP_CATALOG {true}
|
||||
set_use_testbench_naming_pattern 0 {}
|
||||
|
||||
# add HDL parameters
|
||||
|
||||
# add the components
|
||||
add_instance emif_cal_0 altera_emif_cal 2.7.4
|
||||
set_instance_parameter_value emif_cal_0 {AXM_ID_NUM} {0}
|
||||
set_instance_parameter_value emif_cal_0 {DIAG_ENABLE_JTAG_UART} {0}
|
||||
set_instance_parameter_value emif_cal_0 {DIAG_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED}
|
||||
set_instance_parameter_value emif_cal_0 {DIAG_EXPORT_VJI} {0}
|
||||
set_instance_parameter_value emif_cal_0 {DIAG_EXTRA_CONFIGS} {}
|
||||
set_instance_parameter_value emif_cal_0 {DIAG_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP}
|
||||
set_instance_parameter_value emif_cal_0 {DIAG_SIM_VERBOSE} {0}
|
||||
set_instance_parameter_value emif_cal_0 {DIAG_SYNTH_FOR_SIM} {0}
|
||||
set_instance_parameter_value emif_cal_0 {ENABLE_DDRT} {0}
|
||||
set_instance_parameter_value emif_cal_0 {NUM_CALBUS_INTERFACE} {1}
|
||||
set_instance_parameter_value emif_cal_0 {PHY_DDRT_EXPORT_CLK_STP_IF} {0}
|
||||
set_instance_parameter_value emif_cal_0 {SHORT_QSYS_INTERFACE_NAMES} {1}
|
||||
set_instance_property emif_cal_0 AUTO_EXPORT true
|
||||
|
||||
# add wirelevel expressions
|
||||
|
||||
# preserve ports for debug
|
||||
|
||||
# add the exports
|
||||
set_interface_property emif_calbus_0 EXPORT_OF emif_cal_0.emif_calbus_0
|
||||
set_interface_property emif_calbus_clk EXPORT_OF emif_cal_0.emif_calbus_clk
|
||||
|
||||
# set values for exposed HDL parameters
|
||||
|
||||
# set the the module properties
|
||||
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
|
||||
<bonusData>
|
||||
<element __value="emif_cal_0">
|
||||
<datum __value="_sortIndex" value="0" type="int" />
|
||||
</element>
|
||||
</bonusData>
|
||||
}
|
||||
set_module_property FILE {emif_cal.ip}
|
||||
set_module_property GENERATION_ID {0x00000000}
|
||||
set_module_property NAME {emif_cal}
|
||||
|
||||
# save the system
|
||||
sync_sysinfo_parameters
|
||||
save_system emif_cal
|
||||
}
|
||||
|
||||
proc do_set_exported_interface_sysinfo_parameters {} {
|
||||
}
|
||||
|
||||
# create all the systems, from bottom up
|
||||
do_create_emif_cal
|
||||
|
||||
# set system info parameters on exported interface, from bottom up
|
||||
do_set_exported_interface_sysinfo_parameters
|
||||
74
corev_apu/altera/ip/iddr_intel.tcl
Normal file
74
corev_apu/altera/ip/iddr_intel.tcl
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
# Quartus Pro License required to use this file
|
||||
package require -exact qsys 24.1
|
||||
|
||||
# create the system "iddr_intel"
|
||||
proc do_create_iddr_intel {} {
|
||||
# create the system
|
||||
create_system iddr_intel
|
||||
set_project_property BOARD {default}
|
||||
set_project_property DEVICE {AGFB014R24B2E2V}
|
||||
set_project_property DEVICE_FAMILY {Agilex 7}
|
||||
set_project_property HIDE_FROM_IP_CATALOG {true}
|
||||
set_use_testbench_naming_pattern 0 {}
|
||||
|
||||
# add HDL parameters
|
||||
|
||||
# add the components
|
||||
add_instance gpio_0 altera_gpio 22.1.0
|
||||
set_instance_parameter_value gpio_0 {EXT_DRIVER_PARAM} {0}
|
||||
set_instance_parameter_value gpio_0 {GENERATE_SDC_FILE} {0}
|
||||
set_instance_parameter_value gpio_0 {IP_MIGRATE_PORT_MAP_FILE} {altddio_bidir_port_map.csv}
|
||||
set_instance_parameter_value gpio_0 {PIN_TYPE_GUI} {Input}
|
||||
set_instance_parameter_value gpio_0 {SIZE} {1}
|
||||
set_instance_parameter_value gpio_0 {gui_areset_mode} {None}
|
||||
set_instance_parameter_value gpio_0 {gui_bus_hold} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_ddio_with_delay} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_diff_buff} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_enable_cke} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_enable_migratable_port_names} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_enable_termination_ports} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_hr_logic} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_io_reg_mode} {DDIO}
|
||||
set_instance_parameter_value gpio_0 {gui_open_drain} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_pseudo_diff} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_separate_io_clks} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_sreset_mode} {None}
|
||||
set_instance_parameter_value gpio_0 {gui_use_oe} {0}
|
||||
set_instance_property gpio_0 AUTO_EXPORT true
|
||||
|
||||
# add wirelevel expressions
|
||||
|
||||
# preserve ports for debug
|
||||
|
||||
# add the exports
|
||||
set_interface_property ck EXPORT_OF gpio_0.ck
|
||||
set_interface_property dout EXPORT_OF gpio_0.dout
|
||||
set_interface_property pad_in EXPORT_OF gpio_0.pad_in
|
||||
|
||||
# set values for exposed HDL parameters
|
||||
|
||||
# set the the module properties
|
||||
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
|
||||
<bonusData>
|
||||
<element __value="gpio_0">
|
||||
<datum __value="_sortIndex" value="0" type="int" />
|
||||
</element>
|
||||
</bonusData>
|
||||
}
|
||||
set_module_property FILE {iddr_intel.ip}
|
||||
set_module_property GENERATION_ID {0x00000000}
|
||||
set_module_property NAME {iddr_intel}
|
||||
|
||||
# save the system
|
||||
sync_sysinfo_parameters
|
||||
save_system iddr_intel
|
||||
}
|
||||
|
||||
proc do_set_exported_interface_sysinfo_parameters {} {
|
||||
}
|
||||
|
||||
# create all the systems, from bottom up
|
||||
do_create_iddr_intel
|
||||
|
||||
# set system info parameters on exported interface, from bottom up
|
||||
do_set_exported_interface_sysinfo_parameters
|
||||
2523
corev_apu/altera/ip/interconnect.tcl
Normal file
2523
corev_apu/altera/ip/interconnect.tcl
Normal file
File diff suppressed because it is too large
Load diff
312
corev_apu/altera/ip/io_pll.tcl
Normal file
312
corev_apu/altera/ip/io_pll.tcl
Normal file
|
|
@ -0,0 +1,312 @@
|
|||
# Quartus Pro License required to use this file
|
||||
package require -exact qsys 24.1
|
||||
|
||||
# create the system "io_pll"
|
||||
proc do_create_io_pll {} {
|
||||
# create the system
|
||||
create_system io_pll
|
||||
set_project_property BOARD {default}
|
||||
set_project_property DEVICE {AGFB014R24B2E2V}
|
||||
set_project_property DEVICE_FAMILY {Agilex 7}
|
||||
set_project_property HIDE_FROM_IP_CATALOG {true}
|
||||
set_use_testbench_naming_pattern 0 {}
|
||||
|
||||
# add HDL parameters
|
||||
|
||||
# add the components
|
||||
add_instance iopll_0 altera_iopll 19.3.1
|
||||
set_instance_parameter_value iopll_0 {gui_active_clk} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src0} {c_m_cnt_in_src_ph_mux_clk}
|
||||
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src1} {c_m_cnt_in_src_ph_mux_clk}
|
||||
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src2} {c_m_cnt_in_src_ph_mux_clk}
|
||||
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src3} {c_m_cnt_in_src_ph_mux_clk}
|
||||
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src4} {c_m_cnt_in_src_ph_mux_clk}
|
||||
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src5} {c_m_cnt_in_src_ph_mux_clk}
|
||||
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src6} {c_m_cnt_in_src_ph_mux_clk}
|
||||
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src7} {c_m_cnt_in_src_ph_mux_clk}
|
||||
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src8} {c_m_cnt_in_src_ph_mux_clk}
|
||||
set_instance_parameter_value iopll_0 {gui_cal_code_hex_file} {iossm.hex}
|
||||
set_instance_parameter_value iopll_0 {gui_cal_converge} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cal_error} {cal_clean}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter0} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter1} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter10} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter11} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter12} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter13} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter14} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter15} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter16} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter17} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter2} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter3} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter4} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter5} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter6} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter7} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter8} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter9} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_outclk_index} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_clk_bad} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_global} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string0} {outclk0}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string1} {outclk1}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string10} {outclk10}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string11} {outclk11}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string12} {outclk12}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string13} {outclk13}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string14} {outclk14}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string15} {outclk15}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string16} {outclk16}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string17} {outclk17}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string2} {outclk2}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string3} {outclk3}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string4} {outclk4}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string5} {outclk5}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string6} {outclk6}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string7} {outclk7}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string8} {outclk8}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string9} {outclk9}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_to_compensate} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_debug_mode} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c0} {1}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c1} {25}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c10} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c11} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c12} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c13} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c14} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c15} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c16} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c17} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c2} {25}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c3} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c4} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c5} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c6} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c7} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c8} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c9} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_n} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_dps_cntr} {C0}
|
||||
set_instance_parameter_value iopll_0 {gui_dps_dir} {Positive}
|
||||
set_instance_parameter_value iopll_0 {gui_dps_num} {1}
|
||||
set_instance_parameter_value iopll_0 {gui_dsm_out_sel} {1st_order}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle0} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle1} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle10} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle11} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle12} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle13} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle14} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle15} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle16} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle17} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle2} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle3} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle4} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle5} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle6} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle7} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle8} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle9} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_en_adv_params} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_en_dps_ports} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_en_extclkout_ports} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_en_iossm_reconf} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_en_lvds_ports} {Disabled}
|
||||
set_instance_parameter_value iopll_0 {gui_en_periphery_ports} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_en_phout_ports} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_en_reconf} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_enable_cascade_in} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_enable_cascade_out} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_enable_mif_dps} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_enable_output_counter_cascading} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_enable_permit_cal} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_enable_upstream_out_clk} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_existing_mif_file_path} {~/pll.mif}
|
||||
set_instance_parameter_value iopll_0 {gui_extclkout_0_source} {C0}
|
||||
set_instance_parameter_value iopll_0 {gui_extclkout_1_source} {C0}
|
||||
set_instance_parameter_value iopll_0 {gui_extclkout_source} {C0}
|
||||
set_instance_parameter_value iopll_0 {gui_feedback_clock} {Global Clock}
|
||||
set_instance_parameter_value iopll_0 {gui_fix_vco_frequency} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_fixed_vco_frequency} {600.0}
|
||||
set_instance_parameter_value iopll_0 {gui_fixed_vco_frequency_ps} {1667.0}
|
||||
set_instance_parameter_value iopll_0 {gui_frac_multiply_factor} {1.0}
|
||||
set_instance_parameter_value iopll_0 {gui_fractional_cout} {32}
|
||||
set_instance_parameter_value iopll_0 {gui_include_iossm} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_location_type} {I/O Bank}
|
||||
set_instance_parameter_value iopll_0 {gui_lock_setting} {Low Lock Time}
|
||||
set_instance_parameter_value iopll_0 {gui_mif_config_name} {unnamed}
|
||||
set_instance_parameter_value iopll_0 {gui_mif_gen_options} {Generate New MIF File}
|
||||
set_instance_parameter_value iopll_0 {gui_multiply_factor} {25}
|
||||
set_instance_parameter_value iopll_0 {gui_new_mif_file_path} {~/pll.mif}
|
||||
set_instance_parameter_value iopll_0 {gui_number_of_clocks} {5}
|
||||
set_instance_parameter_value iopll_0 {gui_operation_mode} {direct}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency0} {200.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency1} {125.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency10} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency11} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency12} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency13} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency14} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency15} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency16} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency17} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency2} {200.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency3} {125.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency4} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency5} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency6} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency7} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency8} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency9} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps0} {5000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps1} {8000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps10} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps11} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps12} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps13} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps14} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps15} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps16} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps17} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps2} {5000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps3} {8000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps4} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps5} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps6} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps7} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps8} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps9} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_parameter_table_hex_file} {seq_params_sim.hex}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift0} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift1} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift10} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift11} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift12} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift13} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift14} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift15} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift16} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift17} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift2} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift3} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift4} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift5} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift6} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift7} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift8} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift9} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg0} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg1} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg10} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg11} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg12} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg13} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg14} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg15} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg16} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg17} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg2} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg3} {90.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg4} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg5} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg6} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg7} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg8} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg9} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phout_division} {1}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_auto_reset} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_bandwidth_preset} {Medium}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_cal_done} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_cascading_mode} {adjpllin}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_freqcal_en} {1}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_freqcal_req_flag} {1}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_m_cnt_in_src} {c_m_cnt_in_src_ph_mux_clk}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_mode} {Integer-N PLL}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_tclk_mux_en} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_tclk_sel} {pll_tclk_m_src}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_type} {S10_Simple}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_vco_freq_band_0} {pll_freq_clk0_band18}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_vco_freq_band_1} {pll_freq_clk1_band18}
|
||||
set_instance_parameter_value iopll_0 {gui_prot_mode} {UNUSED}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units0} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units1} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units10} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units11} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units12} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units13} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units14} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units15} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units16} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units17} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units2} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units3} {degrees}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units4} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units5} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units6} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units7} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units8} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units9} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_refclk1_frequency} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_refclk_might_change} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_refclk_switch} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_reference_clock_frequency} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_reference_clock_frequency_ps} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_simulation_type} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_skip_sdc_generation} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_switchover_delay} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_switchover_mode} {Automatic Switchover}
|
||||
set_instance_parameter_value iopll_0 {gui_use_NDFB_modes} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_use_coreclk} {1}
|
||||
set_instance_parameter_value iopll_0 {gui_use_locked} {1}
|
||||
set_instance_parameter_value iopll_0 {gui_use_logical} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_user_base_address} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_usr_device_speed_grade} {1}
|
||||
set_instance_parameter_value iopll_0 {gui_vco_frequency} {1250.0}
|
||||
set_instance_parameter_value iopll_0 {hp_qsys_scripting_mode} {0}
|
||||
set_instance_parameter_value iopll_0 {system_info_device_iobank_rev} {}
|
||||
set_instance_property iopll_0 AUTO_EXPORT true
|
||||
|
||||
# add wirelevel expressions
|
||||
|
||||
# preserve ports for debug
|
||||
|
||||
# add the exports
|
||||
set_interface_property refclk EXPORT_OF iopll_0.refclk
|
||||
set_interface_property locked EXPORT_OF iopll_0.locked
|
||||
set_interface_property reset EXPORT_OF iopll_0.reset
|
||||
set_interface_property outclk0 EXPORT_OF iopll_0.outclk0
|
||||
set_interface_property outclk1 EXPORT_OF iopll_0.outclk1
|
||||
set_interface_property outclk2 EXPORT_OF iopll_0.outclk2
|
||||
set_interface_property outclk3 EXPORT_OF iopll_0.outclk3
|
||||
set_interface_property outclk4 EXPORT_OF iopll_0.outclk4
|
||||
|
||||
# set values for exposed HDL parameters
|
||||
|
||||
# set the the module properties
|
||||
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
|
||||
<bonusData>
|
||||
<element __value="iopll_0">
|
||||
<datum __value="_sortIndex" value="0" type="int" />
|
||||
</element>
|
||||
</bonusData>
|
||||
}
|
||||
set_module_property FILE {io_pll.ip}
|
||||
set_module_property GENERATION_ID {0x00000000}
|
||||
set_module_property NAME {io_pll}
|
||||
|
||||
# save the system
|
||||
sync_sysinfo_parameters
|
||||
save_system io_pll
|
||||
}
|
||||
|
||||
proc do_set_exported_interface_sysinfo_parameters {} {
|
||||
}
|
||||
|
||||
# create all the systems, from bottom up
|
||||
do_create_io_pll
|
||||
|
||||
# set system info parameters on exported interface, from bottom up
|
||||
do_set_exported_interface_sysinfo_parameters
|
||||
75
corev_apu/altera/ip/iobuf.tcl
Normal file
75
corev_apu/altera/ip/iobuf.tcl
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
# Quartus Pro License required to use this file
|
||||
package require -exact qsys 24.1
|
||||
|
||||
# create the system "iobuf"
|
||||
proc do_create_iobuf {} {
|
||||
# create the system
|
||||
create_system iobuf
|
||||
set_project_property BOARD {default}
|
||||
set_project_property DEVICE {AGFB014R24B2E2V}
|
||||
set_project_property DEVICE_FAMILY {Agilex 7}
|
||||
set_project_property HIDE_FROM_IP_CATALOG {true}
|
||||
set_use_testbench_naming_pattern 0 {}
|
||||
|
||||
# add HDL parameters
|
||||
|
||||
# add the components
|
||||
add_instance gpio_0 altera_gpio 22.1.0
|
||||
set_instance_parameter_value gpio_0 {EXT_DRIVER_PARAM} {0}
|
||||
set_instance_parameter_value gpio_0 {GENERATE_SDC_FILE} {0}
|
||||
set_instance_parameter_value gpio_0 {IP_MIGRATE_PORT_MAP_FILE} {altddio_bidir_port_map.csv}
|
||||
set_instance_parameter_value gpio_0 {PIN_TYPE_GUI} {Bidir}
|
||||
set_instance_parameter_value gpio_0 {SIZE} {1}
|
||||
set_instance_parameter_value gpio_0 {gui_areset_mode} {None}
|
||||
set_instance_parameter_value gpio_0 {gui_bus_hold} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_ddio_with_delay} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_diff_buff} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_enable_cke} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_enable_migratable_port_names} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_enable_termination_ports} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_hr_logic} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_io_reg_mode} {none}
|
||||
set_instance_parameter_value gpio_0 {gui_open_drain} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_pseudo_diff} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_separate_io_clks} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_sreset_mode} {None}
|
||||
set_instance_parameter_value gpio_0 {gui_use_oe} {0}
|
||||
set_instance_property gpio_0 AUTO_EXPORT true
|
||||
|
||||
# add wirelevel expressions
|
||||
|
||||
# preserve ports for debug
|
||||
|
||||
# add the exports
|
||||
set_interface_property dout EXPORT_OF gpio_0.dout
|
||||
set_interface_property din EXPORT_OF gpio_0.din
|
||||
set_interface_property oe EXPORT_OF gpio_0.oe
|
||||
set_interface_property pad_io EXPORT_OF gpio_0.pad_io
|
||||
|
||||
# set values for exposed HDL parameters
|
||||
|
||||
# set the the module properties
|
||||
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
|
||||
<bonusData>
|
||||
<element __value="gpio_0">
|
||||
<datum __value="_sortIndex" value="0" type="int" />
|
||||
</element>
|
||||
</bonusData>
|
||||
}
|
||||
set_module_property FILE {iobuf.ip}
|
||||
set_module_property GENERATION_ID {0x00000000}
|
||||
set_module_property NAME {iobuf}
|
||||
|
||||
# save the system
|
||||
sync_sysinfo_parameters
|
||||
save_system iobuf
|
||||
}
|
||||
|
||||
proc do_set_exported_interface_sysinfo_parameters {} {
|
||||
}
|
||||
|
||||
# create all the systems, from bottom up
|
||||
do_create_iobuf
|
||||
|
||||
# set system info parameters on exported interface, from bottom up
|
||||
do_set_exported_interface_sysinfo_parameters
|
||||
74
corev_apu/altera/ip/oddr_intel.tcl
Normal file
74
corev_apu/altera/ip/oddr_intel.tcl
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
# Quartus Pro License required to use this file
|
||||
package require -exact qsys 24.1
|
||||
|
||||
# create the system "oddr_intel"
|
||||
proc do_create_oddr_intel {} {
|
||||
# create the system
|
||||
create_system oddr_intel
|
||||
set_project_property BOARD {default}
|
||||
set_project_property DEVICE {AGFB014R24B2E2V}
|
||||
set_project_property DEVICE_FAMILY {Agilex 7}
|
||||
set_project_property HIDE_FROM_IP_CATALOG {true}
|
||||
set_use_testbench_naming_pattern 0 {}
|
||||
|
||||
# add HDL parameters
|
||||
|
||||
# add the components
|
||||
add_instance gpio_0 altera_gpio 22.1.0
|
||||
set_instance_parameter_value gpio_0 {EXT_DRIVER_PARAM} {0}
|
||||
set_instance_parameter_value gpio_0 {GENERATE_SDC_FILE} {0}
|
||||
set_instance_parameter_value gpio_0 {IP_MIGRATE_PORT_MAP_FILE} {altddio_bidir_port_map.csv}
|
||||
set_instance_parameter_value gpio_0 {PIN_TYPE_GUI} {Output}
|
||||
set_instance_parameter_value gpio_0 {SIZE} {1}
|
||||
set_instance_parameter_value gpio_0 {gui_areset_mode} {None}
|
||||
set_instance_parameter_value gpio_0 {gui_bus_hold} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_ddio_with_delay} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_diff_buff} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_enable_cke} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_enable_migratable_port_names} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_enable_termination_ports} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_hr_logic} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_io_reg_mode} {DDIO}
|
||||
set_instance_parameter_value gpio_0 {gui_open_drain} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_pseudo_diff} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_separate_io_clks} {0}
|
||||
set_instance_parameter_value gpio_0 {gui_sreset_mode} {None}
|
||||
set_instance_parameter_value gpio_0 {gui_use_oe} {0}
|
||||
set_instance_property gpio_0 AUTO_EXPORT true
|
||||
|
||||
# add wirelevel expressions
|
||||
|
||||
# preserve ports for debug
|
||||
|
||||
# add the exports
|
||||
set_interface_property ck EXPORT_OF gpio_0.ck
|
||||
set_interface_property din EXPORT_OF gpio_0.din
|
||||
set_interface_property pad_out EXPORT_OF gpio_0.pad_out
|
||||
|
||||
# set values for exposed HDL parameters
|
||||
|
||||
# set the the module properties
|
||||
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
|
||||
<bonusData>
|
||||
<element __value="gpio_0">
|
||||
<datum __value="_sortIndex" value="0" type="int" />
|
||||
</element>
|
||||
</bonusData>
|
||||
}
|
||||
set_module_property FILE {oddr_intel.ip}
|
||||
set_module_property GENERATION_ID {0x00000000}
|
||||
set_module_property NAME {oddr_intel}
|
||||
|
||||
# save the system
|
||||
sync_sysinfo_parameters
|
||||
save_system oddr_intel
|
||||
}
|
||||
|
||||
proc do_set_exported_interface_sysinfo_parameters {} {
|
||||
}
|
||||
|
||||
# create all the systems, from bottom up
|
||||
do_create_oddr_intel
|
||||
|
||||
# set system info parameters on exported interface, from bottom up
|
||||
do_set_exported_interface_sysinfo_parameters
|
||||
72
corev_apu/altera/ip/test_mm_ccb_0.tcl
Normal file
72
corev_apu/altera/ip/test_mm_ccb_0.tcl
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
# Quartus Pro License required to use this file
|
||||
package require -exact qsys 24.1
|
||||
|
||||
# create the system "test_mm_ccb_0"
|
||||
proc do_create_test_mm_ccb_0 {} {
|
||||
# create the system
|
||||
create_system test_mm_ccb_0
|
||||
set_project_property BOARD {default}
|
||||
set_project_property DEVICE {AGFB014R24B2E2V}
|
||||
set_project_property DEVICE_FAMILY {Agilex 7}
|
||||
set_project_property HIDE_FROM_IP_CATALOG {false}
|
||||
set_use_testbench_naming_pattern 0 {}
|
||||
|
||||
# add HDL parameters
|
||||
|
||||
# add the components
|
||||
add_instance mm_ccb_0 mm_ccb 19.2.1
|
||||
set_instance_parameter_value mm_ccb_0 {ADDRESS_UNITS} {SYMBOLS}
|
||||
set_instance_parameter_value mm_ccb_0 {ADDRESS_WIDTH} {27}
|
||||
set_instance_parameter_value mm_ccb_0 {COMMAND_FIFO_DEPTH} {256}
|
||||
set_instance_parameter_value mm_ccb_0 {DATA_WIDTH} {512}
|
||||
set_instance_parameter_value mm_ccb_0 {MASTER_SYNC_DEPTH} {2}
|
||||
set_instance_parameter_value mm_ccb_0 {MAX_BURST_SIZE} {128}
|
||||
set_instance_parameter_value mm_ccb_0 {RESPONSE_FIFO_DEPTH} {256}
|
||||
set_instance_parameter_value mm_ccb_0 {SLAVE_SYNC_DEPTH} {2}
|
||||
set_instance_parameter_value mm_ccb_0 {SYMBOL_WIDTH} {8}
|
||||
set_instance_parameter_value mm_ccb_0 {SYNC_RESET} {1}
|
||||
set_instance_parameter_value mm_ccb_0 {USE_AUTO_ADDRESS_WIDTH} {0}
|
||||
set_instance_property mm_ccb_0 AUTO_EXPORT true
|
||||
|
||||
# add wirelevel expressions
|
||||
|
||||
# preserve ports for debug
|
||||
|
||||
# add the exports
|
||||
set_interface_property m0_clk EXPORT_OF mm_ccb_0.m0_clk
|
||||
set_interface_property m0_reset EXPORT_OF mm_ccb_0.m0_reset
|
||||
set_interface_property s0_clk EXPORT_OF mm_ccb_0.s0_clk
|
||||
set_interface_property s0_reset EXPORT_OF mm_ccb_0.s0_reset
|
||||
set_interface_property s0 EXPORT_OF mm_ccb_0.s0
|
||||
set_interface_property m0 EXPORT_OF mm_ccb_0.m0
|
||||
|
||||
# set values for exposed HDL parameters
|
||||
|
||||
# set the the module properties
|
||||
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
|
||||
<bonusData>
|
||||
<element __value="mm_ccb_0">
|
||||
<datum __value="_sortIndex" value="0" type="int" />
|
||||
</element>
|
||||
</bonusData>
|
||||
}
|
||||
set_module_property FILE {ip/test_mm_ccb_0.ip}
|
||||
set_module_property GENERATION_ID {0x00000000}
|
||||
set_module_property NAME {test_mm_ccb_0}
|
||||
|
||||
# save the system
|
||||
sync_sysinfo_parameters
|
||||
save_system test_mm_ccb_0
|
||||
}
|
||||
|
||||
proc do_set_exported_interface_sysinfo_parameters {} {
|
||||
load_system test_mm_ccb_0.ip
|
||||
set_exported_interface_sysinfo_parameter_value m0 address_width {10}
|
||||
save_system test_mm_ccb_0.ip
|
||||
}
|
||||
|
||||
# create all the systems, from bottom up
|
||||
do_create_test_mm_ccb_0
|
||||
|
||||
# set system info parameters on exported interface, from bottom up
|
||||
do_set_exported_interface_sysinfo_parameters
|
||||
58
corev_apu/altera/ip/vJTAG.tcl
Normal file
58
corev_apu/altera/ip/vJTAG.tcl
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
# Quartus Pro License required to use this file
|
||||
package require -exact qsys 24.1
|
||||
|
||||
# create the system "vJTAG"
|
||||
proc do_create_vJTAG {} {
|
||||
# create the system
|
||||
create_system vJTAG
|
||||
set_project_property BOARD {default}
|
||||
set_project_property DEVICE {AGFB014R24B2E2V}
|
||||
set_project_property DEVICE_FAMILY {Agilex 7}
|
||||
set_project_property HIDE_FROM_IP_CATALOG {true}
|
||||
set_use_testbench_naming_pattern 0 {}
|
||||
|
||||
# add HDL parameters
|
||||
|
||||
# add the components
|
||||
add_instance virtual_jtag_0 altera_virtual_jtag 19.2.1
|
||||
set_instance_parameter_value virtual_jtag_0 {CREATE_PRIMITIVE_JTAG_STATE_SIGNAL_PORTS} {1}
|
||||
set_instance_parameter_value virtual_jtag_0 {gui_use_auto_index} {1}
|
||||
set_instance_parameter_value virtual_jtag_0 {sld_instance_index} {0}
|
||||
set_instance_parameter_value virtual_jtag_0 {sld_ir_width} {10}
|
||||
set_instance_property virtual_jtag_0 AUTO_EXPORT true
|
||||
|
||||
# add wirelevel expressions
|
||||
|
||||
# preserve ports for debug
|
||||
|
||||
# add the exports
|
||||
set_interface_property jtag EXPORT_OF virtual_jtag_0.jtag
|
||||
set_interface_property tck EXPORT_OF virtual_jtag_0.tck
|
||||
|
||||
# set values for exposed HDL parameters
|
||||
|
||||
# set the the module properties
|
||||
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
|
||||
<bonusData>
|
||||
<element __value="virtual_jtag_0">
|
||||
<datum __value="_sortIndex" value="0" type="int" />
|
||||
</element>
|
||||
</bonusData>
|
||||
}
|
||||
set_module_property FILE {vJTAG.ip}
|
||||
set_module_property GENERATION_ID {0x00000000}
|
||||
set_module_property NAME {vJTAG}
|
||||
|
||||
# save the system
|
||||
sync_sysinfo_parameters
|
||||
save_system vJTAG
|
||||
}
|
||||
|
||||
proc do_set_exported_interface_sysinfo_parameters {} {
|
||||
}
|
||||
|
||||
# create all the systems, from bottom up
|
||||
do_create_vJTAG
|
||||
|
||||
# set system info parameters on exported interface, from bottom up
|
||||
do_set_exported_interface_sysinfo_parameters
|
||||
9
corev_apu/altera/ip_files.csv
Normal file
9
corev_apu/altera/ip_files.csv
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
./test_mm_ccb_0.ip
|
||||
./io_pll.ip
|
||||
./iobuf.ip
|
||||
./oddr_intel.ip
|
||||
./iddr_intel.ip
|
||||
./ed_synth_emif_fm_0.ip
|
||||
./emif_cal.ip
|
||||
./vJTAG.ip
|
||||
./cva6_intel_jtag_uart_0.ip
|
||||
|
139
corev_apu/altera/loc_constraints.csv
Normal file
139
corev_apu/altera/loc_constraints.csv
Normal file
|
|
@ -0,0 +1,139 @@
|
|||
PIN_A24 -to cpu_resetn
|
||||
PIN_CU24 -to pll_ref_clk_p
|
||||
PIN_C30 -to led[0]
|
||||
PIN_A30 -to led[1]
|
||||
PIN_D31 -to led[2]
|
||||
PIN_B31 -to led[3]
|
||||
PIN_L40 -to clk_ddr4_ch0_p
|
||||
PIN_F33 -to ddr4_dq[0]
|
||||
PIN_H33 -to ddr4_dq[1]
|
||||
PIN_G34 -to ddr4_dq[2]
|
||||
PIN_J34 -to ddr4_dq[3]
|
||||
PIN_J38 -to ddr4_dq[4]
|
||||
PIN_G38 -to ddr4_dq[5]
|
||||
PIN_F37 -to ddr4_dq[6]
|
||||
PIN_H37 -to ddr4_dq[7]
|
||||
PIN_B33 -to ddr4_dq[8]
|
||||
PIN_D33 -to ddr4_dq[9]
|
||||
PIN_A34 -to ddr4_dq[10]
|
||||
PIN_C34 -to ddr4_dq[11]
|
||||
PIN_D37 -to ddr4_dq[12]
|
||||
PIN_A38 -to ddr4_dq[13]
|
||||
PIN_B37 -to ddr4_dq[14]
|
||||
PIN_C38 -to ddr4_dq[15]
|
||||
PIN_A40 -to ddr4_dq[16]
|
||||
PIN_C40 -to ddr4_dq[17]
|
||||
PIN_B41 -to ddr4_dq[18]
|
||||
PIN_D41 -to ddr4_dq[19]
|
||||
PIN_D45 -to ddr4_dq[20]
|
||||
PIN_B45 -to ddr4_dq[21]
|
||||
PIN_A44 -to ddr4_dq[22]
|
||||
PIN_C44 -to ddr4_dq[23]
|
||||
PIN_G40 -to ddr4_dq[24]
|
||||
PIN_J40 -to ddr4_dq[25]
|
||||
PIN_F41 -to ddr4_dq[26]
|
||||
PIN_H41 -to ddr4_dq[27]
|
||||
PIN_J44 -to ddr4_dq[28]
|
||||
PIN_H45 -to ddr4_dq[29]
|
||||
PIN_G44 -to ddr4_dq[30]
|
||||
PIN_F45 -to ddr4_dq[31]
|
||||
PIN_G48 -to ddr4_dq[32]
|
||||
PIN_F47 -to ddr4_dq[33]
|
||||
PIN_J48 -to ddr4_dq[34]
|
||||
PIN_H47 -to ddr4_dq[35]
|
||||
PIN_F51 -to ddr4_dq[36]
|
||||
PIN_H51 -to ddr4_dq[37]
|
||||
PIN_G52 -to ddr4_dq[38]
|
||||
PIN_J52 -to ddr4_dq[39]
|
||||
PIN_F55 -to ddr4_dq[40]
|
||||
PIN_G54 -to ddr4_dq[41]
|
||||
PIN_H55 -to ddr4_dq[42]
|
||||
PIN_J54 -to ddr4_dq[43]
|
||||
PIN_J58 -to ddr4_dq[44]
|
||||
PIN_F59 -to ddr4_dq[45]
|
||||
PIN_G58 -to ddr4_dq[46]
|
||||
PIN_H59 -to ddr4_dq[47]
|
||||
PIN_B55 -to ddr4_dq[48]
|
||||
PIN_A54 -to ddr4_dq[49]
|
||||
PIN_D55 -to ddr4_dq[50]
|
||||
PIN_C54 -to ddr4_dq[51]
|
||||
PIN_D59 -to ddr4_dq[52]
|
||||
PIN_C58 -to ddr4_dq[53]
|
||||
PIN_F61 -to ddr4_dq[54]
|
||||
PIN_H61 -to ddr4_dq[55]
|
||||
PIN_V55 -to ddr4_dq[56]
|
||||
PIN_T55 -to ddr4_dq[57]
|
||||
PIN_W54 -to ddr4_dq[58]
|
||||
PIN_U54 -to ddr4_dq[59]
|
||||
PIN_W58 -to ddr4_dq[60]
|
||||
PIN_T59 -to ddr4_dq[61]
|
||||
PIN_U58 -to ddr4_dq[62]
|
||||
PIN_V59 -to ddr4_dq[63]
|
||||
PIN_A48 -to ddr4_dq[64]
|
||||
PIN_B47 -to ddr4_dq[65]
|
||||
PIN_C48 -to ddr4_dq[66]
|
||||
PIN_D47 -to ddr4_dq[67]
|
||||
PIN_C52 -to ddr4_dq[68]
|
||||
PIN_D51 -to ddr4_dq[69]
|
||||
PIN_B51 -to ddr4_dq[70]
|
||||
PIN_A52 -to ddr4_dq[71]
|
||||
PIN_G36 -to ddr4_dbi_n[0]
|
||||
PIN_A36 -to ddr4_dbi_n[1]
|
||||
PIN_B43 -to ddr4_dbi_n[2]
|
||||
PIN_F43 -to ddr4_dbi_n[3]
|
||||
PIN_G50 -to ddr4_dbi_n[4]
|
||||
PIN_F57 -to ddr4_dbi_n[5]
|
||||
PIN_B57 -to ddr4_dbi_n[6]
|
||||
PIN_T57 -to ddr4_dbi_n[7]
|
||||
PIN_A50 -to ddr4_dbi_n[8]
|
||||
PIN_H35 -to ddr4_dqs_n[0]
|
||||
PIN_F35 -to ddr4_dqs_p[0]
|
||||
PIN_D35 -to ddr4_dqs_n[1]
|
||||
PIN_B35 -to ddr4_dqs_p[1]
|
||||
PIN_C42 -to ddr4_dqs_n[2]
|
||||
PIN_A42 -to ddr4_dqs_p[2]
|
||||
PIN_J42 -to ddr4_dqs_n[3]
|
||||
PIN_G42 -to ddr4_dqs_p[3]
|
||||
PIN_H49 -to ddr4_dqs_n[4]
|
||||
PIN_F49 -to ddr4_dqs_p[4]
|
||||
PIN_J56 -to ddr4_dqs_n[5]
|
||||
PIN_G56 -to ddr4_dqs_p[5]
|
||||
PIN_C56 -to ddr4_dqs_n[6]
|
||||
PIN_A56 -to ddr4_dqs_p[6]
|
||||
PIN_W56 -to ddr4_dqs_n[7]
|
||||
PIN_U56 -to ddr4_dqs_p[7]
|
||||
PIN_D49 -to ddr4_dqs_n[8]
|
||||
PIN_B49 -to ddr4_dqs_p[8]
|
||||
PIN_P37 -to ddr4_ck_n[0]
|
||||
PIN_M37 -to ddr4_ck_p[0]
|
||||
PIN_P43 -to ddr4_a[16]
|
||||
PIN_M43 -to ddr4_a[15]
|
||||
PIN_N42 -to ddr4_a[14]
|
||||
PIN_L42 -to ddr4_a[13]
|
||||
PIN_P41 -to ddr4_a[12]
|
||||
PIN_W38 -to ddr4_a[11]
|
||||
PIN_U38 -to ddr4_a[10]
|
||||
PIN_V37 -to ddr4_a[9]
|
||||
PIN_T37 -to ddr4_a[8]
|
||||
PIN_W36 -to ddr4_a[7]
|
||||
PIN_U36 -to ddr4_a[6]
|
||||
PIN_V35 -to ddr4_a[5]
|
||||
PIN_T35 -to ddr4_a[4]
|
||||
PIN_W34 -to ddr4_a[3]
|
||||
PIN_U34 -to ddr4_a[2]
|
||||
PIN_V33 -to ddr4_a[1]
|
||||
PIN_T33 -to ddr4_a[0]
|
||||
PIN_L34 -to ddr4_cs_n[0]
|
||||
PIN_P45 -to ddr4_bg[0]
|
||||
PIN_M33 -to ddr4_bg[1]
|
||||
PIN_N44 -to ddr4_ba[0]
|
||||
PIN_M45 -to ddr4_ba[1]
|
||||
PIN_L36 -to ddr4_cke[0]
|
||||
PIN_M35 -to ddr4_odt[0]
|
||||
PIN_U44 -to ddr4_alert_n
|
||||
PIN_M41 -to oct_rzqin
|
||||
PIN_N38 -to ddr4_par
|
||||
PIN_N34 -to ddr4_act_n
|
||||
PIN_P33 -to ddr4_reset_n
|
||||
PIN_AA6 -to tx
|
||||
PIN_F1 -to rx
|
||||
|
9
corev_apu/altera/search_paths.csv
Normal file
9
corev_apu/altera/search_paths.csv
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
"../fpga/src/apb/include"
|
||||
"../fpga/src"
|
||||
"../fpga/"
|
||||
"../../vendor/pulp-platform/common_cells/include"
|
||||
"../../vendor/pulp-platform/axi/include"
|
||||
"../../core/cache_subsystem/hpdcache/rtl/include"
|
||||
"../../core/include"
|
||||
"../register_interface/include"
|
||||
"../"
|
||||
|
45
corev_apu/altera/settings.csv
Normal file
45
corev_apu/altera/settings.csv
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
TOP_LEVEL_ENTITY cva6_altera
|
||||
ORIGINAL_QUARTUS_VERSION 24.1.0
|
||||
PROJECT_CREATION_TIME_DATE "14:07:44 JUNE 03, 2024"
|
||||
LAST_QUARTUS_VERSION "24.1.0 Pro Edition"
|
||||
PROJECT_OUTPUT_DIRECTORY output_files
|
||||
MIN_CORE_JUNCTION_TEMP 0
|
||||
MAX_CORE_JUNCTION_TEMP 100
|
||||
DEVICE AGFB014R24B2E2V
|
||||
FAMILY "Agilex 7"
|
||||
ERROR_CHECK_FREQUENCY_DIVISOR 256
|
||||
EDA_SIMULATION_TOOL "QuestaSim (Verilog)"
|
||||
EDA_TIME_SCALE "1 ps" -section_id eda_simulation
|
||||
EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
|
||||
STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
|
||||
USE_CONFIGURATION_DEVICE ON
|
||||
GENERATE_PR_RBF_FILE ON
|
||||
ENABLE_ED_CRC_CHECK ON
|
||||
MINIMUM_SEU_INTERVAL 0
|
||||
PWRMGT_SLAVE_DEVICE_TYPE ED8401
|
||||
PWRMGT_SLAVE_DEVICE0_ADDRESS 47
|
||||
PWRMGT_SLAVE_DEVICE1_ADDRESS 00
|
||||
PWRMGT_SLAVE_DEVICE2_ADDRESS 00
|
||||
ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ
|
||||
USE_PWRMGT_SCL SDM_IO14
|
||||
USE_PWRMGT_SDA SDM_IO11
|
||||
USE_CONF_DONE SDM_IO16
|
||||
AUTO_RESTART_CONFIGURATION OFF
|
||||
USE_CVP_CONFDONE SDM_IO10
|
||||
DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ
|
||||
PWRMGT_PAGE_COMMAND_ENABLE OFF
|
||||
PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
|
||||
PWRMGT_LINEAR_FORMAT_N "-13"
|
||||
POWER_APPLY_THERMAL_MARGIN ADDITIONAL
|
||||
USE_INIT_DONE SDM_IO0
|
||||
BOARD default
|
||||
OPTIMIZATION_MODE "OPTIMIZE NETLIST FOR ROUTABILITY"
|
||||
ALM_REGISTER_PACKING_EFFORT "LOW"
|
||||
ADVANCED_PHYSICAL_SYNTHESIS "ON"
|
||||
PLACEMENT_EFFORT_MULTIPLIER 50
|
||||
ROUTER_TIMING_OPTIMIZATION_LEVEL "MAXIMUM"
|
||||
FINAL_PLACEMENT_OPTIMIZATION "AUTOMATICALLY"
|
||||
FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS
|
||||
GLOBAL_PLACEMENT_EFFORT "MAXIMUM EFFORT"
|
||||
QII_AUTO_PACKED_REGISTERS SPARSE
|
||||
OPTIMIZATION_TECHNIQUE SPEED
|
||||
|
Can't render this file because it contains an unexpected character in line 3 and column 28.
|
21
corev_apu/fpga/src/agilex7.svh
Normal file
21
corev_apu/fpga/src/agilex7.svh
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
// Copyright 2018 ETH Zurich and University of Bologna.
|
||||
// Copyright and related rights are licensed under the Solderpad Hardware
|
||||
// License, Version 0.51 (the "License"); you may not use this file except in
|
||||
// compliance with the License. You may obtain a copy of the License at
|
||||
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
|
||||
// or agreed to in writing, software, hardware and materials distributed under
|
||||
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
|
||||
// specific language governing permissions and limitations under the License.
|
||||
|
||||
// Description: Set global FPGA degines
|
||||
// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
|
||||
|
||||
`define AGILEX7
|
||||
// include KINTEX7 specific code (relevant for KC705, GENESYSII,...)
|
||||
`define KINTEX7
|
||||
|
||||
`define ARIANE_DATA_WIDTH 64
|
||||
|
||||
// Instantiate protocl checker
|
||||
// `define PROTOCOL_CHECKER
|
||||
|
|
@ -20,7 +20,7 @@ endif
|
|||
CC = $(RISCV)/bin/${CROSSCOMPILE}gcc
|
||||
OBJCOPY = $(RISCV)/bin/$(CROSSCOMPILE)objcopy
|
||||
SED = sed
|
||||
PLATFORM_DEFINES = -DCLOCK_FREQUENCY=$(CLOCK_FREQUENCY) -DUART_BITRATE=$(UART_BITRATE)
|
||||
PLATFORM_DEFINES = -DCLOCK_FREQUENCY=$(CLOCK_FREQUENCY) -DUART_BITRATE=$(UART_BITRATE) -D$(PLATFORM)
|
||||
|
||||
ifeq ($(XLEN), 64)
|
||||
CFLAGS = $(PLATFORM_DEFINES) -Os -ggdb -march=rv64im_zicsr -mabi=lp64 -Wall -mcmodel=medany -mexplicit-relocs -ffreestanding
|
||||
|
|
@ -56,6 +56,7 @@ endif
|
|||
$(MAIN): $(DTB) $(OBJS_C) $(OBJS_S) linker.lds
|
||||
$(CC) $(CFLAGS) $(LDFLAGS) $(INCLUDES) -Tlinker.lds $(OBJS_S) $(OBJS_C) -o $(MAIN)
|
||||
@echo "LD >= $(MAIN)"
|
||||
@echo "BOOTROM PLATFORM IS : $(PLATFORM)"
|
||||
|
||||
%.img: %.bin
|
||||
dd if=$< of=$@ bs=128
|
||||
|
|
|
|||
|
|
@ -48,7 +48,9 @@ int main()
|
|||
uint8_t uart_res = 0;
|
||||
uintptr_t start;
|
||||
|
||||
init_uart(CLOCK_FREQUENCY, UART_BITRATE);
|
||||
#ifndef PLAT_AGILEX
|
||||
init_uart(CLOCK_FREQUENCY, UART_BITRATE); //not needed in intel setup as UART IP is already configured via HW
|
||||
#endif
|
||||
print_uart("Hello World!\r\n");
|
||||
|
||||
// See if we should enter update mode
|
||||
|
|
@ -70,9 +72,12 @@ int main()
|
|||
res = update((uint8_t *)0x80000000UL);
|
||||
} else {
|
||||
print_uart(" booting!\r\n");
|
||||
res = gpt_find_boot_partition((uint8_t *)0x80000000UL, 2 * 16384);
|
||||
#ifndef PLAT_AGILEX
|
||||
res = gpt_find_boot_partition((uint8_t *)0x80000000UL, 2 * 16384); // linux boot not yet supported for altera
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifndef PLAT_AGILEX // linux boot not yet supported for altera
|
||||
if (res == 0)
|
||||
{
|
||||
// jump to the address
|
||||
|
|
@ -81,6 +86,7 @@ int main()
|
|||
"la a1, _dtb;"
|
||||
"jr s0");
|
||||
}
|
||||
#endif
|
||||
|
||||
while (1)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -20,15 +20,27 @@ int is_transmit_empty()
|
|||
return read_reg_u8(UART_LINE_STATUS) & 0x20;
|
||||
}
|
||||
|
||||
char is_transmit_empty_altera()
|
||||
{
|
||||
return read_reg_u8(UART_THR+6);
|
||||
}
|
||||
|
||||
int is_receive_empty()
|
||||
{
|
||||
return !(read_reg_u8(UART_LINE_STATUS) & 0x1);
|
||||
#ifndef PLAT_AGILEX
|
||||
return !(read_reg_u8(UART_LINE_STATUS) & 0x1);
|
||||
#else
|
||||
return !(read_reg_u8(UART_THR+1) & 0x8);
|
||||
#endif
|
||||
}
|
||||
|
||||
void write_serial(char a)
|
||||
{
|
||||
while (is_transmit_empty() == 0) {};
|
||||
|
||||
#ifndef PLAT_AGILEX
|
||||
while (is_transmit_empty() == 0) {};
|
||||
#else
|
||||
while (is_transmit_empty_altera() < 8) {};
|
||||
#endif
|
||||
write_reg_u8(UART_THR, a);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue