github-mirrors/cva6
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva6.git synced 2025-04-23 21:57:11 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 7

🐛 Minor fixes to hart enumeration logic

Browse source
This commit is contained in:
Florian Zaruba 2018-07-10 10:29:47 -07:00
parent 527e944577
commit eb95474ace
No known key found for this signature in database
GPG key ID: E742FFE8EC38A792
4 changed files with 24 additions and 20 deletions
Download patch file Download diff file Expand all files Collapse all files

2
Makefile
View file

@ -177,7 +177,7 @@ verilate:
$(verilator) $(ariane_pkg) $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) $(wildcard src/axi_slice/*.sv) \
$(filter-out src/debug/dm_pkg.sv, $(wildcard src/debug/*.sv)) src/util/generic_fifo.sv tb/common/SimDTM.v \
src/util/cluster_clock_gating.sv src/util/behav_sram.sv src/axi_mem_if/src/axi2mem.sv tb/agents/axi_if/axi_if.sv \
+incdir+src/axi_node --vpi \
+incdir+src/axi_node --vpi --trace-structs \
--unroll-count 256 -Wno-fatal -Werror-PINMISSING -Werror-IMPLICIT -LDFLAGS "-lfesvr" -CFLAGS "-std=c++11" -Wall --cc --trace \
-Wno-PINCONNECTEMPTY -Wno-DECLFILENAME -Wno-UNOPTFLAT -Wno-UNUSED \
$(list_incdir) --top-module ariane_wrapped --exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc

2
include/ariane_pkg.sv
View file

@ -49,7 +49,7 @@ package ariane_pkg;
localparam REG_ADDR_SIZE = 6;
// static debug hartinfo
// for the moment nothing of this is implemented
parameter dm::hartinfo_t DebugHartInfo = '{zero1: '0, nscratch: 1, zero0: '0, dataaccess: '0, datasize: '0, dataaddr: '0};
parameter dm::hartinfo_t DebugHartInfo = '{zero1: '0, nscratch: 1, zero0: '0, dataaccess: 1'b1, datasize: '0, dataaddr: '0};
// ---------------
// Fetch Stage
// ---------------

28
src/debug/dm_csrs.sv
View file

@ -54,6 +54,8 @@ module dm_csrs #(
);
// the amount of bits we need to represent all harts
localparam HartSelLen = (NrHarts == 1) ? 1 : $clog2(NrHarts);
dm::dtm_op_t dtm_op;
assign dtm_op = dm::dtm_op_t'(dmi_req_bits_op_i);
logic resp_queue_full;
logic resp_queue_empty;
@ -66,6 +68,7 @@ module dm_csrs #(
logic [31:0] haltsum0, haltsum1, haltsum2, haltsum3;
for (genvar i = 0; i < 32; i++) begin
assign haltsum0[i] = halted_i[i];
// TODO(zarubaf) Implement correct haltsum logic
// assign haltsum0[i] = halted_i[hartsel[19:5]];
// assign haltsum1[i] = (NrHarts > 32) ? &halted_i[hartsel[19:10] +: 32] : 1'b0;
// assign haltsum2[i] = (NrHarts > 1024) ? &halted_i[hartsel[19:15] +: 1024] : 1'b0;
@ -110,6 +113,8 @@ module dm_csrs #(
dmstatus.allunavail = unavailable_i[hartsel[HartSelLen-1:0]];
dmstatus.anyunavail = unavailable_i[hartsel[HartSelLen-1:0]];
// as soon as we are out of the legal Hart region tell the debugger
// that there are only non-existent harts
dmstatus.allnonexistent = (hartsel > NrHarts - 1) ? 1'b1 : 1'b0;
dmstatus.anynonexistent = (hartsel > NrHarts - 1) ? 1'b1 : 1'b0;
@ -137,17 +142,18 @@ module dm_csrs #(
ackhavereset_o = 'b0;
// read
if (dmi_req_valid_i && dmi_req_bits_op_i == dm::DTM_READ) begin
if (dmi_req_ready_o && dmi_req_valid_i && dtm_op == dm::DTM_READ) begin
unique case (dm::dm_csr_t'({1'b0, dmi_req_bits_addr_i})) inside
[(dm::Data0):(dm::Data0 + dm::DataCount << 2)]: begin
resp_queue_data = data_q[dmi_req_bits_addr_i[4:0]];
[(dm::Data0):(dm::Data0 + dm::DataCount)]: begin
if (dm::DataCount > 0)
resp_queue_data = data_q[dmi_req_bits_addr_i[4:0]];
end
dm::DMControl: resp_queue_data = dmcontrol_q;
dm::DMStatus: resp_queue_data = dmstatus;
dm::Hartinfo: resp_queue_data = hartinfo_i[selected_hart];
dm::AbstractCS: resp_queue_data = abstractcs;
dm::Command: resp_queue_data = command_q;
[(dm::ProgBuf0):(dm::ProgBuf0 + dm::ProgBufSize << 2)]: begin
[(dm::ProgBuf0):(dm::ProgBuf0 + dm::ProgBufSize)]: begin
resp_queue_data = progbuf_q[dmi_req_bits_addr_i[4:0]];
end
dm::HaltSum0: resp_queue_data = haltsum0;
@ -159,11 +165,11 @@ module dm_csrs #(
end
// write
if (dmi_req_valid_i && dmi_req_bits_op_i == dm::DTM_WRITE) begin
if (dmi_req_ready_o && dmi_req_valid_i && dtm_op == dm::DTM_WRITE) begin
unique case (dm::dm_csr_t'({1'b0, dmi_req_bits_addr_i})) inside
[(dm::Data0):(dm::Data0 + dm::DataCount << 2)]: begin
[(dm::Data0):(dm::Data0 + dm::DataCount)]: begin
// attempts to write them while busy is set does not change their value
if (!cmdbusy_i) begin
if (!cmdbusy_i && dm::DataCount > 0) begin
data_d[dmi_req_bits_addr_i[4:0]] = dmi_req_bits_data_i;
end
end
@ -185,7 +191,7 @@ module dm_csrs #(
command_write_o = 1'b1;
command_d = dmi_req_bits_data_i;
end
[dm::ProgBuf0:dm::ProgBuf15]: begin
[(dm::ProgBuf0):(dm::ProgBuf0 + dm::ProgBufSize)]: begin
// attempts to write them while busy is set does not change their value
if (!cmdbusy_i) begin
progbuf_d[dmi_req_bits_addr_i[4:0]] = dmi_req_bits_data_i;
@ -199,19 +205,15 @@ module dm_csrs #(
cmderr_d = cmderror_i[selected_hart];
end
// dmcontrol
// determine how how many harts we actually want to select
// and tie-off (through constant propagation the remaining harts)
{dmcontrol_d.hartselhi, dmcontrol_d.hartsello} = hartsel[19:HartSelLen];
// TODO(zarubaf) we currently do not implement the hartarry mask
dmcontrol_d.hasel = 1'b0;
// we do not support resetting an individual hart
dmcontrol_d.hartreset = 1'b0;
// we only allow 1024 harts
dmcontrol_d.hartselhi = '0;
dmcontrol_d.setresethaltreq = 1'b0;
dmcontrol_d.clrresethaltreq = 1'b0;
dmcontrol_d.zero1 = '0;
dmcontrol_d.zero0 = '0;
// TODO(zarubaf)
dmcontrol_d.ackhavereset = 1'b0;
end

12
src/debug/dm_pkg.sv
View file

@ -68,7 +68,7 @@ package dm;
typedef struct packed {
logic [31:23] zero1;
logic impebreak;
logic [21:0] zero0;
logic [21:20] zero0;
logic allhavereset;
logic anyhavereset;
logic allresumeack;
@ -85,7 +85,7 @@ package dm;
logic authbusy;
logic hasresethaltreq;
logic devtreevalid;
logic version;
logic [3:0] version;
} dmstatus_t;
typedef struct packed {
@ -159,9 +159,11 @@ package dm;
} dcsr_t;
// DTM
localparam logic[1:0] DTM_NOP = 2'h0;
localparam logic[1:0] DTM_READ = 2'h1;
localparam logic[1:0] DTM_WRITE = 2'h2;
typedef enum logic [1:0] {
DTM_NOP = 2'h0,
DTM_READ = 2'h1,
DTM_WRITE = 2'h2
} dtm_op_t;
localparam logic[1:0] DTM_SUCCESS = 2'h0;