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Add sign extend in LSU
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Florian Zaruba
parent
c4edf3de3d
commit
ec4384a95f
2 changed files with 146 additions and 15 deletions
153
lsu.sv
153
lsu.sv
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@ -32,6 +32,7 @@ module lsu #(
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input logic lsu_valid_i, // Input is valid
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input logic [TRANS_ID_BITS-1:0] lsu_trans_id_i, // transaction id, needed for WB
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output logic [TRANS_ID_BITS-1:0] lsu_trans_id_o, // ID of scoreboard entry at which to write back
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output logic [63:0] lsu_result_o,
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output logic lsu_valid_o, // transaction id for which the output is the requested one
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input logic enable_translation_i,
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@ -56,11 +57,20 @@ module lsu #(
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output exception lsu_exception_o // to WB, signal exception status LD/ST exception
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);
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mem_if ptw_if(clk_i);
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// data is misaligned
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logic data_misaligned;
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assign lsu_trans_id_o = lsu_trans_id_i;
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assign lsu_valid_o = 1'b0;
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logic [63:0] vaddr;
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// ------------------------------
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// Address Generation Unit (AGU)
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// ------------------------------
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assign vaddr = imm_i + operand_a_i;
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assign data_if.address = vaddr;
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// ---------------
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// Memory Arbiter
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// ---------------
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@ -73,7 +83,8 @@ module lsu #(
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logic [2:0] data_rvalid_o;
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logic [2:0][63:0] data_rdata_o;
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mem_arbiter i_mem_arbiter (
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// port 0 PTW, port 1 loads, port 2 stores
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mem_arbiter mem_arbiter_i (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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@ -98,6 +109,16 @@ module lsu #(
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.data_rdata_o ( data_rdata_o )
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);
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// connecting PTW to D$ (aka mem arbiter)
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assign address_i[0] = ptw_if.address;
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assign data_wdata_i[0] = ptw_if.data_wdata;
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assign data_req_i[0] = ptw_if.data_req;
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assign data_we_i [0] = ptw_if.data_we;
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assign data_be_i [0] = ptw_if.data_be;
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assign ptw_if.data_rvalid = data_rvalid_o[0];
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assign ptw_if.data_rdata = data_rdata_o[0];
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// -------------------
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// MMU e.g.: TLBs/PTW
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// -------------------
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@ -112,32 +133,142 @@ module lsu #(
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) i_mmu (
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.lsu_req_i ( lsu_req_i ),
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.lsu_vaddr_i ( lsu_vaddr_i ),
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.lsu_valid_o ( ),
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.lsu_valid_o ( ),
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.data_if ( ptw_if ),
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.*
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);
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// ------------------
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// LSU Control
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// ------------------
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always_comb begin : lsu_control
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end
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// ---------------
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// Store Queue
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// ---------------
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// ---------------
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// Sign Extend
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// Byte Enable
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// ---------------
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// ------------------------------
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// Address Generation Unit (AGU)
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// ------------------------------
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assign vaddr = imm_i + operand_a_i;
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assign data_if.address = vaddr;
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// ---------------
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// Sign Extend
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// ---------------
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logic [63:0] rdata_ext;
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// data coming from arbiter interface 1
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assign rdata_ext = data_rdata_o[1];
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logic [63:0] rdata_d_ext; // sign extension for double words, actually only misaligned assembly
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logic [63:0] rdata_w_ext; // sign extension for words
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logic [63:0] rdata_h_ext; // sign extension for half words
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logic [63:0] rdata_b_ext; // sign extension for bytes
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// ------------------
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// LSU Control
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// ------------------
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// double words
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always_comb begin : sign_extend_double_word
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case (vaddr[2:0])
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3'b000: rdata_d_ext = operand_b_i[63:0];
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// this is for misaligned accesse only
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// 3'b001: rdata_d_ext = {data_rdata_i[7:0], rdata_q[63:8]};
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// 3'b010: rdata_d_ext = {data_rdata_i[15:0], rdata_q[63:16]};
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// 3'b011: rdata_d_ext = {data_rdata_i[23:0], rdata_q[63:24]};
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// 3'b100: rdata_d_ext = {data_rdata_i[31:0], rdata_q[63:32]};
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// 3'b101: rdata_d_ext = {data_rdata_i[39:0], rdata_q[63:40]};
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// 3'b110: rdata_d_ext = {data_rdata_i[47:0], rdata_q[63:48]};
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// 3'b111: rdata_d_ext = {data_rdata_i[55:0], rdata_q[63:56]};
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endcase
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end
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// sign extension for words
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always_comb begin : sign_extend_word
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case (vaddr[2:0])
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3'b000: rdata_w_ext = (operator_i == LW) ? {{32{rdata_ext[31]}}, rdata_ext[31:0]} : {32'h0, rdata_ext[31:0]};
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3'b001: rdata_w_ext = (operator_i == LW) ? {{32{rdata_ext[39]}}, rdata_ext[39:8]} : {32'h0, rdata_ext[39:8]};
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3'b010: rdata_w_ext = (operator_i == LW) ? {{32{rdata_ext[47]}}, rdata_ext[47:16]} : {32'h0, rdata_ext[47:16]};
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3'b011: rdata_w_ext = (operator_i == LW) ? {{32{rdata_ext[55]}}, rdata_ext[55:24]} : {32'h0, rdata_ext[55:24]};
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3'b100: rdata_w_ext = (operator_i == LW) ? {{32{rdata_ext[63]}}, rdata_ext[63:32]} : {32'h0, rdata_ext[63:32]};
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// miss-aligned access
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// 3'b101: rdata_w_ext = (data_sign_ext_q) ? {{32{data_rdata_i[7]}}, data_rdata_i[7:0], rdata_q[63:40]} : {32'h0, data_rdata_i[7:0], rdata_q[63:40]};
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// 3'b110: rdata_w_ext = (data_sign_ext_q) ? {{32{data_rdata_i[15]}}, data_rdata_i[15:0], rdata_q[63:48]} : {32'h0, data_rdata_i[15:0], rdata_q[63:48]};
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// 3'b111: rdata_w_ext = (data_sign_ext_q) ? {{32{data_rdata_i[23]}}, data_rdata_i[23:0], rdata_q[63:56]} : {32'h0, data_rdata_i[23:0], rdata_q[63:56]};
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endcase
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end
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// sign extension for half words
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always_comb begin : sign_extend_half_word
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case (vaddr[2:0])
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3'b000: rdata_h_ext = (operator_i == LH) ? {{48{rdata_ext[15]}}, rdata_ext[15:0]} : {48'h0, rdata_ext[15:0]};
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3'b001: rdata_h_ext = (operator_i == LH) ? {{48{rdata_ext[23]}}, rdata_ext[23:8]} : {48'h0, rdata_ext[23:8]};
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3'b010: rdata_h_ext = (operator_i == LH) ? {{48{rdata_ext[31]}}, rdata_ext[31:16]} : {48'h0, rdata_ext[31:16]};
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3'b011: rdata_h_ext = (operator_i == LH) ? {{48{rdata_ext[39]}}, rdata_ext[39:24]} : {48'h0, rdata_ext[39:24]};
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3'b100: rdata_h_ext = (operator_i == LH) ? {{48{rdata_ext[47]}}, rdata_ext[47:32]} : {48'h0, rdata_ext[47:32]};
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3'b101: rdata_h_ext = (operator_i == LH) ? {{48{rdata_ext[55]}}, rdata_ext[55:40]} : {48'h0, rdata_ext[55:40]};
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3'b110: rdata_h_ext = (operator_i == LH) ? {{48{rdata_ext[63]}}, rdata_ext[63:48]} : {48'h0, rdata_ext[63:48]};
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// miss-aligned access
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// 3'b111: rdata_h_ext = (data_sign_ext_q) ? {{48{data_rdata_i[7]}}, data_rdata_i[7:0], rdata_q[31:24]} : {48'h0, data_rdata_i[7:0], rdata_q[31:24]};
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endcase
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end
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always_comb begin : sign_extend_byte
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case (vaddr[2:0])
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3'b000: rdata_b_ext = (operator_i == LB) ? {{56{rdata_ext[7]}}, rdata_ext[7:0]} : {56'h0, rdata_ext[7:0]};
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3'b001: rdata_b_ext = (operator_i == LB) ? {{56{rdata_ext[15]}}, rdata_ext[15:8]} : {56'h0, rdata_ext[15:8]};
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3'b010: rdata_b_ext = (operator_i == LB) ? {{56{rdata_ext[23]}}, rdata_ext[23:16]} : {56'h0, rdata_ext[23:16]};
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3'b011: rdata_b_ext = (operator_i == LB) ? {{56{rdata_ext[31]}}, rdata_ext[31:24]} : {56'h0, rdata_ext[31:24]};
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3'b100: rdata_b_ext = (operator_i == LB) ? {{56{rdata_ext[39]}}, rdata_ext[39:32]} : {56'h0, rdata_ext[39:32]};
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3'b101: rdata_b_ext = (operator_i == LB) ? {{56{rdata_ext[47]}}, rdata_ext[47:40]} : {56'h0, rdata_ext[47:40]};
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3'b110: rdata_b_ext = (operator_i == LB) ? {{56{rdata_ext[55]}}, rdata_ext[55:48]} : {56'h0, rdata_ext[55:48]};
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3'b111: rdata_b_ext = (operator_i == LB) ? {{56{rdata_ext[63]}}, rdata_ext[63:56]} : {56'h0, rdata_ext[63:56]};
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endcase // case (rdata_offset_q)
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end
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always_comb begin
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case (operator_i)
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LD: lsu_result_o = rdata_d_ext;
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LW, LWU: lsu_result_o = rdata_w_ext;
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LH, LHU: lsu_result_o = rdata_h_ext;
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LB, LBU: lsu_result_o = rdata_b_ext;
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endcase //~case(rdata_type_q)
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end
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// ------------------
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// Exception Control
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// ------------------
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// misaligned detector
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// page fault, privilege exception
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always_comb begin : exception_control
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data_misaligned = 1'b0;
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if(lsu_valid_i) begin
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case (operator_i)
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LD, SD: begin // double word
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if(vaddr[2:0] != 3'b000)
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data_misaligned = 1'b1;
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end
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LW, LWU, SW: begin // word
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if(vaddr[2] == 1'b1 && vaddr[2:0] != 3'b100)
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data_misaligned = 1'b1;
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end
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LH, LHU, SH: begin // half word
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if(vaddr[2:0] == 3'b111)
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data_misaligned = 1'b1;
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end // byte -> is always aligned
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default:;
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endcase
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end
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end
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// registers
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if(~rst_ni) begin
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// if the request was valid latch it
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// it is the purpose of the issue stage to not dispatch
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// instructions if the unit was not ready
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end else if (lsu_valid_i) begin
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end
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end
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endmodule
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@ -108,11 +108,11 @@ module mem_arbiter #(
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data_rvalid_o[i] = 1'b0;
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data_rdata_o[i] = 64'b0;
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end
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// if there is an entry in the queue we are waiting for a read to return
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// there is a valid signal and the FIFO should not be empty anyway
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// if there is an entry in the queue -> we are waiting for a read/write to return
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// if there is a valid signal the FIFO should not be empty anyway
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if (data_rvalid_i) begin
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// pass the read through to the appropriate slave
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pop_i = 1'b1;
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// pass the read to the appropriate slave
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pop_i = 1'b1;
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data_rvalid_o[data_o] = data_rvalid_i;
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data_rdata_o[data_o] = data_rdata_i;
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end
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