mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-20 12:17:19 -04:00
Move DCacheType to config struct (#2025)
This commit is contained in:
Florian Zaruba
GitHub
parent
bfff84eaeb
commit
ecd6ed6b6b
23 changed files with 67 additions and 160 deletions
179
Bender.yml
179
Bender.yml
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@ -14,154 +14,93 @@ dependencies:
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tech_cells_generic:
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{ git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 }
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frozen: true
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export_include_dirs:
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- core/include
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sources:
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- include_dirs:
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- core/include
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files:
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- core/include/config_pkg.sv
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- core/include/build_config_pkg.sv
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# Pick the right configuration by passing the right bender flag.
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- target: cv64a6_imafdcv_sv39
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files:
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- core/include/cv64a6_imafdcv_sv39_config_pkg.sv
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- core/include/riscv_pkg.sv
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- core/include/ariane_pkg.sv
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- core/mmu_sv39/tlb.sv
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- core/mmu_sv39/mmu.sv
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- core/mmu_sv39/ptw.sv
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- corev_apu/tb/common/mock_uart.sv
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- target: cv64a6_imafdc_sv39
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files:
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- core/include/cv64a6_imafdc_sv39_config_pkg.sv
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- core/include/riscv_pkg.sv
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- core/include/ariane_pkg.sv
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- core/mmu_sv39/tlb.sv
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- core/mmu_sv39/mmu.sv
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- core/mmu_sv39/ptw.sv
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- core/cva6_accel_first_pass_decoder_stub.sv
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- target: cv64a6_imafdc_sv39_wb
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files:
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- core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
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- core/include/riscv_pkg.sv
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- core/include/ariane_pkg.sv
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- core/mmu_sv39/tlb.sv
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- core/mmu_sv39/mmu.sv
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- core/mmu_sv39/ptw.sv
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- core/cva6_accel_first_pass_decoder_stub.sv
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- target: cv64a6_imafdch_sv39
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files:
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- core/include/cv64a6_imafdch_sv39_config_pkg.sv
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- core/include/riscv_pkg.sv
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- core/include/ariane_pkg.sv
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- core/mmu_sv39x4/cva6_tlb_sv39x4.sv
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- core/mmu_sv39x4/cva6_mmu_sv39x4.sv
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- core/mmu_sv39x4/cva6_ptw_sv39x4.sv
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- core/cva6_accel_first_pass_decoder_stub.sv
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- target: cv64a6_imafdch_sv39_wb
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files:
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- core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
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- core/include/riscv_pkg.sv
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- core/include/ariane_pkg.sv
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- core/mmu_sv39x4/cva6_tlb_sv39x4.sv
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- core/mmu_sv39x4/cva6_mmu_sv39x4.sv
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- core/mmu_sv39x4/cva6_ptw_sv39x4.sv
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- core/cva6_accel_first_pass_decoder_stub.sv
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- target: cv32a6_imac_sv0
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files:
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- core/include/cv32a6_imac_sv0_config_pkg.sv
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- core/include/riscv_pkg.sv
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- core/include/ariane_pkg.sv
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- core/mmu_sv32/cva6_tlb_sv32.sv
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- core/mmu_sv32/cva6_mmu_sv32.sv
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- core/mmu_sv32/cva6_ptw_sv32.sv
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- core/cva6_accel_first_pass_decoder_stub.sv
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- target: cv32a6_imac_sv32
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files:
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- core/include/cv32a6_imac_sv32_config_pkg.sv
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- core/include/riscv_pkg.sv
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- core/include/ariane_pkg.sv
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- core/mmu_sv32/cva6_tlb_sv32.sv
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- core/mmu_sv32/cva6_mmu_sv32.sv
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- core/mmu_sv32/cva6_ptw_sv32.sv
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- core/cva6_accel_first_pass_decoder_stub.sv
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- target: cv32a6_imafc_sv32
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files:
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- core/include/cv32a6_imafc_sv32_config_pkg.sv
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- core/include/riscv_pkg.sv
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- core/include/ariane_pkg.sv
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# General config infrastructure
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- core/include/riscv_pkg.sv
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- core/include/ariane_pkg.sv
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- core/include/build_config_pkg.sv
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- target: not(exclude_first_pass_decoder)
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files:
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- core/cva6_accel_first_pass_decoder_stub.sv
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# MMU
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- target: any(cv64a6_imafdcv_sv39, cv64a6_imafdc_sv39, cv64a6_imafdc_sv39_wb)
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files:
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- core/mmu_sv39/tlb.sv
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- core/mmu_sv39/mmu.sv
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- core/mmu_sv39/ptw.sv
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- target: any(cv64a6_imafdch_sv39, cv64a6_imafdch_sv39_wb)
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files:
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- core/mmu_sv39x4/cva6_tlb_sv39x4.sv
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- core/mmu_sv39x4/cva6_mmu_sv39x4.sv
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- core/mmu_sv39x4/cva6_ptw_sv39x4.sv
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- target: any(cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32)
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files:
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- core/mmu_sv32/cva6_tlb_sv32.sv
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- core/mmu_sv32/cva6_mmu_sv32.sv
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- core/mmu_sv32/cva6_ptw_sv32.sv
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- core/cva6_accel_first_pass_decoder_stub.sv
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# included via target core/include/${TARGET_CFG}_config_pkg.sv
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# ariane_axi_pkg is dependent on this.
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# - vendor/pulp-platform/axi/src/axi_pkg.sv
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# Packages
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- core/include/wt_cache_pkg.sv
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- core/include/std_cache_pkg.sv
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# for all the below files use Flist.cva6 as baseline and also look at Makefile pd/synth
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# CVXIF
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- core/include/instr_tracer_pkg.sv
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# Extension Interface
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- core/include/cvxif_pkg.sv
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- core/cvxif_example/include/cvxif_instr_pkg.sv
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- core/cvxif_fu.sv
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- core/cvxif_example/cvxif_example_coprocessor.sv
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- core/cvxif_example/instr_decoder.sv
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# Tracing
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- core/cva6_rvfi_probes.sv
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- core/cva6_fifo_v3.sv
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# vendored deps
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# - include_dirs: [vendor/pulp-platform/common_cells/include/, vendor/pulp-platform/common_cells/src/]
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# files:
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# - vendor/pulp-platform/common_cells/src/cf_math_pkg.sv
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# - vendor/pulp-platform/common_cells/src/lfsr.sv
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# - vendor/pulp-platform/common_cells/src/lzc.sv
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# - vendor/pulp-platform/common_cells/src/rr_arb_tree.sv
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# - vendor/pulp-platform/common_cells/src/shift_reg.sv
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# - vendor/pulp-platform/common_cells/src/unread.sv
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# - vendor/pulp-platform/common_cells/src/popcount.sv
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# - vendor/pulp-platform/common_cells/src/exp_backoff.sv
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# # Common Cells for example coprocessor
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# - vendor/pulp-platform/common_cells/src/counter.sv
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# - vendor/pulp-platform/common_cells/src/delta_counter.sv
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# Floating point unit
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# - vendor/openhwgroup/cvfpu/src/fpnew_pkg.sv
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# - vendor/openhwgroup/cvfpu/src/fpnew_cast_multi.sv
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# - vendor/openhwgroup/cvfpu/src/fpnew_classifier.sv
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# - vendor/openhwgroup/cvfpu/src/fpnew_divsqrt_multi.sv
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# - vendor/openhwgroup/cvfpu/src/fpnew_fma_multi.sv
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# - vendor/openhwgroup/cvfpu/src/fpnew_fma.sv
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# - vendor/openhwgroup/cvfpu/src/fpnew_noncomp.sv
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# - vendor/openhwgroup/cvfpu/src/fpnew_opgroup_block.sv
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# - vendor/openhwgroup/cvfpu/src/fpnew_opgroup_fmt_slice.sv
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# - vendor/openhwgroup/cvfpu/src/fpnew_opgroup_multifmt_slice.sv
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# - vendor/openhwgroup/cvfpu/src/fpnew_rounding.sv
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# - vendor/openhwgroup/cvfpu/src/fpnew_top.sv
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# - vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
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# - vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
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# - vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
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# - vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
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# - vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
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# - vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
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# - vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
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# Top-level source files (not necessarily instantiated at the top of the cva6).
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- core/cva6.sv
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- core/alu.sv
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# Note: depends on fpnew_pkg, above
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- core/fpu_wrap.sv
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- core/fpu_wrap.sv # depends on fpnew_pkg, above
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- core/branch_unit.sv
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- core/compressed_decoder.sv
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- core/controller.sv
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@ -182,7 +121,6 @@ sources:
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- core/perf_counters.sv
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- core/ariane_regfile_ff.sv
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- core/ariane_regfile_fpga.sv
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# NOTE: scoreboard.sv modified for DSIM (unchanged for other simulators)
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- core/scoreboard.sv
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- core/store_buffer.sv
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- core/amo_buffer.sv
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@ -190,23 +128,22 @@ sources:
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- core/commit_stage.sv
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- core/axi_shim.sv
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# What is "frontend"?
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# Frontend (i.e., fetch, decode, dispatch)
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- core/frontend/btb.sv
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- core/frontend/bht.sv
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- core/frontend/ras.sv
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- core/frontend/instr_scan.sv
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- core/frontend/instr_queue.sv
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- core/frontend/frontend.sv
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# Cache subsystem
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# Cache subsystem(s)
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- core/cache_subsystem/wt_dcache_ctrl.sv
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- core/cache_subsystem/wt_dcache_mem.sv
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- core/cache_subsystem/wt_dcache_missunit.sv
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- core/cache_subsystem/wt_dcache_wbuffer.sv
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- core/cache_subsystem/wt_dcache.sv
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- core/cache_subsystem/cva6_icache.sv
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- core/cache_subsystem/wt_cache_subsystem.sv
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- core/cache_subsystem/wt_axi_adapter.sv
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- core/cache_subsystem/cva6_icache.sv
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- core/cache_subsystem/tag_cmp.sv
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- core/cache_subsystem/cva6_icache_axi_wrapper.sv
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- core/cache_subsystem/axi_adapter.sv
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@ -216,7 +153,6 @@ sources:
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- core/cache_subsystem/std_cache_subsystem.sv
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# Physical Memory Protection
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# NOTE: pmp.sv modified for DSIM (unchanged for other simulators)
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- core/pmp/src/pmp.sv
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- core/pmp/src/pmp_entry.sv
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@ -230,7 +166,6 @@ sources:
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- common/local/util
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files:
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- common/local/util/tc_sram_wrapper.sv
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# - vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv
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- target: all(fpga, xilinx)
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include_dirs:
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@ -246,49 +181,3 @@ sources:
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# Tracer (behavioral code, not RTL)
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- core/include/instr_tracer_pkg.sv
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- common/local/util/instr_tracer.sv
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# TODO target define FPGA target + verification etc
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# - target: test
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# files:
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# - corev_apu/riscv-dbg/src/dm_pkg.sv
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# - corev_apu/tb/ariane_soc_pkg.sv
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# - corev_apu/tb/ariane_axi_soc_pkg.sv
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# - corev_apu/tb/ariane_testharness.sv
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# - corev_apu/tb/ariane_peripherals.sv
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# - corev_apu/tb/common/uart.sv
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# - corev_apu/tb/common/SimDTM.sv
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# - corev_apu/tb/common/SimJTAG.sv
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# - target: all(fpga, xilinx)
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# files:
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# - corev_apu/fpga/src/ariane_peripherals_xilinx.sv
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# - corev_apu/fpga/src/ariane_xilinx.sv
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# - corev_apu/fpga/src/fan_ctrl.sv
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# - corev_apu/fpga/src/bootrom/bootrom.sv
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# - corev_apu/fpga/src/ariane-ethernet/ssio_ddr_in.sv
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# - corev_apu/fpga/src/ariane-ethernet/rgmii_soc.sv
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# - corev_apu/fpga/src/ariane-ethernet/axis_gmii_rx.sv
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# - corev_apu/fpga/src/ariane-ethernet/oddr.sv
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# - corev_apu/fpga/src/ariane-ethernet/axis_gmii_tx.sv
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# - corev_apu/fpga/src/ariane-ethernet/dualmem_widen8.sv
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# - corev_apu/fpga/src/ariane-ethernet/rgmii_phy_if.sv
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# - corev_apu/fpga/src/ariane-ethernet/dualmem_widen.sv
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# - corev_apu/fpga/src/ariane-ethernet/rgmii_lfsr.sv
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# - corev_apu/fpga/src/ariane-ethernet/rgmii_core.sv
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# - corev_apu/fpga/src/ariane-ethernet/eth_mac_1g.sv
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# - corev_apu/fpga/src/ariane-ethernet/eth_mac_1g_rgmii.sv
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# - corev_apu/fpga/src/ariane-ethernet/eth_mac_1g_rgmii_fifo.sv
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# - corev_apu/fpga/src/ariane-ethernet/iddr.sv
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# - corev_apu/fpga/src/ariane-ethernet/framing_top.sv
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# - corev_apu/fpga/src/apb_uart/src/apb_uart.vhd
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# - corev_apu/fpga/src/apb_uart/src/uart_transmitter.vhd
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# - corev_apu/fpga/src/apb_uart/src/uart_interrupt.vhd
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# - corev_apu/fpga/src/apb_uart/src/slib_mv_filter.vhd
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# - corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd
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# - corev_apu/fpga/src/apb_uart/src/slib_counter.vhd
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# - corev_apu/fpga/src/apb_uart/src/uart_receiver.vhd
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# - corev_apu/fpga/src/apb_uart/src/slib_input_sync.vhd
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# - corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd
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# - corev_apu/fpga/src/apb_uart/src/slib_clock_div.vhd
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# - corev_apu/fpga/src/apb_uart/src/slib_fifo.vhd
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# - corev_apu/fpga/src/apb_uart/src/uart_baudgen.vhd
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|
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@ -14,7 +14,7 @@
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// coherent memory system.
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//
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// Define PITON_ARIANE if you want to use this cache.
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// Define DCACHE_TYPE if you want to use this cache
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// Define CVA6Cfg.DCacheType if you want to use this cache
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// with a standard 64 bit AXI interface instead of the OpenPiton
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// L1.5 interface.
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@ -246,7 +246,7 @@ module commit_stage
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// from interrupt service routine
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// Fence synchronizes data and instruction streams. That means that we need to flush the private icache
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// and the private dcache. This is the most expensive instruction.
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if (commit_instr_i[0].op == FENCE_I || (flush_dcache_i && DCACHE_TYPE == int'(config_pkg::WB) && commit_instr_i[0].fu != STORE)) begin
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if (commit_instr_i[0].op == FENCE_I || (flush_dcache_i && CVA6Cfg.DCacheType == config_pkg::WB && commit_instr_i[0].fu != STORE)) begin
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commit_ack_o[0] = no_st_pending_i;
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// tell the controller to flush the I$
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fence_i_o = no_st_pending_i;
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@ -120,7 +120,7 @@ module controller
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flush_ex_o = 1'b1;
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// this is not needed in the case since we
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// have a write-through cache in this case
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if (DCACHE_TYPE == int'(config_pkg::WB)) begin
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if (CVA6Cfg.DCacheType == config_pkg::WB) begin
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flush_dcache = 1'b1;
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fence_active_d = 1'b1;
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end
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@ -138,7 +138,7 @@ module controller
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flush_icache_o = 1'b1;
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// this is not needed in the case since we
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// have a write-through cache in this case
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if (DCACHE_TYPE == int'(config_pkg::WB)) begin
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if (CVA6Cfg.DCacheType == config_pkg::WB) begin
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flush_dcache = 1'b1;
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fence_active_d = 1'b1;
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end
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@ -146,7 +146,7 @@ module controller
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// this is not needed in the case since we
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// have a write-through cache in this case
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if (DCACHE_TYPE == int'(config_pkg::WB)) begin
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if (CVA6Cfg.DCacheType == config_pkg::WB) begin
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// wait for the acknowledge here
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if (flush_dcache_ack_i && fence_active_q) begin
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fence_active_d = 1'b0;
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@ -238,7 +238,7 @@ module controller
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// ----------------------
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always_comb begin
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// halt the core if the fence is active
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halt_o = halt_csr_i || halt_acc_i || (DCACHE_TYPE == int'(config_pkg::WB) && fence_active_q);
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halt_o = halt_csr_i || halt_acc_i || (CVA6Cfg.DCacheType == config_pkg::WB && fence_active_q);
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end
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// ----------------------
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|
|
|
|||
|
|
@ -1193,7 +1193,7 @@ module cva6
|
|||
dcache_req_ports_cache_acc[1].data_gnt &= !dcache_req_ports_ex_cache[2].data_req;
|
||||
end
|
||||
|
||||
if (DCACHE_TYPE == int'(config_pkg::WT)) begin : gen_cache_wt
|
||||
if (CVA6Cfg.DCacheType == config_pkg::WT) begin : gen_cache_wt
|
||||
// this is a cache subsystem that is compatible with OpenPiton
|
||||
wt_cache_subsystem #(
|
||||
.CVA6Cfg (CVA6Cfg),
|
||||
|
|
@ -1242,7 +1242,7 @@ module cva6
|
|||
.inval_valid_i (inval_valid),
|
||||
.inval_ready_o (inval_ready)
|
||||
);
|
||||
end else if (DCACHE_TYPE == int'(config_pkg::HPDCACHE)) begin : gen_cache_hpd
|
||||
end else if (CVA6Cfg.DCacheType == config_pkg::HPDCACHE) begin : gen_cache_hpd
|
||||
cva6_hpdcache_subsystem #(
|
||||
.CVA6Cfg (CVA6Cfg),
|
||||
.icache_areq_t(icache_areq_t),
|
||||
|
|
|
|||
|
|
@ -36,12 +36,11 @@ package ariane_pkg;
|
|||
// depth of store-buffers, this needs to be a power of two
|
||||
localparam logic [2:0] DEPTH_SPEC = 'd4;
|
||||
|
||||
localparam int unsigned DCACHE_TYPE = int'(cva6_config_pkg::CVA6ConfigDcacheType);
|
||||
// if DCACHE_TYPE = cva6_config_pkg::WT
|
||||
// if CVA6Cfg.DCacheType = cva6_config_pkg::WT
|
||||
// we can use a small commit queue since we have a write buffer in the dcache
|
||||
// we could in principle do without the commit queue in this case, but the timing degrades if we do that due
|
||||
// to longer paths into the commit stage
|
||||
// if DCACHE_TYPE = cva6_config_pkg::WB
|
||||
// if CVA6Cfg.DCacheType = cva6_config_pkg::WB
|
||||
// allocate more space for the commit buffer to be on the save side, this needs to be a power of two
|
||||
localparam logic [2:0] DEPTH_COMMIT = 'd4;
|
||||
|
||||
|
|
@ -772,7 +771,7 @@ package ariane_pkg;
|
|||
function automatic logic is_trans_2M(input logic s_st_enbl, input logic g_st_enbl,
|
||||
input logic is_s_1G, input logic is_s_2M,
|
||||
input logic is_g_1G, input logic is_g_2M);
|
||||
return (s_st_enbl && g_st_enbl) ?
|
||||
return (s_st_enbl && g_st_enbl) ?
|
||||
((is_s_2M && (is_g_1G || is_g_2M)) || (is_g_2M && (is_s_1G || is_s_2M))) :
|
||||
((is_s_2M && s_st_enbl) || (is_g_2M && g_st_enbl));
|
||||
endfunction : is_trans_2M
|
||||
|
|
|
|||
|
|
@ -111,6 +111,7 @@ package build_config_pkg;
|
|||
cfg.ICACHE_TAG_WIDTH = cfg.PLEN - ICACHE_INDEX_WIDTH;
|
||||
cfg.ICACHE_LINE_WIDTH = CVA6Cfg.IcacheLineWidth;
|
||||
cfg.ICACHE_USER_LINE_WIDTH = (CVA6Cfg.AxiUserWidth == 1) ? 4 : CVA6Cfg.IcacheLineWidth;
|
||||
cfg.DCacheType = CVA6Cfg.DCacheType;
|
||||
cfg.DCACHE_SET_ASSOC = CVA6Cfg.DcacheSetAssoc;
|
||||
cfg.DCACHE_SET_ASSOC_WIDTH = $clog2(CVA6Cfg.DcacheSetAssoc);
|
||||
cfg.DCACHE_INDEX_WIDTH = DCACHE_INDEX_WIDTH;
|
||||
|
|
|
|||
|
|
@ -136,6 +136,8 @@ package config_pkg;
|
|||
int unsigned IcacheSetAssoc;
|
||||
// Instruction cache line width
|
||||
int unsigned IcacheLineWidth;
|
||||
// Cache Type
|
||||
cache_type_t DCacheType;
|
||||
// Data cache size (in bytes)
|
||||
int unsigned DcacheByteSize;
|
||||
// Data cache associativity (number of ways)
|
||||
|
|
@ -255,6 +257,7 @@ package config_pkg;
|
|||
int unsigned ICACHE_TAG_WIDTH;
|
||||
int unsigned ICACHE_LINE_WIDTH;
|
||||
int unsigned ICACHE_USER_LINE_WIDTH;
|
||||
cache_type_t DCacheType;
|
||||
int unsigned DCACHE_SET_ASSOC;
|
||||
int unsigned DCACHE_SET_ASSOC_WIDTH;
|
||||
int unsigned DCACHE_INDEX_WIDTH;
|
||||
|
|
|
|||
|
|
@ -131,6 +131,7 @@ package cva6_config_pkg;
|
|||
IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize),
|
||||
IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc),
|
||||
IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth),
|
||||
DCacheType: CVA6ConfigDcacheType,
|
||||
DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
|
||||
DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
|
||||
DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
|
||||
|
|
|
|||
|
|
@ -130,6 +130,7 @@ package cva6_config_pkg;
|
|||
IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize),
|
||||
IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc),
|
||||
IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth),
|
||||
DCacheType: CVA6ConfigDcacheType,
|
||||
DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
|
||||
DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
|
||||
DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
|
||||
|
|
|
|||
|
|
@ -130,6 +130,7 @@ package cva6_config_pkg;
|
|||
IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize),
|
||||
IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc),
|
||||
IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth),
|
||||
DCacheType: CVA6ConfigDcacheType,
|
||||
DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
|
||||
DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
|
||||
DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
|
||||
|
|
|
|||
|
|
@ -131,6 +131,7 @@ package cva6_config_pkg;
|
|||
IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize),
|
||||
IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc),
|
||||
IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth),
|
||||
DCacheType: CVA6ConfigDcacheType,
|
||||
DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
|
||||
DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
|
||||
DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
|
||||
|
|
|
|||
|
|
@ -131,6 +131,7 @@ package cva6_config_pkg;
|
|||
IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize),
|
||||
IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc),
|
||||
IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth),
|
||||
DCacheType: CVA6ConfigDcacheType,
|
||||
DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
|
||||
DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
|
||||
DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
|
||||
|
|
|
|||
|
|
@ -131,6 +131,7 @@ package cva6_config_pkg;
|
|||
IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize),
|
||||
IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc),
|
||||
IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth),
|
||||
DCacheType: CVA6ConfigDcacheType,
|
||||
DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
|
||||
DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
|
||||
DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
|
||||
|
|
|
|||
|
|
@ -134,6 +134,7 @@ package cva6_config_pkg;
|
|||
DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
|
||||
DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
|
||||
DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
|
||||
DCacheType: CVA6ConfigDcacheType,
|
||||
DataUserEn: unsigned'(CVA6ConfigDataUserEn),
|
||||
FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),
|
||||
FetchUserEn: unsigned'(CVA6ConfigFetchUserEn)
|
||||
|
|
|
|||
|
|
@ -131,6 +131,7 @@ package cva6_config_pkg;
|
|||
IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize),
|
||||
IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc),
|
||||
IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth),
|
||||
DCacheType: CVA6ConfigDcacheType,
|
||||
DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
|
||||
DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
|
||||
DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
|
||||
|
|
|
|||
|
|
@ -131,6 +131,7 @@ package cva6_config_pkg;
|
|||
IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize),
|
||||
IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc),
|
||||
IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth),
|
||||
DCacheType: CVA6ConfigDcacheType,
|
||||
DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
|
||||
DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
|
||||
DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
|
||||
|
|
|
|||
|
|
@ -138,6 +138,7 @@ package cva6_config_pkg;
|
|||
IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize),
|
||||
IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc),
|
||||
IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth),
|
||||
DCacheType: CVA6ConfigDcacheType,
|
||||
DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
|
||||
DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
|
||||
DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
|
||||
|
|
|
|||
|
|
@ -131,6 +131,7 @@ package cva6_config_pkg;
|
|||
IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize),
|
||||
IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc),
|
||||
IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth),
|
||||
DCacheType: CVA6ConfigDcacheType,
|
||||
DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
|
||||
DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
|
||||
DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
|
||||
|
|
|
|||
|
|
@ -131,6 +131,7 @@ package cva6_config_pkg;
|
|||
IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize),
|
||||
IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc),
|
||||
IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth),
|
||||
DCacheType: CVA6ConfigDcacheType,
|
||||
DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
|
||||
DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
|
||||
DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
|
||||
|
|
|
|||
|
|
@ -124,7 +124,8 @@ package cva6_config_pkg;
|
|||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
MaxOutstandingStores: unsigned'(7),
|
||||
DebugEn: bit'(1),
|
||||
AxiBurstWriteEn: bit'(0)
|
||||
AxiBurstWriteEn: bit'(0),
|
||||
DCacheType: CVA6ConfigDcacheType
|
||||
};
|
||||
|
||||
endpackage
|
||||
|
|
|
|||
|
|
@ -124,7 +124,8 @@ package cva6_config_pkg;
|
|||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
MaxOutstandingStores: unsigned'(7),
|
||||
DebugEn: bit'(1),
|
||||
AxiBurstWriteEn: bit'(0)
|
||||
AxiBurstWriteEn: bit'(0),
|
||||
DCacheType: CVA6ConfigDcacheType
|
||||
};
|
||||
|
||||
endpackage
|
||||
|
|
|
|||
|
|
@ -136,6 +136,7 @@ package cva6_config_pkg;
|
|||
DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
|
||||
DataUserEn: unsigned'(CVA6ConfigDataUserEn),
|
||||
FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),
|
||||
FetchUserEn: unsigned'(CVA6ConfigFetchUserEn)
|
||||
FetchUserEn: unsigned'(CVA6ConfigFetchUserEn),
|
||||
DCacheType: CVA6ConfigDcacheType
|
||||
};
|
||||
endpackage
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue