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Add multiplication encoding
This commit is contained in:
Florian Zaruba
parent
6560ef9520
commit
ed3a4ea13b
2 changed files with 94 additions and 79 deletions
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@ -222,22 +222,31 @@ module decoder (
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// Reg-Reg Operations
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// --------------------------
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OPCODE_OP: begin
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instruction_o.fu = ALU;
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instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU;
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instruction_o.rs1 = instr.rtype.rs1;
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instruction_o.rs2 = instr.rtype.rs2;
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instruction_o.rd = instr.rtype.rd;
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unique case ({instr.rtype.funct7, instr.rtype.funct3})
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{6'b00_0000, 3'b000}: instruction_o.op = ADD; // Add
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{6'b10_0000, 3'b000}: instruction_o.op = SUB; // Sub
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{6'b00_0000, 3'b010}: instruction_o.op = SLTS; // Set Lower Than
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{6'b00_0000, 3'b011}: instruction_o.op = SLTU; // Set Lower Than Unsigned
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{6'b00_0000, 3'b100}: instruction_o.op = XORL; // Xor
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{6'b00_0000, 3'b110}: instruction_o.op = ORL; // Or
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{6'b00_0000, 3'b111}: instruction_o.op = ANDL; // And
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{6'b00_0000, 3'b001}: instruction_o.op = SLL; // Shift Left Logical
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{6'b00_0000, 3'b101}: instruction_o.op = SRL; // Shift Right Logical
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{6'b10_0000, 3'b101}: instruction_o.op = SRA; // Shift Right Arithmetic
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{7'b000_0000, 3'b000}: instruction_o.op = ADD; // Add
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{7'b010_0000, 3'b000}: instruction_o.op = SUB; // Sub
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{7'b000_0000, 3'b010}: instruction_o.op = SLTS; // Set Lower Than
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{7'b000_0000, 3'b011}: instruction_o.op = SLTU; // Set Lower Than Unsigned
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{7'b000_0000, 3'b100}: instruction_o.op = XORL; // Xor
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{7'b000_0000, 3'b110}: instruction_o.op = ORL; // Or
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{7'b000_0000, 3'b111}: instruction_o.op = ANDL; // And
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{7'b000_0000, 3'b001}: instruction_o.op = SLL; // Shift Left Logical
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{7'b000_0000, 3'b101}: instruction_o.op = SRL; // Shift Right Logical
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{7'b010_0000, 3'b101}: instruction_o.op = SRA; // Shift Right Arithmetic
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// Multiplications
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{7'b000_0001, 3'b000}: instruction_o.op = MUL;
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{7'b000_0001, 3'b001}: instruction_o.op = MULH;
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{7'b000_0001, 3'b010}: instruction_o.op = MULHSU;
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{7'b000_0001, 3'b011}: instruction_o.op = MULHU;
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{7'b000_0001, 3'b100}: instruction_o.op = DIV;
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{7'b000_0001, 3'b101}: instruction_o.op = DIVU;
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{7'b000_0001, 3'b110}: instruction_o.op = REM;
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{7'b000_0001, 3'b111}: instruction_o.op = REMU;
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default: begin
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illegal_instr = 1'b1;
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end
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@ -256,12 +265,16 @@ module decoder (
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if (~instr.instr[28])
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unique case ({instr.rtype.funct7, instr.rtype.funct3})
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{6'b00_0000, 3'b000}: instruction_o.op = ADDW; // addw
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{6'b10_0000, 3'b000}: instruction_o.op = SUBW; // subw
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{6'b00_0000, 3'b001}: instruction_o.op = SLLW; // sllw
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{6'b00_0000, 3'b101}: instruction_o.op = SRLW; // srlw
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{6'b10_0000, 3'b101}: instruction_o.op = SRAW; // sraw
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// multiplications
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{7'b000_0000, 3'b000}: instruction_o.op = ADDW; // addw
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{7'b010_0000, 3'b000}: instruction_o.op = SUBW; // subw
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{7'b000_0000, 3'b001}: instruction_o.op = SLLW; // sllw
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{7'b000_0000, 3'b101}: instruction_o.op = SRLW; // srlw
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{7'b010_0000, 3'b101}: instruction_o.op = SRAW; // sraw
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// Multiplications
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{7'b000_0001, 3'b000}: instruction_o.op = MULW;
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{7'b000_0001, 3'b100}: instruction_o.op = DIVW;
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{7'b000_0001, 3'b110}: instruction_o.op = REMW;
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{7'b000_0001, 3'b111}: instruction_o.op = REMUW;
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default: illegal_instr = 1'b1;
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endcase
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126
src/mult.sv
126
src/mult.sv
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@ -36,77 +36,79 @@ module mult
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output logic mult_ready_o,
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output logic [TRANS_ID_BITS-1:0] mult_trans_id_o
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);
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// MUL and MULH is a two cycle instructions
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logic signed [63:0] result_mult;
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logic signed [63:0] result_multh;
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enum logic {FIRST_CYCLE, SECOND_CYCLE} multCS, multNS;
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logic [TRANS_ID_BITS-1:0] mult_trans_q, mult_trans_n;
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// // MUL and MULH is a two cycle instructions
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// logic signed [63:0] result_mult;
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// logic signed [63:0] result_multh;
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// enum logic {FIRST_CYCLE, SECOND_CYCLE} multCS, multNS;
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// logic [TRANS_ID_BITS-1:0] mult_trans_q, mult_trans_n;
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assign mult_trans_id_o = mult_trans_q;
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assign result_o = is_low_part_i ? result_mult : result_multh;
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// assign mult_trans_id_o = mult_trans_q;
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// assign result_o = is_low_part_i ? result_mult : result_multh;
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mult_datapath
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mult_dp
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(
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.operand_a_i (operand_a_i ),
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.operand_b_i (operand_b_i ),
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.sign_a_i (sign_a_i ),
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.sign_b_i (sign_b_i ),
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.result_low_o (result_mult ),
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.result_high_o (result_multh )
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);
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// mult_datapath
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// mult_dp
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// (
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// .operand_a_i (operand_a_i ),
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// .operand_b_i (operand_b_i ),
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// .sign_a_i (sign_a_i ),
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// .sign_b_i (sign_b_i ),
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// .result_low_o (result_mult ),
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// .result_high_o (result_multh )
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// );
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always_comb begin
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mult_valid_o = 1'b0;
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mult_ready_o = 1'b0;
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multNS = multCS;
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mult_trans_n = mult_trans_q;
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unique case (multCS)
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FIRST_CYCLE: begin
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mult_valid_o = 1'b0;
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mult_ready_o = 1'b0;
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multNS = mult_valid_i ? SECOND_CYCLE : multCS;
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end
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SECOND_CYCLE: begin
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multNS = FIRST_CYCLE;
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mult_valid_o = 1'b1;
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mult_ready_o = 1'b1;
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end
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default:;
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endcase
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end
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// always_comb begin
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// mult_valid_o = 1'b0;
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// mult_ready_o = 1'b0;
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// multNS = multCS;
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// mult_trans_n = mult_trans_q;
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// unique case (multCS)
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// FIRST_CYCLE: begin
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// mult_valid_o = 1'b0;
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// mult_ready_o = 1'b0;
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// multNS = mult_valid_i ? SECOND_CYCLE : multCS;
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// end
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// SECOND_CYCLE: begin
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// multNS = FIRST_CYCLE;
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// mult_valid_o = 1'b1;
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// mult_ready_o = 1'b1;
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// end
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// default:;
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// endcase
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// end
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if(~rst_ni) begin
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multCS <= FIRST_CYCLE;
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end else begin
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multCS <= multNS;
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mult_trans_n <= mult_trans_q;
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end
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end
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// always_ff @(posedge clk_i or negedge rst_ni) begin
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// if(~rst_ni) begin
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// multCS <= FIRST_CYCLE;
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// end else begin
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// multCS <= multNS;
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// mult_trans_n <= mult_trans_q;
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// end
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// end
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// Check if we need sign extension
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endmodule
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module mult_datapath
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(
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input logic [63:0] operand_a_i,
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input logic [63:0] operand_b_i,
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input logic sign_a_i,
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input logic sign_b_i,
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output logic [63:0] result_low_o,
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output logic [63:0] result_high_o
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);
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// module mult_datapath
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// (
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// input logic [63:0] operand_a_i,
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// input logic [63:0] operand_b_i,
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// input logic sign_a_i,
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// input logic sign_b_i,
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// output logic [63:0] result_low_o,
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// output logic [63:0] result_high_o
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// );
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logic signed [129:0] mult_result;
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logic signed [64:0] operand_a_ext;
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logic signed [64:0] operand_b_ext;
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// logic signed [129:0] mult_result;
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// logic signed [64:0] operand_a_ext;
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// logic signed [64:0] operand_b_ext;
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assign operand_a_ext = $signed({sign_a_i & operand_a_i[63], operand_a_i});
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assign operand_b_ext = $signed({sign_b_i & operand_b_i[63], operand_b_i});
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// assign operand_a_ext = $signed({sign_a_i & operand_a_i[63], operand_a_i});
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// assign operand_b_ext = $signed({sign_b_i & operand_b_i[63], operand_b_i});
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assign mult_result = operand_a_ext * operand_b_ext;
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// assign mult_result = operand_a_ext * operand_b_ext;
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assign result_low_o = $signed(mult_result[ 63: 0]);
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assign result_high_o = $signed(mult_result[127:64]);
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// assign result_low_o = $signed(mult_result[ 63: 0]);
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// assign result_high_o = $signed(mult_result[127:64]);
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endmodule
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// endmodule
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