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[CV32A65X] Update PMPADDRn spec to make bit 0 ROCST 0. Update config files. (#2651)
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Update CV32A65X-annotated privileged ISA specification to reflect the fact that with PMP granularity 8 and only supported PMP address matching modes being OFF and TOR, bit 0 of the pmpaddr0..pmpaddr7 registers can be safely made read-only zero. Update riscv-config specifications and its generated files accordingly.
This commit is contained in:
Zbigniew Chamski 2024-12-09 13:22:38 +01:00 • committed by GitHub
parent 5ff6b2d32e
commit ed89c717f7
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GPG key ID: B5690EEEBB952194
6 changed files with 31 additions and 25 deletions
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2
config/gen_from_riscv_config/cv32a65x/csr/csr.adoc
View file

@ -334,7 +334,7 @@ Description:: Physical memory protection address register
|=== |===
| Bits | Field Name | Reset Value | Type | Legal Values | Description | Bits | Field Name | Reset Value | Type | Legal Values | Description
| [31:0] | PMPADDR[I] | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | Physical memory protection address register | [31:0] | PMPADDR[I] | 0x00000000 | WARL | masked: & 0xFFFFFFFE \| 0x0 | Physical memory protection address register
|=== |===
[[_PMPADDR8-63]] [[_PMPADDR8-63]]

10
config/gen_from_riscv_config/cv32a65x/csr/csr.rst
View file

@ -418,13 +418,13 @@ PMPCFG[0-1]
+---------+----------------+---------------+--------+----------------------+------------------------+ +---------+----------------+---------------+--------+----------------------+------------------------+
| Bits | Field Name | Reset Value | Type | Legal Values | Description | | Bits | Field Name | Reset Value | Type | Legal Values | Description |
+=========+================+===============+========+======================+========================+ +=========+================+===============+========+======================+========================+
| [7:0] | PMP[I*4 +0]CFG | 0x0 | WARL | masked: & 0x8f | 0x0 | pmp configuration bits | | [7:0] | PMP[I*4 +0]CFG | 0x0 | WARL | masked: & 0x8f \| 0x0 | pmp configuration bits |
+---------+----------------+---------------+--------+----------------------+------------------------+ +---------+----------------+---------------+--------+----------------------+------------------------+
| [15:8] | PMP[I*4 +1]CFG | 0x0 | WARL | masked: & 0x8f | 0x0 | pmp configuration bits | | [15:8] | PMP[I*4 +1]CFG | 0x0 | WARL | masked: & 0x8f \| 0x0 | pmp configuration bits |
+---------+----------------+---------------+--------+----------------------+------------------------+ +---------+----------------+---------------+--------+----------------------+------------------------+
| [23:16] | PMP[I*4 +2]CFG | 0x0 | WARL | masked: & 0x8f | 0x0 | pmp configuration bits | | [23:16] | PMP[I*4 +2]CFG | 0x0 | WARL | masked: & 0x8f \| 0x0 | pmp configuration bits |
+---------+----------------+---------------+--------+----------------------+------------------------+ +---------+----------------+---------------+--------+----------------------+------------------------+
| [31:24] | PMP[I*4 +3]CFG | 0x0 | WARL | masked: & 0x8f | 0x0 | pmp configuration bits | | [31:24] | PMP[I*4 +3]CFG | 0x0 | WARL | masked: & 0x8f \| 0x0 | pmp configuration bits |
+---------+----------------+---------------+--------+----------------------+------------------------+ +---------+----------------+---------------+--------+----------------------+------------------------+
@ -462,7 +462,7 @@ PMPADDR[0-7]
+--------+--------------+---------------+--------+-------------------------+---------------------------------------------+ +--------+--------------+---------------+--------+-------------------------+---------------------------------------------+
| Bits | Field Name | Reset Value | Type | Legal Values | Description | | Bits | Field Name | Reset Value | Type | Legal Values | Description |
+========+==============+===============+========+=========================+=============================================+ +========+==============+===============+========+=========================+=============================================+
| [31:0] | PMPADDR[I] | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | Physical memory protection address register | | [31:0] | PMPADDR[I] | 0x00000000 | WARL | masked: & 0xFFFFFFFE \| 0x00000000 | Physical memory protection address register |
+--------+--------------+---------------+--------+-------------------------+---------------------------------------------+ +--------+--------------+---------------+--------+-------------------------+---------------------------------------------+

8
config/gen_from_riscv_config/cv32a65x/spike/spike.yaml
View file

@ -44,6 +44,14 @@ spike_param_tree:
tdata2_accessible: 0 tdata2_accessible: 0
tdata3_accessible: 0 tdata3_accessible: 0
tselect_accessible: 0 tselect_accessible: 0
pmpaddr0_write_mask: 0xFFFFFFFE
pmpaddr1_write_mask: 0xFFFFFFFE
pmpaddr2_write_mask: 0xFFFFFFFE
pmpaddr3_write_mask: 0xFFFFFFFE
pmpaddr4_write_mask: 0xFFFFFFFE
pmpaddr5_write_mask: 0xFFFFFFFE
pmpaddr6_write_mask: 0xFFFFFFFE
pmpaddr7_write_mask: 0xFFFFFFFE
mhartid: 0 mhartid: 0
mvendorid_override_mask : 0xFFFFFFFF mvendorid_override_mask : 0xFFFFFFFF
mvendorid_override_value: 1538 mvendorid_override_value: 1538

16
config/riscv-config/cv32a65x/generated/isa_gen.yaml
View file

@ -3165,7 +3165,7 @@ hart0:
warl: warl:
dependency_fields: [] dependency_fields: []
legal: legal:
- pmpaddr0[31:0] in [0x00000000:0xFFFFFFFF] - pmpaddr0[31:0] bitmask [0xFFFFFFFE, 0x00000000]
wr_illegal: wr_illegal:
- unchanged - unchanged
fields: [] fields: []
@ -3186,7 +3186,7 @@ hart0:
warl: warl:
dependency_fields: [] dependency_fields: []
legal: legal:
- pmpaddr1[31:0] in [0x00000000:0xFFFFFFFF] - pmpaddr1[31:0] bitmask [0xFFFFFFFE, 0x00000000]
wr_illegal: wr_illegal:
- unchanged - unchanged
fields: [] fields: []
@ -3207,7 +3207,7 @@ hart0:
warl: warl:
dependency_fields: [] dependency_fields: []
legal: legal:
- pmpaddr2[31:0] in [0x00000000:0xFFFFFFFF] - pmpaddr2[31:0] bitmask [0xFFFFFFFE, 0x00000000]
wr_illegal: wr_illegal:
- unchanged - unchanged
fields: [] fields: []
@ -3228,7 +3228,7 @@ hart0:
warl: warl:
dependency_fields: [] dependency_fields: []
legal: legal:
- pmpaddr3[31:0] in [0x00000000:0xFFFFFFFF] - pmpaddr3[31:0] bitmask [0xFFFFFFFE, 0x00000000]
wr_illegal: wr_illegal:
- unchanged - unchanged
fields: [] fields: []
@ -3249,7 +3249,7 @@ hart0:
warl: warl:
dependency_fields: [] dependency_fields: []
legal: legal:
- pmpaddr4[31:0] in [0x00000000:0xFFFFFFFF] - pmpaddr4[31:0] bitmask [0xFFFFFFFE, 0x00000000]
wr_illegal: wr_illegal:
- unchanged - unchanged
fields: [] fields: []
@ -3270,7 +3270,7 @@ hart0:
warl: warl:
dependency_fields: [] dependency_fields: []
legal: legal:
- pmpaddr5[31:0] in [0x00000000:0xFFFFFFFF] - pmpaddr5[31:0] bitmask [0xFFFFFFFE, 0x00000000]
wr_illegal: wr_illegal:
- unchanged - unchanged
fields: [] fields: []
@ -3291,7 +3291,7 @@ hart0:
warl: warl:
dependency_fields: [] dependency_fields: []
legal: legal:
- pmpaddr6[31:0] in [0x00000000:0xFFFFFFFF] - pmpaddr6[31:0] bitmask [0xFFFFFFFE, 0x00000000]
wr_illegal: wr_illegal:
- unchanged - unchanged
fields: [] fields: []
@ -3312,7 +3312,7 @@ hart0:
warl: warl:
dependency_fields: [] dependency_fields: []
legal: legal:
- pmpaddr7[31:0] in [0x00000000:0xFFFFFFFF] - pmpaddr7[31:0] bitmask [0xFFFFFFFE, 0x00000000]
wr_illegal: wr_illegal:
- unchanged - unchanged
fields: [] fields: []

16
config/riscv-config/cv32a65x/spec/isa_spec.yaml
View file

@ -1440,7 +1440,7 @@ hart0: &hart0
warl: warl:
dependency_fields: [] dependency_fields: []
legal: legal:
- pmpaddr0[31:0] in [0x00000000:0xFFFFFFFF] - pmpaddr0[31:0] bitmask [0xFFFFFFFE, 0x00000000]
wr_illegal: wr_illegal:
- unchanged - unchanged
rv64: rv64:
@ -1453,7 +1453,7 @@ hart0: &hart0
warl: warl:
dependency_fields: [] dependency_fields: []
legal: legal:
- pmpaddr1[31:0] in [0x00000000:0xFFFFFFFF] - pmpaddr1[31:0] bitmask [0xFFFFFFFE, 0x00000000]
wr_illegal: wr_illegal:
- unchanged - unchanged
rv64: rv64:
@ -1466,7 +1466,7 @@ hart0: &hart0
warl: warl:
dependency_fields: [] dependency_fields: []
legal: legal:
- pmpaddr2[31:0] in [0x00000000:0xFFFFFFFF] - pmpaddr2[31:0] bitmask [0xFFFFFFFE, 0x00000000]
wr_illegal: wr_illegal:
- unchanged - unchanged
rv64: rv64:
@ -1479,7 +1479,7 @@ hart0: &hart0
warl: warl:
dependency_fields: [] dependency_fields: []
legal: legal:
- pmpaddr3[31:0] in [0x00000000:0xFFFFFFFF] - pmpaddr3[31:0] bitmask [0xFFFFFFFE, 0x00000000]
wr_illegal: wr_illegal:
- unchanged - unchanged
rv64: rv64:
@ -1492,7 +1492,7 @@ hart0: &hart0
warl: warl:
dependency_fields: [] dependency_fields: []
legal: legal:
- pmpaddr4[31:0] in [0x00000000:0xFFFFFFFF] - pmpaddr4[31:0] bitmask [0xFFFFFFFE, 0x00000000]
wr_illegal: wr_illegal:
- unchanged - unchanged
rv64: rv64:
@ -1505,7 +1505,7 @@ hart0: &hart0
warl: warl:
dependency_fields: [] dependency_fields: []
legal: legal:
- pmpaddr5[31:0] in [0x00000000:0xFFFFFFFF] - pmpaddr5[31:0] bitmask [0xFFFFFFFE, 0x00000000]
wr_illegal: wr_illegal:
- unchanged - unchanged
rv64: rv64:
@ -1518,7 +1518,7 @@ hart0: &hart0
warl: warl:
dependency_fields: [] dependency_fields: []
legal: legal:
- pmpaddr6[31:0] in [0x00000000:0xFFFFFFFF] - pmpaddr6[31:0] bitmask [0xFFFFFFFE, 0x00000000]
wr_illegal: wr_illegal:
- unchanged - unchanged
rv64: rv64:
@ -1531,7 +1531,7 @@ hart0: &hart0
warl: warl:
dependency_fields: [] dependency_fields: []
legal: legal:
- pmpaddr7[31:0] in [0x00000000:0xFFFFFFFF] - pmpaddr7[31:0] bitmask [0xFFFFFFFE, 0x00000000]
wr_illegal: wr_illegal:
- unchanged - unchanged
rv64: rv64:

4
docs/riscv-isa/src/machine.adoc
View file

@ -4346,9 +4346,7 @@ ifdef::archi-CVA6[]
[{ohg-config}] The PMP grain is 8 bytes (latexmath:[$2^{G+2}$] with G = 1) [{ohg-config}] The PMP grain is 8 bytes (latexmath:[$2^{G+2}$] with G = 1)
and must be the same across all PMP regions. and must be the same across all PMP regions.
As latexmath:[${\tt pmpcfg}_i$].A[1] is always clear, i.e. the mode is OFF or TOR, As latexmath:[${\tt pmpcfg}_i$].A[1] is always clear, i.e. the mode is OFF or TOR,
then bit latexmath:[${\tt pmpaddr}_i$][0] read as zero. Bit then bit latexmath:[${\tt pmpaddr}_i$][0] is read-only zero.
latexmath:[${\tt pmpaddr}_i$][0] does not affect the TOR address-matching
logic.
endif::[] endif::[]
ifeval::[{note} == true] ifeval::[{note} == true]