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Completion of load unit
This commit is contained in:
Florian Zaruba
parent
54671bce96
commit
edd4665fb5
2 changed files with 259 additions and 33 deletions
282
src/load_unit.sv
282
src/load_unit.sv
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@ -18,11 +18,21 @@
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import ariane_pkg::*;
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// ---------------
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// D$ Tag Status
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// ---------------
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`define WAIT_TRANSLATION 2'b00
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`define VALID_TRANSLATION 2'b01
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`define ABORT_TRANSLATION 2'b10
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`define NOT_IMPL 2'b11
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module load_unit (
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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input logic flush_i,
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// load unit input port
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input logic [1:0] operator_i,
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input logic [TRANS_ID_BITS-1:0] trans_id_i,
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input logic valid_i,
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input logic [63:0] vaddr_i,
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input logic [7:0] be_i,
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@ -50,6 +60,230 @@ module load_unit (
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input logic data_rvalid_i,
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input logic [63:0] data_rdata_i
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);
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enum logic [2:0] {IDLE, WAIT_GNT, SEND_TAG, ABORT_TRANSLATION, WAIT_FLUSH} NS, CS;
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typedef struct packed {
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logic [TRANS_ID_BITS-1:0] trans_id;
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logic [2:0] address_offset;
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fu_t operator;
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} rvalid_entry_t;
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rvalid_entry_t in_data;
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logic push;
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rvalid_entry_t out_data;
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logic pop;
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logic empty;
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logic [63:0] paddr_n, paddr_q;
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// page offset is defined as the lower 12 bits
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assign page_offset_o = vaddr_i[11:0];
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// feed-through the virtual address
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assign vaddr_o = vaddr_i;
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// this is a read-only interface so set the write enable to 0
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assign data_we_o = 1'b0;
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assign in_data = {trans_id_i, vaddr_i[2:0], operator_i};
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// ---------------
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// Load Control
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// ---------------
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always_comb begin : load_controll
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// default assignments
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NS = CS;
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paddr_n = paddr_q;
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translation_req_o = 1'b0;
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address_o = 64'b0;
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ready_o = 1'b1;
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data_req_o = 1'b0;
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data_tag_status_o = `WAIT_TRANSLATION;
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push = 1'b0;
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data_be_o = be_i;
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case (CS)
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IDLE: begin
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// we've got a new load request
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if (valid_i) begin
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// check if the page offset matches with a store, if it does then stall and wait
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if (!page_offset_matches_i) begin
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// make a load request to memory
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data_req_o = 1'b1;
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// we can now output the lower 12 bit as the index to the cache
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address_o[11:0] = vaddr_i[11:0];
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// page offset doesn't match so we can start a new translation request
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translation_req_o = 1'b1;
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// the translation request we got is valid
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if (translation_valid_i) begin
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// save the physical address for the next cycle
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paddr_n = paddr_i;
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// we got no data grant so wait for the grant before sending the tag
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if (!data_gnt_i) begin
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NS = WAIT_GNT;
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ready_o = 1'b0;
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end else begin
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// put the request in the queue
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push = 1'b1;
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// we got a grant so we can send the tag in the next cycle
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NS = SEND_TAG;
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end
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// we got a TLB miss
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end else begin
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// we need to abort the translation and let the PTW walker fix the TLB miss
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NS = ABORT_TRANSLATION;
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ready_o = 1'b0;
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end
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end else begin
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// stall and wait for the store-buffer to drain
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ready_o = 1'b0;
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end
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end
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end
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// we are here because of a TLB miss
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ABORT_TRANSLATION: begin
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// we are not ready here
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ready_o = 1'b0;
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// send an abort signal
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data_tag_status_o = `ABORT_TRANSLATION;
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// wait for the translation to become valid and redo the request
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if (translation_valid_i) begin
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// we have a valid translation so tell the cache it should wait for it on the next cycle
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data_tag_status_o = `WAIT_TRANSLATION;
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// if the request is still here, do the load
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if (valid_i) begin
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address_o = vaddr_i[11:0];
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data_req_o = 1'b1;
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paddr_n = paddr_i;
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if (!data_gnt_i) begin
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NS = WAIT_GNT;
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ready_o = 1'b0;
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end else begin
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// here we are ready to accept a new request
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ready_o = 1'b1;
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// put the request in the queue
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push = 1'b1;
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// we got a grant so we can send the tag in the next cycle
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NS = SEND_TAG;
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end
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end
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end
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end
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WAIT_GNT: begin
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// we are waiting for the grant so we are not ready to accept anything new
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ready_o = 1'b0;
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// keep the request up
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data_req_o = 1'b1;
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// keep the index address valid
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address_o = vaddr_i[11:0];
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// we finally got a data grant
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if (data_gnt_i) begin
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// so we send the tag in the next cycle
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NS = SEND_TAG;
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// we store this grant in our queue
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push = 1'b1;
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// plus: we can accept a new request
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ready_o = 1'b1;
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end
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// otherwise we keep waiting on our grant
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end
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SEND_TAG: begin
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ready_o = 1'b1;
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// if we are sending our tag we are able to process a new request
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data_tag_status_o = `VALID_TRANSLATION;
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// translation from last cycle
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address_o[63:12] = paddr_q[63:12];
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// -------------
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// New Request
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// -------------
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// we can make a new request if we got one
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if (valid_i) begin
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address_o [11:0] = vaddr_i[11:0];
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// do another address translation
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translation_req_o = 1'b1;
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// the translation request we got is valid
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if (translation_valid_i) begin
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// save the physical address for the next cycle
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paddr_n = paddr_i;
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// we got no data grant so wait for the grant before sending the tag
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if (!data_gnt_i) begin
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NS = WAIT_GNT;
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ready_o = 1'b0;
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end else begin
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// put the request in the queue
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push = 1'b1;
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// we got a grant so we can send the tag in the next cycle
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NS = SEND_TAG;
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end
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// we got a TLB miss
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end else begin
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// we need to abort the translation and let the PTW walker fix the TLB miss
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NS = ABORT_TRANSLATION;
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ready_o = 1'b0;
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end
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end else begin
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NS = IDLE;
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end
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end
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WAIT_FLUSH: begin
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ready_o = 1'b0;
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// we got all outstanding requests
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if (empty) begin
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ready_o = 1'b1;
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NS = IDLE;
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end
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end
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endcase
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// if we just flushed and the queue is not empty or we are getting an rvalid this cycle wait in an extra stage
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if (flush_i && (!empty || data_rvalid_i)) begin
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NS = WAIT_FLUSH;
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end
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end
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// decoupled rvalid process
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always_comb begin : rvalid_output
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pop = 1'b0;
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valid_o = 1'b0;
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// we got an rvalid and are currently not flushing
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if (data_rvalid_i && CS != WAIT_FLUSH) begin
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pop = 1'b1;
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valid_o = 1'b1;
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end
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end
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// output the queue data directly, the valid signal is set corresponding to the process above
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assign trans_id_o = out_data.trans_id;
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// latch physical address
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (~rst_ni) begin
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paddr_q <= '0;
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end else begin
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paddr_q <= paddr_n;
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end
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end
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// --------------
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// Rvalid FIFO
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// --------------
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// we can have two outstanding requests, hence we need to elements in the FIFO
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fifo #(
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.dtype ( rvalid_entry_t ),
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.DEPTH ( 2 )
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)
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fifo_i (
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.full_o ( ), // we can ignore the full signal, the FIFO will never overflow
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.empty_o ( empty ), // we can ignore the empty signal, we don't care about it, we will never pop an empty FIFO
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.single_element_o ( ), // we don't care about the single element either
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.data_i ( in_data ),
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.push_i ( push ),
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.data_o ( out_data ),
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.pop_i ( pop ),
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.*
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);
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// ---------------
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// Sign Extend
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@ -66,43 +300,43 @@ module load_unit (
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// sign extension for words
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always_comb begin : sign_extend_word
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case (vaddr_i[2:0])
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default: rdata_w_ext = (operator_i == LW) ? {{32{data_rdata_i[31]}}, data_rdata_i[31:0]} : {32'h0, data_rdata_i[31:0]};
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3'b001: rdata_w_ext = (operator_i == LW) ? {{32{data_rdata_i[39]}}, data_rdata_i[39:8]} : {32'h0, data_rdata_i[39:8]};
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3'b010: rdata_w_ext = (operator_i == LW) ? {{32{data_rdata_i[47]}}, data_rdata_i[47:16]} : {32'h0, data_rdata_i[47:16]};
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3'b011: rdata_w_ext = (operator_i == LW) ? {{32{data_rdata_i[55]}}, data_rdata_i[55:24]} : {32'h0, data_rdata_i[55:24]};
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3'b100: rdata_w_ext = (operator_i == LW) ? {{32{data_rdata_i[63]}}, data_rdata_i[63:32]} : {32'h0, data_rdata_i[63:32]};
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case (out_data.address_offset)
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default: rdata_w_ext = (out_data.operator == LW) ? {{32{data_rdata_i[31]}}, data_rdata_i[31:0]} : {32'h0, data_rdata_i[31:0]};
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3'b001: rdata_w_ext = (out_data.operator == LW) ? {{32{data_rdata_i[39]}}, data_rdata_i[39:8]} : {32'h0, data_rdata_i[39:8]};
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3'b010: rdata_w_ext = (out_data.operator == LW) ? {{32{data_rdata_i[47]}}, data_rdata_i[47:16]} : {32'h0, data_rdata_i[47:16]};
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3'b011: rdata_w_ext = (out_data.operator == LW) ? {{32{data_rdata_i[55]}}, data_rdata_i[55:24]} : {32'h0, data_rdata_i[55:24]};
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3'b100: rdata_w_ext = (out_data.operator == LW) ? {{32{data_rdata_i[63]}}, data_rdata_i[63:32]} : {32'h0, data_rdata_i[63:32]};
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endcase
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end
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// sign extension for half words
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always_comb begin : sign_extend_half_word
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case (vaddr_i[2:0])
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default: rdata_h_ext = (operator_i == LH) ? {{48{data_rdata_i[15]}}, data_rdata_i[15:0]} : {48'h0, data_rdata_i[15:0]};
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3'b001: rdata_h_ext = (operator_i == LH) ? {{48{data_rdata_i[23]}}, data_rdata_i[23:8]} : {48'h0, data_rdata_i[23:8]};
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3'b010: rdata_h_ext = (operator_i == LH) ? {{48{data_rdata_i[31]}}, data_rdata_i[31:16]} : {48'h0, data_rdata_i[31:16]};
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3'b011: rdata_h_ext = (operator_i == LH) ? {{48{data_rdata_i[39]}}, data_rdata_i[39:24]} : {48'h0, data_rdata_i[39:24]};
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3'b100: rdata_h_ext = (operator_i == LH) ? {{48{data_rdata_i[47]}}, data_rdata_i[47:32]} : {48'h0, data_rdata_i[47:32]};
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3'b101: rdata_h_ext = (operator_i == LH) ? {{48{data_rdata_i[55]}}, data_rdata_i[55:40]} : {48'h0, data_rdata_i[55:40]};
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3'b110: rdata_h_ext = (operator_i == LH) ? {{48{data_rdata_i[63]}}, data_rdata_i[63:48]} : {48'h0, data_rdata_i[63:48]};
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case (out_data.address_offset)
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default: rdata_h_ext = (out_data.operator == LH) ? {{48{data_rdata_i[15]}}, data_rdata_i[15:0]} : {48'h0, data_rdata_i[15:0]};
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3'b001: rdata_h_ext = (out_data.operator == LH) ? {{48{data_rdata_i[23]}}, data_rdata_i[23:8]} : {48'h0, data_rdata_i[23:8]};
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3'b010: rdata_h_ext = (out_data.operator == LH) ? {{48{data_rdata_i[31]}}, data_rdata_i[31:16]} : {48'h0, data_rdata_i[31:16]};
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3'b011: rdata_h_ext = (out_data.operator == LH) ? {{48{data_rdata_i[39]}}, data_rdata_i[39:24]} : {48'h0, data_rdata_i[39:24]};
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3'b100: rdata_h_ext = (out_data.operator == LH) ? {{48{data_rdata_i[47]}}, data_rdata_i[47:32]} : {48'h0, data_rdata_i[47:32]};
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3'b101: rdata_h_ext = (out_data.operator == LH) ? {{48{data_rdata_i[55]}}, data_rdata_i[55:40]} : {48'h0, data_rdata_i[55:40]};
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3'b110: rdata_h_ext = (out_data.operator == LH) ? {{48{data_rdata_i[63]}}, data_rdata_i[63:48]} : {48'h0, data_rdata_i[63:48]};
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endcase
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end
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always_comb begin : sign_extend_byte
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case (vaddr_i[2:0])
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default: rdata_b_ext = (operator_i == LB) ? {{56{data_rdata_i[7]}}, data_rdata_i[7:0]} : {56'h0, data_rdata_i[7:0]};
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3'b001: rdata_b_ext = (operator_i == LB) ? {{56{data_rdata_i[15]}}, data_rdata_i[15:8]} : {56'h0, data_rdata_i[15:8]};
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3'b010: rdata_b_ext = (operator_i == LB) ? {{56{data_rdata_i[23]}}, data_rdata_i[23:16]} : {56'h0, data_rdata_i[23:16]};
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3'b011: rdata_b_ext = (operator_i == LB) ? {{56{data_rdata_i[31]}}, data_rdata_i[31:24]} : {56'h0, data_rdata_i[31:24]};
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3'b100: rdata_b_ext = (operator_i == LB) ? {{56{data_rdata_i[39]}}, data_rdata_i[39:32]} : {56'h0, data_rdata_i[39:32]};
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3'b101: rdata_b_ext = (operator_i == LB) ? {{56{data_rdata_i[47]}}, data_rdata_i[47:40]} : {56'h0, data_rdata_i[47:40]};
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3'b110: rdata_b_ext = (operator_i == LB) ? {{56{data_rdata_i[55]}}, data_rdata_i[55:48]} : {56'h0, data_rdata_i[55:48]};
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3'b111: rdata_b_ext = (operator_i == LB) ? {{56{data_rdata_i[63]}}, data_rdata_i[63:56]} : {56'h0, data_rdata_i[63:56]};
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case (out_data.address_offset)
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default: rdata_b_ext = (out_data.operator == LB) ? {{56{data_rdata_i[7]}}, data_rdata_i[7:0]} : {56'h0, data_rdata_i[7:0]};
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3'b001: rdata_b_ext = (out_data.operator == LB) ? {{56{data_rdata_i[15]}}, data_rdata_i[15:8]} : {56'h0, data_rdata_i[15:8]};
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3'b010: rdata_b_ext = (out_data.operator == LB) ? {{56{data_rdata_i[23]}}, data_rdata_i[23:16]} : {56'h0, data_rdata_i[23:16]};
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3'b011: rdata_b_ext = (out_data.operator == LB) ? {{56{data_rdata_i[31]}}, data_rdata_i[31:24]} : {56'h0, data_rdata_i[31:24]};
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3'b100: rdata_b_ext = (out_data.operator == LB) ? {{56{data_rdata_i[39]}}, data_rdata_i[39:32]} : {56'h0, data_rdata_i[39:32]};
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3'b101: rdata_b_ext = (out_data.operator == LB) ? {{56{data_rdata_i[47]}}, data_rdata_i[47:40]} : {56'h0, data_rdata_i[47:40]};
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3'b110: rdata_b_ext = (out_data.operator == LB) ? {{56{data_rdata_i[55]}}, data_rdata_i[55:48]} : {56'h0, data_rdata_i[55:48]};
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3'b111: rdata_b_ext = (out_data.operator == LB) ? {{56{data_rdata_i[63]}}, data_rdata_i[63:56]} : {56'h0, data_rdata_i[63:56]};
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endcase
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end
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always_comb begin
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case (operator_i)
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case (out_data.operator)
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LW, LWU: result_o = rdata_w_ext;
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LH, LHU: result_o = rdata_h_ext;
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LB, LBU: result_o = rdata_b_ext;
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10
src/lsu.sv
10
src/lsu.sv
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@ -18,14 +18,6 @@
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//
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import ariane_pkg::*;
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// ---------------
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// D$ Tag Status
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// ---------------
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`define WAIT_TRANSLATION 2'b00
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`define VALID_TRANSLATION 2'b01
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`define ABORT_TRANSLATION 2'b10
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`define NOT_IMPL 2'b11
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module lsu #(
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parameter int ASID_WIDTH = 1
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)(
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@ -181,10 +173,10 @@ module lsu #(
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logic st_valid;
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logic [TRANS_ID_BITS-1:0] st_trans_id;
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logic [63:0] st_result;
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// ------------------
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// Store Unit
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// ------------------
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store_unit store_unit_i (
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.operator_i ( operator ),
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.trans_id_i ( trans_id ),
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