wt_dcache_buffer: Avoid out-of-range user signal access (#2698)
Some checks are pending
bender-up-to-date / bender-up-to-date (push) Waiting to run
ci / build-riscv-tests (push) Waiting to run
ci / execute-riscv64-tests (push) Blocked by required conditions
ci / execute-riscv32-tests (push) Blocked by required conditions

If the data user signal is disabled and the user bus width is reduced,
the slice operator into the user field will cause elaboration errors.
Since the faulty else block is anyways without effect, just remove it.
This commit is contained in:
Nils Wistoff 2025-01-10 00:42:41 +11:00 committed by GitHub
parent 1c6b89df5b
commit ee58bfab94
No known key found for this signature in database
GPG key ID: B5690EEEBB952194

View file

@ -594,8 +594,6 @@ module wt_dcache_wbuffer
wbuffer_d[wr_ptr].data[k*8+:8] = req_port_i.data_wdata[k*8+:8];
if (CVA6Cfg.DATA_USER_EN) begin
wbuffer_d[wr_ptr].user[k*8+:8] = req_port_i.data_wuser[k*8+:8];
end else begin
wbuffer_d[wr_ptr].user[k*8+:8] = '0;
end
end
end