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Adding configuration-specific CSR doc (#1766)

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Jérôme Quévremont 2024-02-09 13:39:48 +01:00 • committed by GitHub
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docs/01_cva6_user/CSR_CV32A60AX.rst Normal file
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..
Copyright (c) 2023 OpenHW Group
Copyright (c) 2023 Thales DIS design services SAS
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
.. Level 1
=======
Level 2
-------
Level 3
~~~~~~~
Level 4
^^^^^^^
.. _CSR_CV32A60AX:
CV32A60AX Control Status Registers
==================================
*This chapter is not yet available.*

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docs/01_cva6_user/CSR_CV32A60AX_list.rst Normal file
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..
Copyright (c) 2023 OpenHW Group
Copyright (c) 2023 Thales DIS design services SAS
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
.. Level 1
=======
Level 2
-------
Level 3
~~~~~~~
Level 4
^^^^^^^
.. _CSR_CV32A60AX_list:
CV32A60AX Control Status Registers List
=======================================
*This chapter is not yet available.*

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docs/01_cva6_user/CSR_CV32A60X.rst Normal file
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.. include:: ../csr-from-ip-xact/cv32a60x/csr.rst

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.. include:: ../csr-from-ip-xact/cv32a60x/csr_list.rst

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docs/01_cva6_user/Programmer_View.rst
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*The following tables detail the availability of extensions for the various CVA6 configurations:*
CV32A60AX extensions
~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~
These extensions are available in CV32A60AX:
@ -128,7 +128,7 @@ Note: The addition of the H Extension is in the process. After that, HS, VS, and
*The following tables detail the availability of privileges modes for the various CVA6 configurations:*
CV32A60AX privilege modes
~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~
These privilege modes are available in CV32A60AX:
@ -181,7 +181,7 @@ Notes for the integrator:
*These are the addressing modes supported by the various CVA6 configurations:*
CV32A60AX virtual memory
~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~
CV32A60AX integrates an MMU and supports both the **Bare** and **Sv32** addressing modes.

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docs/01_cva6_user/RISCV_Instructions.rst
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@ -162,7 +162,7 @@ The notations below are used in the description of instructions.
- **>>u**: Right shift of 2 unsigned values.
- **M[address]**: Value existe in the address of the memory.
- **M[address]**: Value exists in the address of the memory.
- **/s**: Division of 2 signed values.

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docs/01_cva6_user/RISCV_Instructions_RVZbs.rst
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"CV32A60X", "Implemented extension"
============================
==============================
RVZbs: Single-bit instructions
============================
==============================
The single-bit instructions provide a mechanism to set, clear, invert, or extract a single bit in a register. The bit is specified by its index.
The following instructions (and pseudoinstructions) comprise the Zbs extension:

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docs/01_cva6_user/index.rst
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CVA6 User Manual
================
Editor: **Jerome Quevremont**
.. toctree::
:maxdepth: 2
@ -33,24 +32,30 @@ Editor: **Jerome Quevremont**
Traps_Interrupts_Exceptions
Compiler_Command_Lines
RISCV_Instructions
RISCV_Instructions_RV32I
RISCV_Instructions_RV32M
RISCV_Instructions_RV32A
RISCV_Instructions_RV32C
RISCV_Instructions_RVZba
RISCV_Instructions_RVZbb
RISCV_Instructions_RVZbc
RISCV_Instructions_RVZbs
RISCV_Instructions_RV32ZCb
RISCV_Instructions_RVZicsr
RISCV_Instructions_RVZifencei
RISCV_Instructions_RVZicond
CV32A6_Control_Status_Registers
CV64A6_Control_Status_Registers
RV32I <RISCV_Instructions_RV32I>
RV32M <RISCV_Instructions_RV32M>
RV32A <RISCV_Instructions_RV32A>
RV32C <RISCV_Instructions_RV32C>
RV32Zcb <RISCV_Instructions_RV32ZCb>
RVZba <RISCV_Instructions_RVZba>
RVZbb <RISCV_Instructions_RVZbb>
RVZbc <RISCV_Instructions_RVZbc>
RVZbs <RISCV_Instructions_RVZbs>
RVZicsr <RISCV_Instructions_RVZicsr>
RVZifencei <RISCV_Instructions_RVZifencei>
RVZicond <RISCV_Instructions_RVZicond>
CV32A60X CSR List <CSR_CV32A60X_list>
CV32A60X CSR Details <CSR_CV32A60X>
CV32A60AX CSR List <CSR_CV32A60AX_list>
CV32A60AX CSR Details <CSR_CV32A60AX>
CV64A6 CSR <CV64A6_Control_Status_Registers>
CSR_Cache_Control
CSR_Performance_Counters
CSR Performance Counters <CSR_Performance_Counters>
Parameters_Configuration
Interfaces
AXI Bus Interface <AXI_Interface>
CV-X-IF Interface <CVX_Interface_Coprocessor>
Core_Integration
CVX_Interface_Coprocessor
AXI_Interface