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debug: Bump dm version

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The bump enables crucial fixes for multi-hart debug.
This commit is contained in:
Michael Schaffner 2019-04-17 12:53:00 +02:00 • committed by Florian Zaruba
parent 7232cb18ca
commit ef6e540287
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GPG key ID: E742FFE8EC38A792
4 changed files with 39 additions and 36 deletions
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3
fpga/src/ariane_xilinx.sv
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@ -260,7 +260,7 @@ logic [64-1:0] dm_master_r_rdata;
dm_top #(
.NrHarts ( 1 ),
.BusWidth ( AxiDataWidth ),
.Selectable_Harts ( 1'b1 )
.SelectableHarts ( 1'b1 )
) i_dm_top (
.clk_i ( clk ),
.rst_ni ( rst_n ), // PoR
@ -269,6 +269,7 @@ dm_top #(
.dmactive_o ( dmactive ), // active debug session
.debug_req_o ( debug_req_irq ),
.unavailable_i ( '0 ),
.hartinfo_i ( {ariane_pkg::DebugHartInfo} ),
.slave_req_i ( dm_slave_req ),
.slave_we_i ( dm_slave_we ),
.slave_addr_i ( dm_slave_addr ),

3
openpiton/riscv_peripherals.sv
View file

@ -212,7 +212,7 @@ module riscv_peripherals #(
dm_top #(
.NrHarts ( NumHarts ),
.BusWidth ( AxiDataWidth ),
.Selectable_Harts ( {NumHarts{1'b1}} )
.SelectableHarts ( {NumHarts{1'b1}} )
) i_dm_top (
.clk_i ,
.rst_ni , // PoR
@ -221,6 +221,7 @@ module riscv_peripherals #(
.dmactive_o , // active debug session
.debug_req_o ,
.unavailable_i ,
.hartinfo_i ( {NumHarts{ariane_pkg::DebugHartInfo}} ),
.slave_req_i ( dm_slave_req ),
.slave_we_i ( dm_slave_we ),
.slave_addr_i ( dm_slave_addr ),

2
src/riscv-dbg

@ -1 +1 @@
Subproject commit bec362cd29ce6ea95319f2299f9d3d253bb1ca77
Subproject commit 031ea943fca9a4576068bff54d1414b6fe8b446e

67
tb/ariane_testharness.sv
View file

@ -146,7 +146,7 @@ module ariane_testharness #(
// SiFive's SimDTM Module
// Converts to DPI calls
logic [1:0] debug_req_bits_op;
assign dmi_req.op = dm::dtm_op_t'(debug_req_bits_op);
assign dmi_req.op = dm::dtm_op_e'(debug_req_bits_op);
if (InclSimDTM) begin
SimDTM i_SimDTM (
@ -211,41 +211,42 @@ module ariane_testharness #(
// debug module
dm_top #(
.NrHarts ( 1 ),
.BusWidth ( AXI_DATA_WIDTH ),
.Selectable_Harts ( 1'b1 )
.NrHarts ( 1 ),
.BusWidth ( AXI_DATA_WIDTH ),
.SelectableHarts ( 1'b1 )
) i_dm_top (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ), // PoR
.testmode_i ( test_en ),
.ndmreset_o ( ndmreset ),
.dmactive_o ( ), // active debug session
.debug_req_o ( debug_req_core_ungtd ),
.unavailable_i ( '0 ),
.slave_req_i ( dm_slave_req ),
.slave_we_i ( dm_slave_we ),
.slave_addr_i ( dm_slave_addr ),
.slave_be_i ( dm_slave_be ),
.slave_wdata_i ( dm_slave_wdata ),
.slave_rdata_o ( dm_slave_rdata ),
.master_req_o ( dm_master_req ),
.master_add_o ( dm_master_add ),
.master_we_o ( dm_master_we ),
.master_wdata_o ( dm_master_wdata ),
.master_be_o ( dm_master_be ),
.master_gnt_i ( dm_master_gnt ),
.master_r_valid_i ( dm_master_r_valid ),
.master_r_rdata_i ( dm_master_r_rdata ),
.dmi_rst_ni ( rst_ni ),
.dmi_req_valid_i ( debug_req_valid ),
.dmi_req_ready_o ( debug_req_ready ),
.dmi_req_i ( debug_req ),
.dmi_resp_valid_o ( debug_resp_valid ),
.dmi_resp_ready_i ( debug_resp_ready ),
.dmi_resp_o ( debug_resp )
.clk_i ( clk_i ),
.rst_ni ( rst_ni ), // PoR
.testmode_i ( test_en ),
.ndmreset_o ( ndmreset ),
.dmactive_o ( ), // active debug session
.debug_req_o ( debug_req_core_ungtd ),
.unavailable_i ( '0 ),
.hartinfo_i ( {ariane_pkg::DebugHartInfo} ),
.slave_req_i ( dm_slave_req ),
.slave_we_i ( dm_slave_we ),
.slave_addr_i ( dm_slave_addr ),
.slave_be_i ( dm_slave_be ),
.slave_wdata_i ( dm_slave_wdata ),
.slave_rdata_o ( dm_slave_rdata ),
.master_req_o ( dm_master_req ),
.master_add_o ( dm_master_add ),
.master_we_o ( dm_master_we ),
.master_wdata_o ( dm_master_wdata ),
.master_be_o ( dm_master_be ),
.master_gnt_i ( dm_master_gnt ),
.master_r_valid_i ( dm_master_r_valid ),
.master_r_rdata_i ( dm_master_r_rdata ),
.dmi_rst_ni ( rst_ni ),
.dmi_req_valid_i ( debug_req_valid ),
.dmi_req_ready_o ( debug_req_ready ),
.dmi_req_i ( debug_req ),
.dmi_resp_valid_o ( debug_resp_valid ),
.dmi_resp_ready_i ( debug_resp_ready ),
.dmi_resp_o ( debug_resp )
);
axi2mem #(
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),