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resolved latch lint warnings (#1268)

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Fatima Saleem 2023-06-23 11:28:30 +05:00 • committed by GitHub
parent 4b2f4ca590
commit f038c5831e
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4 changed files with 36 additions and 16 deletions
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14
core/csr_regfile.sv
View file

@ -144,6 +144,7 @@ module csr_regfile import ariane_pkg::*; #(
riscv::pmpcfg_t [15:0] pmpcfg_q, pmpcfg_d;
logic [15:0][riscv::PLEN-3:0] pmpaddr_q, pmpaddr_d;
logic [MHPMCounterNum+3-1:0] mcountinhibit_d,mcountinhibit_q;
int index;
assign pmpcfg_o = pmpcfg_q[15:0];
assign pmpaddr_o = pmpaddr_q;
@ -159,13 +160,14 @@ module csr_regfile import ariane_pkg::*; #(
// ----------------
assign mstatus_extended = riscv::IS_XLEN64 ? mstatus_q[riscv::XLEN-1:0] :
{mstatus_q.sd, mstatus_q.wpri3[7:0], mstatus_q[22:0]};
always_comb begin : csr_read_process
// a read access exception can only occur if we attempt to read a CSR which does not exist
read_access_exception = 1'b0;
csr_rdata = '0;
perf_addr_o = csr_addr.address[11:0];
index = '0;
if (csr_read) begin
unique case (csr_addr.address)
riscv::CSR_FFLAGS: begin
@ -290,7 +292,7 @@ module csr_regfile import ariane_pkg::*; #(
riscv::CSR_MHPM_COUNTER_5,
riscv::CSR_MHPM_COUNTER_6,
riscv::CSR_MHPM_COUNTER_7,
riscv::CSR_MHPM_COUNTER_8,
riscv::CSR_MHPM_COUNTER_8,
riscv::CSR_MHPM_COUNTER_9,
riscv::CSR_MHPM_COUNTER_10,
riscv::CSR_MHPM_COUNTER_11,
@ -313,7 +315,7 @@ module csr_regfile import ariane_pkg::*; #(
riscv::CSR_MHPM_COUNTER_28,
riscv::CSR_MHPM_COUNTER_29,
riscv::CSR_MHPM_COUNTER_30,
riscv::CSR_MHPM_COUNTER_31 : csr_rdata = perf_data_i;
riscv::CSR_MHPM_COUNTER_31 : csr_rdata = perf_data_i;
riscv::CSR_MHPM_COUNTER_3H,
riscv::CSR_MHPM_COUNTER_4H,
@ -351,7 +353,7 @@ module csr_regfile import ariane_pkg::*; #(
riscv::CSR_HPM_COUNTER_5,
riscv::CSR_HPM_COUNTER_6,
riscv::CSR_HPM_COUNTER_7,
riscv::CSR_HPM_COUNTER_8,
riscv::CSR_HPM_COUNTER_8,
riscv::CSR_HPM_COUNTER_9,
riscv::CSR_HPM_COUNTER_10,
riscv::CSR_HPM_COUNTER_11,
@ -432,7 +434,7 @@ module csr_regfile import ariane_pkg::*; #(
riscv::CSR_PMPADDR14,
riscv::CSR_PMPADDR15: begin
// index is specified by the last byte in the address
automatic int index = csr_addr.csr_decode.address[3:0];
index = csr_addr.csr_decode.address[3:0];
// Important: we only support granularity 8 bytes (G=1)
// -> last bit of pmpaddr must be set 0/1 based on the mode:
// NA4, NAPOT: 1

9
core/mmu_sv32/cva6_tlb_sv32.sv
View file

@ -140,8 +140,14 @@ module cva6_tlb_sv32 import ariane_pkg::*; #(
// PLRU - Pseudo Least Recently Used Replacement
// -----------------------------------------------
logic[2*(TLB_ENTRIES-1)-1:0] plru_tree_q, plru_tree_n;
logic en;
int unsigned idx_base, shift, new_index;
always_comb begin : plru_replacement
plru_tree_n = plru_tree_q;
en = '0;
idx_base = '0;
shift = '0;
new_index = '0;
// The PLRU-tree indexing:
// lvl0 0
// / \
@ -166,7 +172,6 @@ module cva6_tlb_sv32 import ariane_pkg::*; #(
// default: begin /* No hit */ end
// endcase
for (int unsigned i = 0; i < TLB_ENTRIES; i++) begin
automatic int unsigned idx_base, shift, new_index;
// we got a hit so update the pointer as it was least recently used
if (lu_hit[i] & lu_access_i) begin
// Set the nodes to the values we would expect
@ -195,8 +200,6 @@ module cva6_tlb_sv32 import ariane_pkg::*; #(
// the corresponding bit of the entry's index, this is
// the next entry to replace.
for (int unsigned i = 0; i < TLB_ENTRIES; i += 1) begin
automatic logic en;
automatic int unsigned idx_base, shift, new_index;
en = 1'b1;
for (int unsigned lvl = 0; lvl < $clog2(TLB_ENTRIES); lvl++) begin
idx_base = $unsigned((2**lvl)-1);

6
core/pmp/src/pmp.sv
View file

@ -73,9 +73,11 @@ module pmp #(
end else assign allow_o = 1'b1;
// synthesis translate_off
always @(*) begin
always_comb begin
logic no_locked;
no_locked = 1'b0;
if(priv_lvl_i == riscv::PRIV_LVL_M) begin
static logic no_locked = 1'b1;
no_locked = 1'b1;
for (int i = 0; i < NR_ENTRIES; i++) begin
if (conf_i[i].locked && conf_i[i].addr_mode != riscv::OFF) begin
no_locked &= 1'b0;

23
core/pmp/src/pmp_entry.sv
View file

@ -29,6 +29,9 @@ module pmp_entry #(
);
logic [PLEN-1:0] conf_addr_n;
logic [$clog2(PLEN)-1:0] trail_ones;
logic [PLEN-1:0] base;
logic [PLEN-1:0] mask;
int unsigned size;
assign conf_addr_n = ~conf_addr_i;
lzc #(.WIDTH(PLEN), .MODE(1'b0)) i_lzc(
.in_i ( conf_addr_n ),
@ -39,6 +42,9 @@ module pmp_entry #(
always_comb begin
case (conf_addr_mode_i)
riscv::TOR: begin
base = '0;
mask = '0;
size = '0;
// check that the requested address is in between the two
// configuration addresses
if (addr_i >= (conf_addr_prev_i << 2) && addr_i < (conf_addr_i << 2)) begin
@ -55,9 +61,6 @@ module pmp_entry #(
end
riscv::NA4, riscv::NAPOT: begin
logic [PLEN-1:0] base;
logic [PLEN-1:0] mask;
int unsigned size;
if (conf_addr_mode_i == riscv::NA4) size = 2;
else begin
@ -100,8 +103,18 @@ module pmp_entry #(
// synthesis translate_on
end
riscv::OFF: match_o = 1'b0;
default: match_o = 0;
riscv::OFF: begin
match_o = 1'b0;
base = '0;
mask = '0;
size = '0;
end
default: begin
match_o = 0;
base = '0;
mask = '0;
size = '0;
end
endcase
end