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fix most of sphinx warnings (#1509)

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Pascal Cotret 2023-10-08 14:42:57 +02:00 • committed by GitHub
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4
docs/01_cva6_user/CVX_Interface_Coprocessor.rst
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@ -102,7 +102,7 @@ If CV-X-IF is enabled and configured with 3 source registers,
a third read port is added to the CVA6 general purpose register file.
Description of interface connections between CVA6 and Coprocessor
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In CVA6 execute stage, there is a new functional unit dedicated to drive the CV-X-IF interfaces.
Here is *how* and *to what* CV-X-IF interfaces are connected to the CVA6.
@ -162,7 +162,7 @@ Here is *how* and *to what* CV-X-IF interfaces are connected to the CVA6.
| information held in these three registers.
Coprocessor recommendations for use with CVA6's CV-X-IF
-----------------------------------------------------
-------------------------------------------------------
CVA6 supports all coprocessors supporting the CV-X-IF specification with the exception of :

2
docs/01_cva6_user/PMA.rst
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@ -53,7 +53,7 @@ structure to describe the PMA regions statically:
- ``CVA6Cfg.CachedRegionLength``: Length of the cacheable region.
Unsupported PMAs
-------
----------------
Currently the following RISC-V defined PMAs are not supported:

2
docs/01_cva6_user/Traps_Interrupts_Exceptions.rst
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@ -30,7 +30,7 @@ Raising Traps
=============
When a trap is raised, the behaviour of the CVA6 core depends on
several CSRs and some CSRs are modified. The CSR description is available
in :doc:`CV32A6_Control_Status_Registers.rst`.
in :doc:`CV32A6_Control_Status_Registers`.
Configuration CSRs
------------------

492
docs/01_cva6_user/ip-xact/cva6_csr.rst
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