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ariane: Support less than 2 commit ports (#365)
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5 changed files with 55 additions and 45 deletions
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@ -281,7 +281,8 @@ module ariane #(
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// ---------
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issue_stage #(
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.NR_ENTRIES ( NR_SB_ENTRIES ),
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.NR_WB_PORTS ( NR_WB_PORTS )
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.NR_WB_PORTS ( NR_WB_PORTS ),
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.NR_COMMIT_PORTS ( NR_COMMIT_PORTS )
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) issue_stage_i (
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.clk_i,
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.rst_ni,
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@ -426,7 +427,9 @@ module ariane #(
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// used e.g. for fence instructions.
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assign no_st_pending_commit = no_st_pending_ex & dcache_commit_wbuffer_empty;
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commit_stage commit_stage_i (
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commit_stage #(
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.NR_COMMIT_PORTS ( NR_COMMIT_PORTS )
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) commit_stage_i (
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.clk_i,
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.rst_ni,
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.halt_i ( halt_ctrl ),
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@ -465,7 +468,8 @@ module ariane #(
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// ---------
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csr_regfile #(
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.AsidWidth ( ASID_WIDTH ),
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.DmBaseAddress ( ArianeCfg.DmBaseAddress )
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.DmBaseAddress ( ArianeCfg.DmBaseAddress ),
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.NrCommitPorts ( NR_COMMIT_PORTS )
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) csr_regfile_i (
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.flush_o ( flush_csr_ctrl ),
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.halt_csr_o ( halt_csr_ctrl ),
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@ -69,9 +69,9 @@ module commit_stage #(
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// .probe9(1'b0) // input wire [0:0] probe9
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// );
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// TODO make these parametric with NR_COMMIT_PORTS
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assign waddr_o[0] = commit_instr_i[0].rd[4:0];
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assign waddr_o[1] = commit_instr_i[1].rd[4:0];
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for (genvar i = 0; i < NR_COMMIT_PORTS; i++) begin : gen_waddr
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assign waddr_o[i] = commit_instr_i[i].rd[4:0];
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end
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assign pc_o = commit_instr_i[0].pc;
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// Dirty the FP state if we are committing anything related to the FPU
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@ -209,38 +209,40 @@ module commit_stage #(
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end
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end
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// -----------------
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// Commit Port 2
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// -----------------
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// check if the second instruction can be committed as well and the first wasn't a CSR instruction
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// also if we are in single step mode don't retire the second instruction
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if (commit_ack_o[0] && commit_instr_i[1].valid
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&& !halt_i
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&& !(commit_instr_i[0].fu inside {CSR})
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&& !flush_dcache_i
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&& !instr_0_is_amo
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&& !single_step_i) begin
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// only if the first instruction didn't throw an exception and this instruction won't throw an exception
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// and the functional unit is of type ALU, LOAD, CTRL_FLOW, MULT, FPU or FPU_VEC
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if (!exception_o.valid && !commit_instr_i[1].ex.valid
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&& (commit_instr_i[1].fu inside {ALU, LOAD, CTRL_FLOW, MULT, FPU, FPU_VEC})) begin
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if (NR_COMMIT_PORTS > 1) begin
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// -----------------
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// Commit Port 2
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// -----------------
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// check if the second instruction can be committed as well and the first wasn't a CSR instruction
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// also if we are in single step mode don't retire the second instruction
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if (commit_ack_o[0] && commit_instr_i[1].valid
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&& !halt_i
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&& !(commit_instr_i[0].fu inside {CSR})
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&& !flush_dcache_i
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&& !instr_0_is_amo
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&& !single_step_i) begin
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// only if the first instruction didn't throw an exception and this instruction won't throw an exception
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// and the functional unit is of type ALU, LOAD, CTRL_FLOW, MULT, FPU or FPU_VEC
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if (!exception_o.valid && !commit_instr_i[1].ex.valid
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&& (commit_instr_i[1].fu inside {ALU, LOAD, CTRL_FLOW, MULT, FPU, FPU_VEC})) begin
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if (is_rd_fpr(commit_instr_i[1].op))
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we_fpr_o[1] = 1'b1;
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else
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we_gpr_o[1] = 1'b1;
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commit_ack_o[1] = 1'b1;
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// additionally check if we are retiring an FPU instruction because we need to make sure that we write all
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// exception flags
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if (commit_instr_i[1].fu inside {FPU, FPU_VEC}) begin
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if (csr_write_fflags_o)
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csr_wdata_o = {59'b0, (commit_instr_i[0].ex.cause[4:0] | commit_instr_i[1].ex.cause[4:0])};
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if (is_rd_fpr(commit_instr_i[1].op))
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we_fpr_o[1] = 1'b1;
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else
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csr_wdata_o = {59'b0, commit_instr_i[1].ex.cause[4:0]};
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we_gpr_o[1] = 1'b1;
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csr_write_fflags_o = 1'b1;
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commit_ack_o[1] = 1'b1;
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// additionally check if we are retiring an FPU instruction because we need to make sure that we write all
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// exception flags
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if (commit_instr_i[1].fu inside {FPU, FPU_VEC}) begin
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if (csr_write_fflags_o)
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csr_wdata_o = {59'b0, (commit_instr_i[0].ex.cause[4:0] | commit_instr_i[1].ex.cause[4:0])};
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else
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csr_wdata_o = {59'b0, commit_instr_i[1].ex.cause[4:0]};
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csr_write_fflags_o = 1'b1;
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end
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end
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end
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end
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@ -1 +1 @@
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Subproject commit 790f2385c01c83022474eede55809666209216e3
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Subproject commit b2a4b2d3decdfc152ad9b4564a48ed3b2649fd6c
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@ -349,9 +349,11 @@ module issue_read_operands #(
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logic [NR_COMMIT_PORTS-1:0][63:0] wdata_pack;
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logic [NR_COMMIT_PORTS-1:0] we_pack;
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assign raddr_pack = {issue_instr_i.rs2[4:0], issue_instr_i.rs1[4:0]};
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assign waddr_pack = {waddr_i[1], waddr_i[0]};
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assign wdata_pack = {wdata_i[1], wdata_i[0]};
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assign we_pack = {we_gpr_i[1], we_gpr_i[0]};
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for (genvar i = 0; i < NR_COMMIT_PORTS; i++) begin : gen_write_back_port
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assign waddr_pack[i] = waddr_i[i];
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assign wdata_pack[i] = wdata_i[i];
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assign we_pack[i] = we_gpr_i[i];
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end
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ariane_regfile #(
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.DATA_WIDTH ( 64 ),
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@ -380,7 +382,9 @@ module issue_read_operands #(
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generate
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if (FP_PRESENT) begin : float_regfile_gen
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assign fp_raddr_pack = {issue_instr_i.result[4:0], issue_instr_i.rs2[4:0], issue_instr_i.rs1[4:0]};
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assign fp_wdata_pack = {wdata_i[1][FLEN-1:0], wdata_i[0][FLEN-1:0]};
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for (genvar i = 0; i < NR_COMMIT_PORTS; i++) begin : gen_fp_wdata_pack
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assign fp_wdata_pack[i] = {wdata_i[i][FLEN-1:0]};
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end
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ariane_regfile #(
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.DATA_WIDTH ( FLEN ),
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@ -438,9 +442,6 @@ module issue_read_operands #(
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@(posedge clk_i) (branch_valid_q) |-> (!$isunknown(operand_a_q) && !$isunknown(operand_b_q)))
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else $warning ("Got unknown value in one of the operands");
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initial begin
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assert (NR_COMMIT_PORTS == 2) else $error("Only two commit ports are supported at the moment!");
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end
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`endif
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//pragma translate_on
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endmodule
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@ -118,7 +118,8 @@ module issue_stage #(
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// ---------------------------------------------------------
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scoreboard #(
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.NR_ENTRIES (NR_ENTRIES ),
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.NR_WB_PORTS(NR_WB_PORTS)
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.NR_WB_PORTS(NR_WB_PORTS),
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.NR_COMMIT_PORTS(NR_COMMIT_PORTS)
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) i_scoreboard (
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.sb_full_o ( sb_full_o ),
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.unresolved_branch_i ( 1'b0 ),
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@ -151,7 +152,9 @@ module issue_stage #(
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// ---------------------------------------------------------
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// 3. Issue instruction and read operand, also commit
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// ---------------------------------------------------------
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issue_read_operands i_issue_read_operands (
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issue_read_operands #(
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.NR_COMMIT_PORTS ( NR_COMMIT_PORTS )
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)i_issue_read_operands (
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.flush_i ( flush_unissued_instr_i ),
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.issue_instr_i ( issue_instr_sb_iro ),
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.issue_instr_valid_i ( issue_instr_valid_sb_iro ),
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