mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-19 11:54:46 -04:00
Add in Github's CI a 64-bit configuration of the CVA6 using the HPDcache and restore WB cache test (#2114)
This commit is contained in:
Cesar Fuguet
GitHub
parent
e6c3bac01e
commit
f32f51777f
5 changed files with 225 additions and 9 deletions
77
.github/workflows/ci.yml
vendored
77
.github/workflows/ci.yml
vendored
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@ -49,15 +49,20 @@ jobs:
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ci/setup.sh
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execute-riscv-tests:
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name: execute-riscv-tests
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execute-riscv64-tests:
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name: execute-riscv64-tests
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runs-on: ubuntu-latest
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env:
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SPIKE_TANDEM: 1
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strategy:
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matrix:
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testcase: [ dv-riscv-arch-test , smoke-tests ]
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target: [ veri-testharness ]
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testcase: [ cv64a6_imafdc_tests ]
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config: [ cv64a6_imafdc_sv39_hpdcache, cv64a6_imafdc_sv39_wb, cv64a6_imafdc_sv39 ]
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simulator: [ veri-testharness ]
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include:
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- testcase: dv-riscv-arch-test
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config: cv64a6_imafdc_sv39_hpdcache
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simulator: veri-testharness
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needs:
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build-riscv-tests
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steps:
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@ -98,11 +103,71 @@ jobs:
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export RISCV=$(pwd)/tools/riscv-toolchain/
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source ci/install-prereq.sh
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source verif/sim/setup-env.sh
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DV_SIMULATORS=${{matrix.target}} bash verif/regress/${{matrix.testcase}}.sh
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DV_SIMULATORS=${{matrix.simulator}},spike DV_TARGET=${{matrix.config}} bash verif/regress/${{matrix.testcase}}.sh
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- name: Upload Lint Report to Github
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uses: actions/upload-artifact@v4
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with:
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name: ${{matrix.target}}.${{matrix.testcase}}
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name: ${{matrix.simulator}}.${{matrix.testcase}}.${{matrix.config}}
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path: 'verif/sim/out*'
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retention-days: 10
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execute-riscv32-tests:
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name: execute-riscv32-tests
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runs-on: ubuntu-latest
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env:
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SPIKE_TANDEM: 1
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strategy:
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matrix:
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testcase: [ dv-riscv-arch-test, cv32a6_tests ]
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config: [ cv32a65x ]
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simulator: [ veri-testharness ]
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needs:
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build-riscv-tests
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steps:
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- uses: actions/checkout@v4
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with:
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submodules: recursive
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- name: Cache toolchain
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id: cache-toolchain
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uses: actions/cache@v3
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env:
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cache-name: cache-toolchain
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with:
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path: tools/riscv-toolchain/
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key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ hashFiles('ci/install-toolchain.sh') }}
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- name: Cache verilator
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id: cache-verilator
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uses: actions/cache@v3
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env:
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cache-name: cache-verilator
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with:
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path: tools/verilator/
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key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ hashFiles('verif/regress/install-verilator.sh') }}
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- name: Cache Spike
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id: cache-spike
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uses: actions/cache@v3
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env:
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cache-name: cache-spike
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with:
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path: tools/spike/
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key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ hashFiles('verif/regress/install-spike.sh', 'verif/core-v-verif/vendor/riscv/riscv-isa-sim/') }}
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- name: Run Tests
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run: |
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set -x
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export RISCV=$(pwd)/tools/riscv-toolchain/
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source ci/install-prereq.sh
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source verif/sim/setup-env.sh
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DV_SIMULATORS=${{matrix.simulator}},spike DV_TARGET=${{matrix.config}} bash verif/regress/${{matrix.testcase}}.sh
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- name: Upload Lint Report to Github
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uses: actions/upload-artifact@v4
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with:
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name: ${{matrix.simulator}}.${{matrix.testcase}}.${{matrix.config}}
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path: 'verif/sim/out*'
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retention-days: 10
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71
verif/regress/cv32a6_tests.sh
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71
verif/regress/cv32a6_tests.sh
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@ -0,0 +1,71 @@
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#!/bin/bash
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# Copyright 2021 Thales DIS design services SAS
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#
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# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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# You may obtain a copy of the License at https://solderpad.org/licenses/
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#
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# Original Author: Jean-Roch COULON - Thales
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# where are the tools
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if ! [ -n "$RISCV" ]; then
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echo "Error: RISCV variable undefined"
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return
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fi
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# install the required tools
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source ./verif/regress/install-verilator.sh
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source ./verif/regress/install-spike.sh
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# install the required test suites
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source ./verif/regress/install-riscv-compliance.sh
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source ./verif/regress/install-riscv-tests.sh
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source ./verif/regress/install-riscv-arch-test.sh
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# setup sim env
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source ./verif/sim/setup-env.sh
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echo "$SPIKE_INSTALL_DIR$"
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if ! [ -n "$DV_SIMULATORS" ]; then
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DV_SIMULATORS=vcs-testharness,spike
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fi
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if ! [ -n "$DV_TARGET" ]; then
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DV_TARGET=cv32a65x
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fi
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if ! [ -n "$UVM_VERBOSITY" ]; then
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export UVM_VERBOSITY=UVM_NONE
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fi
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export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
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cd verif/sim/
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errors=0
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# 32-bit configurations without MMU
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riscv_tests_list=(
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rv32ui-p-add
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rv32ui-p-lw
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rv32ui-p-sw
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rv32ui-p-beq
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rv32ui-p-jal
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)
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for t in ${riscv_tests_list[@]} ; do
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python3 cva6.py --testlist=../tests/testlist_riscv-tests-${DV_TARGET}-p.yaml --test $t --iss_yaml cva6.yaml --target ${DV_TARGET} --iss=$DV_SIMULATORS $DV_OPTS
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[[ $? > 0 ]] && ((errors++))
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done
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python3 cva6.py --target ${DV_TARGET} --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c --linker=../tests/custom/common/test.ld\
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--gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -lgcc -I../tests/custom/env -I../tests/custom/common" $DV_OPTS
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[[ $? > 0 ]] && ((errors++))
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make -C ../.. clean
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make clean_all
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[[ $errors > 0 ]] && exit 1 ;
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exit 0 ;
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74
verif/regress/cv64a6_imafdc_tests.sh
Normal file
74
verif/regress/cv64a6_imafdc_tests.sh
Normal file
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@ -0,0 +1,74 @@
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#!/bin/bash
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# Copyright 2021 Thales DIS design services SAS
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#
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# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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# You may obtain a copy of the License at https://solderpad.org/licenses/
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#
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# Original Author: Jean-Roch COULON - Thales
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#
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# Contributor: Cesar Fuguet, CEA List
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# RISC-V tests for 64-bit configurations implementing MMU
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# where are the tools
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if ! [ -n "$RISCV" ]; then
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echo "Error: RISCV variable undefined"
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return
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fi
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# install the required tools
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source ./verif/regress/install-verilator.sh
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source ./verif/regress/install-spike.sh
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# install the required test suites
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source ./verif/regress/install-riscv-compliance.sh
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source ./verif/regress/install-riscv-tests.sh
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source ./verif/regress/install-riscv-arch-test.sh
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# setup sim env
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source ./verif/sim/setup-env.sh
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echo "$SPIKE_INSTALL_DIR$"
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if ! [ -n "$DV_SIMULATORS" ]; then
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DV_SIMULATORS=vcs-testharness,spike
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fi
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if ! [ -n "$DV_TARGET" ]; then
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DV_TARGET=cv64a6_imafdc_sv39_hpdcache
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fi
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if ! [ -n "$UVM_VERBOSITY" ]; then
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export UVM_VERBOSITY=UVM_NONE
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fi
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export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
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cd verif/sim/
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errors=0
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# 64-bit configurations implementing MMU
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riscv_tests_list=(
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rv64ui-v-add
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rv64ui-v-ld
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rv64ui-v-sd
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rv64ui-v-beq
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rv64ui-v-jal
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)
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for t in ${riscv_tests_list[@]} ; do
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python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml --test $t --iss_yaml cva6.yaml --target ${DV_TARGET} --iss=$DV_SIMULATORS $DV_OPTS
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[[ $? > 0 ]] && ((errors++))
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done
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python3 cva6.py --target ${DV_TARGET} --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c \
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--gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" $DV_OPTS
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[[ $? > 0 ]] && ((errors++))
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make -C ../.. clean
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make clean_all
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[[ $errors > 0 ]] && exit 1 ;
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exit 0 ;
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@ -1,3 +1,4 @@
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#!/bin/bash
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# Copyright 2021 Thales DIS design services SAS
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#
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# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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@ -28,6 +29,11 @@ if ! [ -n "$DV_SIMULATORS" ]; then
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DV_SIMULATORS=veri-testharness,spike
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fi
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if [[ "$DV_TARGET" =~ cv64a6_imafdc* ]] ; then
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TESTLIST=../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml
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else
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TESTLIST=../tests/testlist_riscv-arch-test-$DV_TARGET.yaml
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fi
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cd verif/sim
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python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
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cd -
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python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
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@ -965,7 +965,7 @@ def load_config(args, cwd):
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if not args.custom_target:
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if not args.testlist:
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args.testlist = cwd + "/target/"+ args.target +"/testlist.yaml"
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if args.target == "cv64a6_imafdc_sv39":
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if args.target in ("cv64a6_imafdc_sv39", "cv64a6_imafdc_sv39_hpdcache", "cv64a6_imafdc_sv39_wb"):
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args.mabi = "lp64d"
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args.isa = "rv64gc_zba_zbb_zbs_zbc"
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elif args.target == "cv32a60x": # step1 configuration
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