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Complete Design Document (#1865)

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13
core/alu.sv
View file

@ -23,11 +23,16 @@ module alu
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input fu_data_t fu_data_i,
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
// Asynchronous reset active low - SUBSYSTEM
input logic rst_ni,
// FU data needed to execute instruction - ISSUE_STAGE
input fu_data_t fu_data_i,
// ALU result - ISSUE_STAGE
output riscv::xlen_t result_o,
output logic alu_branch_res_o
// ALU branch compare result - branch_unit
output logic alu_branch_res_o
);
riscv::xlen_t operand_a_rev;

30
core/branch_unit.sv
View file

@ -15,22 +15,34 @@
module branch_unit #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
// Asynchronous reset active low - SUBSYSTEM
input logic rst_ni,
// Debug mode state - CSR_REGFILE
input logic debug_mode_i,
// FU data needed to execute instruction - ISSUE_STAGE
input ariane_pkg::fu_data_t fu_data_i,
input logic [riscv::VLEN-1:0] pc_i, // PC of instruction
// Instruction PC - ISSUE_STAGE
input logic [riscv::VLEN-1:0] pc_i,
// Instruction is compressed - ISSUE_STAGE
input logic is_compressed_instr_i,
input logic fu_valid_i, // any functional unit is valid, check that there is no accidental mis-predict
// any functional unit is valid, check that there is no accidental mis-predict - TO_BE_COMPLETED
input logic fu_valid_i,
// Branch unit instruction is valid - ISSUE_STAGE
input logic branch_valid_i,
input logic branch_comp_res_i, // branch comparison result from ALU
// ALU branch compare result - ALU
input logic branch_comp_res_i,
// Brach unit result - ISSUE_STAGE
output logic [riscv::VLEN-1:0] branch_result_o,
input ariane_pkg::branchpredict_sbe_t branch_predict_i, // this is the address we predicted
output ariane_pkg::bp_resolve_t resolved_branch_o, // this is the actual address we are targeting
output logic resolve_branch_o, // to ID to clear that we resolved the branch and we can
// accept new entries to the scoreboard
output ariane_pkg::exception_t branch_exception_o // branch exception out
// Information of branch prediction - ISSUE_STAGE
input ariane_pkg::branchpredict_sbe_t branch_predict_i,
// Signaling that we resolved the branch - ISSUE_STAGE
output ariane_pkg::bp_resolve_t resolved_branch_o,
// Branch is resolved, new entries can be accepted by scoreboard - ID_STAGE
output logic resolve_branch_o,
// Branch exception out - TO_BE_COMPLETED
output ariane_pkg::exception_t branch_exception_o
);
logic [riscv::VLEN-1:0] target_address;
logic [riscv::VLEN-1:0] next_pc;

26
core/csr_buffer.sv
View file

@ -19,18 +19,24 @@ module csr_buffer
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
// Asynchronous reset active low - SUBSYSTEM
input logic rst_ni,
// Flush CSR - CONTROLLER
input logic flush_i,
// FU data needed to execute instruction - ISSUE_STAGE
input fu_data_t fu_data_i,
output logic csr_ready_o, // FU is ready e.g. not busy
input logic csr_valid_i, // Input is valid
output riscv::xlen_t csr_result_o,
input logic csr_commit_i, // commit the pending CSR OP
// to CSR file
output logic [11:0] csr_addr_o // CSR address to commit stage
// CSR FU is ready - ISSUE_STAGE
output logic csr_ready_o,
// CSR instruction is valid - ISSUE_STAGE
input logic csr_valid_i,
// CSR buffer result - ISSUE_STAGE
output riscv::xlen_t csr_result_o,
// commit the pending CSR OP - TO_BE_COMPLETED
input logic csr_commit_i,
// CSR address to write - COMMIT_STAGE
output logic [11:0] csr_addr_o
);
// this is a single entry store buffer for the address of the CSR
// which we are going to need in the commit stage

8
core/csr_regfile.sv
View file

@ -83,15 +83,15 @@ module csr_regfile
output riscv::xs_t vs_o,
// interrupt management to id stage - ID_STAGE
output irq_ctrl_t irq_ctrl_o,
// enable VA translation - EX_STAGE
// Enable virtual address translation - EX_STAGE
output logic en_translation_o,
// enable VA translation for load and stores - EX_STAGE
// Enable virtual address translation for load and stores - EX_STAGE
output logic en_ld_st_translation_o,
// Privilege level at which load and stores should happen - EX_STAGE
output riscv::priv_lvl_t ld_st_priv_lvl_o,
// TO_BE_COMPLETED - EX_STAGE
// Supervisor User Memory - EX_STAGE
output logic sum_o,
// TO_BE_COMPLETED - EX_STAGE
// Make Executable Readable - EX_STAGE
output logic mxr_o,
// TO_BE_COMPLETED - EX_STAGE
output logic [ riscv::PPNW-1:0] satp_ppn_o,

2
core/cva6.sv
View file

@ -131,7 +131,7 @@ module cva6
input logic time_irq_i,
// Debug (async) request - SUBSYSTEM
input logic debug_req_i,
// Probes to build RVFI, can be left open when not used - SUBSYSTEM
// Probes to build RVFI, can be left open when not used - RVFI
output rvfi_probes_t rvfi_probes_o,
// CVXIF request - SUBSYSTEM
output cvxif_req_t cvxif_req_o,

17
core/cvxif_fu.sv
View file

@ -15,22 +15,33 @@ module cvxif_fu
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
// Asynchronous reset active low - SUBSYSTEM
input logic rst_ni,
// FU data needed to execute instruction - ISSUE_STAGE
input fu_data_t fu_data_i,
// Current privilege mode - CSR_REGFILE
input riscv::priv_lvl_t priv_lvl_i,
//from issue
// CVXIF instruction is valid - ISSUE_STAGE
input logic x_valid_i,
// CVXIF is ready - ISSUE_STAGE
output logic x_ready_o,
// Offloaded instruction - ISSUE_STAGE
input logic [ 31:0] x_off_instr_i,
//to writeback
// CVXIF transaction ID - ISSUE_STAGE
output logic [TRANS_ID_BITS-1:0] x_trans_id_o,
// CVXIF exception - ISSUE_STAGE
output exception_t x_exception_o,
// CVXIF FU result - ISSUE_STAGE
output riscv::xlen_t x_result_o,
// CVXIF result valid - ISSUE_STAGE
output logic x_valid_o,
// CVXIF write enable - ISSUE_STAGE
output logic x_we_o,
//to coprocessor
// CVXIF request - SUBSYSTEM
output cvxif_pkg::cvxif_req_t cvxif_req_o,
// CVXIF response - SUBSYSTEM
input cvxif_pkg::cvxif_resp_t cvxif_resp_i
);
localparam X_NUM_RS = ariane_pkg::NR_RGPR_PORTS;

27
core/ex_stage.sv
View file

@ -26,7 +26,7 @@ module ex_stage
input logic rst_ni,
// Fetch flush request - CONTROLLER
input logic flush_i,
// TO_BE_COMPLETED - CSR_REGFILE
// Debug mode is enabled - CSR_REGFILE
input logic debug_mode_i,
// rs1 forwarding - ISSUE_STAGE
input logic [riscv::VLEN-1:0] rs1_forwarding_i,
@ -38,11 +38,11 @@ module ex_stage
input logic [riscv::VLEN-1:0] pc_i,
// Report whether isntruction is compressed - ISSUE_STAGE
input logic is_compressed_instr_i,
// TO_BE_COMPLETED - ISSUE_STAGE
// Fixed Latency Unit result - ISSUE_STAGE
output riscv::xlen_t flu_result_o,
// ID of the scoreboard entry at which a=to write back - ISSUE_STAGE
output logic [TRANS_ID_BITS-1:0] flu_trans_id_o,
// TO_BE_COMPLETED - ISSUE_STAGE
// Fixed Latency Unit exception - ISSUE_STAGE
output exception_t flu_exception_o,
// FLU is ready - ISSUE_STAGE
output logic flu_ready_o,
@ -62,7 +62,7 @@ module ex_stage
input logic csr_valid_i,
// CSR address to write - COMMIT_STAGE
output logic [11:0] csr_addr_o,
// TO_BE_COMPLETED - COMMIT_STAGE
// CSR commit - COMMIT_STAGE
input logic csr_commit_i,
// MULT instruction is valid - ISSUE_STAGE
input logic mult_valid_i,
@ -86,11 +86,11 @@ module ex_stage
output logic [TRANS_ID_BITS-1:0] store_trans_id_o,
// Exception generated by store instruction - ISSUE_STAGE
output exception_t store_exception_o,
// TO_BE_COMPLETED - COMMIT_STAGE
// LSU commit - COMMIT_STAGE
input logic lsu_commit_i,
// Commit queue ready to accept another commit request - COMMIT_STAGE
output logic lsu_commit_ready_o,
// TO_BE_COMPLETED - COMMIT_STAGE
// Commit transaction ID - COMMIT_STAGE
input logic [TRANS_ID_BITS-1:0] commit_tran_id_i,
// TO_BE_COMPLETED - ACC_DISPATCHER
input logic stall_st_pending_i,
@ -140,11 +140,11 @@ module ex_stage
input cvxif_pkg::cvxif_resp_t cvxif_resp_i,
// accelerate port result is valid - ACC_DISPATCHER
input logic acc_valid_i,
// TO_BE_COMPLETED - CSR_REGFILE
// Enable virtual memory translation - CSR_REGFILE
input logic enable_translation_i,
// TO_BE_COMPLETED - CSR_REGFILE
// Enable virtual memory translation for load/stores - CSR_REGFILE
input logic en_ld_st_translation_i,
// TO_BE_COMPLETED - CONTROLLER
// Flush TLB - CONTROLLER
input logic flush_tlb_i,
// Privilege mode - CSR_REGFILE
input riscv::priv_lvl_t priv_lvl_i,
@ -162,18 +162,17 @@ module ex_stage
input icache_arsp_t icache_areq_i,
// icache translation request - CACHE
output icache_areq_t icache_areq_o,
// TO_BE_COMPLETED - CACHE
// interface to dcache
// Data cache request ouput - CACHE
input dcache_req_o_t [2:0] dcache_req_ports_i,
// TO_BE_COMPLETED - CACHE
// Data cache request input - CACHE
output dcache_req_i_t [2:0] dcache_req_ports_o,
// TO_BE_COMPLETED - CACHE
// Write buffer is empty - CACHE
input logic dcache_wbuffer_empty_i,
// TO_BE_COMPLETED - CACHE
input logic dcache_wbuffer_not_ni_i,
// AMO request - CACHE
output amo_req_t amo_req_o,
// AMO response from cache - CACHE
// AMO response - CACHE
input amo_resp_t amo_resp_i,
// To count the instruction TLB misses - PERF_COUNTERS
output logic itlb_miss_o,

32
core/include/config_pkg.sv
View file

@ -46,15 +46,15 @@ package config_pkg;
int unsigned AxiIdWidth;
// AXI User width
int unsigned AxiUserWidth;
// TO_BE_COMPLETED
// Load buffer entry buffer
int unsigned NrLoadBufEntries;
// FPU is enabled
// Floating Point
bit FpuEn;
// TO_BE_COMPLETED
// Non standard 16bits Floating Point
bit XF16;
// TO_BE_COMPLETED
// Non standard 16bits Floating Point Alt
bit XF16ALT;
// TO_BE_COMPLETED
// Non standard 8bits Floating Point
bit XF8;
// Atomic RISC-V extension
bit RVA;
@ -66,33 +66,33 @@ package config_pkg;
bit RVC;
// Zcb RISC-V extension
bit RVZCB;
// TO_BE_COMPLETED
// Non standard Vector Floating Point
bit XFVec;
// CV-X-IF coprocessor interface is supported
bit CvxifEn;
// Zicond RISC-V extension is enabled
// Zicond RISC-V extension
bit ZiCondExtEn;
// Single precision FP RISC-V extension
bit RVF;
// Double precision FP RISC-V extension
bit RVD;
// Floating point is present
// Floating Point is present
bit FpPresent;
// TO_BE_COMPLETED
// Non standard Floating is Point present
bit NSX;
// TO_BE_COMPLETED
// Floating Point lenght
int unsigned FLen;
// Vector floating point extension
// Vector Floating Point extension
bit RVFVec;
// 16 bits vector floating point extension
// 16 bits vector Floating Point extension
bit XF16Vec;
// TO_BE_COMPLETED
// 16 bits vector Floating Point Alt extension
bit XF16ALTVec;
// 8 bits vector floating point extension
// 8 bits vector Floating Point extension
bit XF8Vec;
// TO_BE_COMPLETED
int unsigned NrRgprPorts;
// TO_BE_COMPLETED
// Function Unit write back port number
int unsigned NrWbPorts;
// Accelerate Port coprocessor interface
bit EnableAccelerator;
@ -144,7 +144,7 @@ package config_pkg;
logic [NrMaxRules-1:0][63:0] CachedRegionLength;
// Maximum number of outstanding stores
int unsigned MaxOutstandingStores;
// Debug mode
// Debug support
bit DebugEn;
// Non idem potency
bit NonIdemPotenceEn;

93
core/issue_read_operands.sv
View file

@ -20,69 +20,96 @@ module issue_read_operands
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type rs3_len_t = logic
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
// flush
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
// Asynchronous reset active low - SUBSYSTEM
input logic rst_ni,
// Flush - CONTROLLER
input logic flush_i,
// stall
// Stall inserted by Acc dispatcher - ACC_DISPATCHER
input logic stall_i,
// coming from decoder
// TO_BE_COMPLETED - TO_BE_COMPLETED
input scoreboard_entry_t issue_instr_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic [31:0] orig_instr_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic issue_instr_valid_i,
// Issue stage acknowledge - TO_BE_COMPLETED
output logic issue_ack_o,
// lookup rd in scoreboard
// rs1 operand address - scoreboard
output logic [REG_ADDR_SIZE-1:0] rs1_o,
// rs1 operand - scoreboard
input riscv::xlen_t rs1_i,
// rs1 operand is valid - scoreboard
input logic rs1_valid_i,
// rs2 operand address - scoreboard
output logic [REG_ADDR_SIZE-1:0] rs2_o,
// rs2 operand - scoreboard
input riscv::xlen_t rs2_i,
// rs2 operand is valid - scoreboard
input logic rs2_valid_i,
// rs3 operand address - scoreboard
output logic [REG_ADDR_SIZE-1:0] rs3_o,
// rs3 operand - scoreboard
input rs3_len_t rs3_i,
// rs3 operand is valid - scoreboard
input logic rs3_valid_i,
// get clobber input
// TO_BE_COMPLETED - TO_BE_COMPLETED
input fu_t [2**REG_ADDR_SIZE-1:0] rd_clobber_gpr_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input fu_t [2**REG_ADDR_SIZE-1:0] rd_clobber_fpr_i,
// To FU, just single issue for now
// TO_BE_COMPLETED - TO_BE_COMPLETED
output fu_data_t fu_data_o,
output riscv::xlen_t rs1_forwarding_o, // unregistered version of fu_data_o.operanda
output riscv::xlen_t rs2_forwarding_o, // unregistered version of fu_data_o.operandb
// Unregistered version of fu_data_o.operanda - TO_BE_COMPLETED
output riscv::xlen_t rs1_forwarding_o,
// Unregistered version of fu_data_o.operandb - TO_BE_COMPLETED
output riscv::xlen_t rs2_forwarding_o,
// Instruction pc - TO_BE_COMPLETED
output logic [riscv::VLEN-1:0] pc_o,
// Is compressed instruction - TO_BE_COMPLETED
output logic is_compressed_instr_o,
// ALU 1
input logic flu_ready_i, // Fixed latency unit ready to accept a new request
output logic alu_valid_o, // Output is valid
// Branches and Jumps
output logic branch_valid_o, // this is a valid branch instruction
// Fixed Latency Unit ready to accept new request - TO_BE_COMPLETED
input logic flu_ready_i,
// ALU output is valid - TO_BE_COMPLETED
output logic alu_valid_o,
// Branch instruction is valid - TO_BE_COMPLETED
output logic branch_valid_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output branchpredict_sbe_t branch_predict_o,
// LSU
input logic lsu_ready_i, // FU is ready
output logic lsu_valid_o, // Output is valid
// MULT
output logic mult_valid_o, // Output is valid
// FPU
input logic fpu_ready_i, // FU is ready
output logic fpu_valid_o, // Output is valid
output logic [1:0] fpu_fmt_o, // FP fmt field from instr.
output logic [2:0] fpu_rm_o, // FP rm field from instr.
// CSR
output logic csr_valid_o, // Output is valid
// CVXIF
// Load Store Unit is ready - TO_BE_COMPLETED
input logic lsu_ready_i,
// Load Store Unit result is valid - TO_BE_COMPLETED
output logic lsu_valid_o,
// Mult result is valid - TO_BE_COMPLETED
output logic mult_valid_o,
// FPU is ready - TO_BE_COMPLETED
input logic fpu_ready_i,
// FPU result is valid - TO_BE_COMPLETED
output logic fpu_valid_o,
// FPU fmt field from instruction - TO_BE_COMPLETED
output logic [1:0] fpu_fmt_o,
// FPU rm field from isntruction - TO_BE_COMPLETED
output logic [2:0] fpu_rm_o,
// CSR result is valid - TO_BE_COMPLETED
output logic csr_valid_o,
// CVXIF result is valid - TO_BE_COMPLETED
output logic cvxif_valid_o,
// CVXIF is ready - TO_BE_COMPLETED
input logic cvxif_ready_i,
// CVXIF offloaded instruction - TO_BE_COMPLETED
output logic [31:0] cvxif_off_instr_o,
// commit port
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_i,
output logic stall_issue_o // stall signal, we do not want to fetch any more entries
// committing instruction instruction
// from scoreboard
// input scoreboard_entry commit_instr_i,
// output logic commit_ack_o
// Stall signal, we do not want to fetch any more entries - TO_BE_COMPLETED
output logic stall_issue_o
);
logic stall;
logic fu_busy; // functional unit is busy

20
core/issue_stage.sv
View file

@ -47,15 +47,15 @@ module issue_stage
output [riscv::VLEN-1:0] rs2_forwarding_o,
// FU data useful to execute instruction - EX_STAGE
output fu_data_t fu_data_o,
// TO_BE_COMPLETED - EX_STAGE
// Program Counter - EX_STAGE
output logic [riscv::VLEN-1:0] pc_o,
// Is compressed instruction - EX_STAGE
output logic is_compressed_instr_o,
// TO_BE_COMPLETED - EX_STAGE
// Fixed Latency Unit is ready - EX_STAGE
input logic flu_ready_i,
// ALU FU is valid - EX_STAGE
output logic alu_valid_o,
// TO_BE_COMPLETED - EX_STAGE
// Signaling that we resolved the branch - EX_STAGE
input logic resolve_branch_i,
// Load store unit FU is ready - EX_STAGE
input logic lsu_ready_i,
@ -87,9 +87,9 @@ module issue_stage
output scoreboard_entry_t issue_instr_o,
// TO_BE_COMPLETED - ACC_DISPATCHER
output logic issue_instr_hs_o,
// TO_BE_COMPLETED - EX_STAGE
// Transaction ID - EX_STAGE
input logic [CVA6Cfg.NrWbPorts-1:0][TRANS_ID_BITS-1:0] trans_id_i,
// TO_BE_COMPLETED - EX_STAGE
// The branch engine uses the write back from the ALU - EX_STAGE
input bp_resolve_t resolved_branch_i,
// TO_BE_COMPLETED - EX_STAGE
input logic [CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] wbdata_i,
@ -97,19 +97,19 @@ module issue_stage
input exception_t [CVA6Cfg.NrWbPorts-1:0] ex_ex_i,
// TO_BE_COMPLETED - EX_STAGE
input logic [CVA6Cfg.NrWbPorts-1:0] wt_valid_i,
// TO_BE_COMPLETED - EX_STAGE
// CVXIF write enable - EX_STAGE
input logic x_we_i,
// TO_BE_COMPLETED - EX_STAGE
input logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_i,
// TO_BE_COMPLETED - EX_STAGE
input logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_i,
// TO_BE_COMPLETED - EX_STAGE
// GPR write enable - EX_STAGE
input logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_i,
// TO_BE_COMPLETED - EX_STAGE
// FPR write enable - EX_STAGE
input logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_i,
// TO_BE_COMPLETED - COMMIT_STAGE
// Instructions to commit - COMMIT_STAGE
output scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_o,
// TO_BE_COMPLETED - COMMIT_STAGE
// Commit acknowledge - COMMIT_STAGE
input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i,
// Issue stall - PERF_COUNTERS
output logic stall_issue_o,

96
core/load_store_unit.sv
View file

@ -19,65 +19,103 @@ module load_store_unit
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter int unsigned ASID_WIDTH = 1
) (
input logic clk_i,
input logic rst_ni,
input logic flush_i,
input logic stall_st_pending_i,
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
// Asynchronous reset active low - SUBSYSTEM
input logic rst_ni,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic flush_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic stall_st_pending_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output logic no_st_pending_o,
input logic amo_valid_commit_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic amo_valid_commit_i,
// FU data needed to execute instruction - ISSUE_STAGE
input fu_data_t fu_data_i,
// Load Store Unit is ready - ISSUE_STAGE
output logic lsu_ready_o,
// Load Store Unit instruction is valid - ISSUE_STAGE
input logic lsu_valid_i,
input fu_data_t fu_data_i,
output logic lsu_ready_o, // FU is ready e.g. not busy
input logic lsu_valid_i, // Input is valid
output logic [TRANS_ID_BITS-1:0] load_trans_id_o, // ID of scoreboard entry at which to write back
// Load transaction ID - ISSUE_STAGE
output logic [TRANS_ID_BITS-1:0] load_trans_id_o,
// Load result - ISSUE_STAGE
output riscv::xlen_t load_result_o,
// Load result is valid - ISSUE_STAGE
output logic load_valid_o,
output exception_t load_exception_o, // to WB, signal exception status LD exception
// Load exception - ISSUE_STAGE
output exception_t load_exception_o,
output logic [TRANS_ID_BITS-1:0] store_trans_id_o, // ID of scoreboard entry at which to write back
// Store transaction ID - ISSUE_STAGE
output logic [TRANS_ID_BITS-1:0] store_trans_id_o,
// Store result - ISSUE_STAGE
output riscv::xlen_t store_result_o,
// Store result is valid - ISSUE_STAGE
output logic store_valid_o,
output exception_t store_exception_o, // to WB, signal exception status ST exception
// Store exception - ISSUE_STAGE
output exception_t store_exception_o,
input logic commit_i, // commit the pending store
output logic commit_ready_o, // commit queue is ready to accept another commit request
// Commit the first pending store - TO_BE_COMPLETED
input logic commit_i,
// Commit queue is ready to accept another commit request - TO_BE_COMPLETED
output logic commit_ready_o,
// Commit transaction ID - TO_BE_COMPLETED
input logic [TRANS_ID_BITS-1:0] commit_tran_id_i,
input logic enable_translation_i, // enable virtual memory translation
input logic en_ld_st_translation_i, // enable virtual memory translation for load/stores
// Enable virtual memory translation - TO_BE_COMPLETED
input logic enable_translation_i,
// Enable virtual memory translation for load/stores - TO_BE_COMPLETED
input logic en_ld_st_translation_i,
// icache translation requests
// Instruction cache input request - CACHES
input icache_arsp_t icache_areq_i,
// Instruction cache output request - CACHES
output icache_areq_t icache_areq_o,
input riscv::priv_lvl_t priv_lvl_i, // From CSR register file
input riscv::priv_lvl_t ld_st_priv_lvl_i, // From CSR register file
input logic sum_i, // From CSR register file
input logic mxr_i, // From CSR register file
input logic [riscv::PPNW-1:0] satp_ppn_i, // From CSR register file
input logic [ ASID_WIDTH-1:0] asid_i, // From CSR register file
// Current privilege mode - CSR_REGFILE
input riscv::priv_lvl_t priv_lvl_i,
// Privilege level at which load and stores should happen - CSR_REGFILE
input riscv::priv_lvl_t ld_st_priv_lvl_i,
// Supervisor User Memory - CSR_REGFILE
input logic sum_i,
// Make Executable Readable - CSR_REGFILE
input logic mxr_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic [riscv::PPNW-1:0] satp_ppn_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic [ ASID_WIDTH-1:0] asid_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic [ ASID_WIDTH-1:0] asid_to_be_flushed_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic [riscv::VLEN-1:0] vaddr_to_be_flushed_i,
// TLB flush - CONTROLLER
input logic flush_tlb_i,
// Performance counters
// Instruction TLB miss - PERF_COUNTERS
output logic itlb_miss_o,
// Data TLB miss - PERF_COUNTERS
output logic dtlb_miss_o,
// interface to dcache
// Data cache request output - CACHES
input dcache_req_o_t [ 2:0] dcache_req_ports_i,
// Data cache request input - CACHES
output dcache_req_i_t [ 2:0] dcache_req_ports_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic dcache_wbuffer_empty_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic dcache_wbuffer_not_ni_i,
// AMO interface
// AMO request - CACHE
output amo_req_t amo_req_o,
// AMO response - CACHE
input amo_resp_t amo_resp_i,
// PMP
// PMP configuration - CSR_REGFILE
input riscv::pmpcfg_t [15:0] pmpcfg_i,
// PMP address - CSR_REGFILE
input logic [15:0][riscv::PLEN-3:0] pmpaddr_i,
//RVFI
// RVFI inforamtion - RVFI
output lsu_ctrl_t rvfi_lsu_ctrl_o,
// RVFI information - RVFI
output [riscv::PLEN-1:0] rvfi_mem_paddr_o
);
// data is misaligned

46
core/load_unit.sv
View file

@ -23,33 +23,51 @@ module load_unit
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
// Asynchronous reset active low - SUBSYSTEM
input logic rst_ni,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic flush_i,
// load unit input port
// Load unit input port - TO_BE_COMPLETED
input logic valid_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input lsu_ctrl_t lsu_ctrl_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output logic pop_ld_o,
// load unit output port
// Load unit result is valid - TO_BE_COMPLETED
output logic valid_o,
// Load transaction ID - TO_BE_COMPLETED
output logic [TRANS_ID_BITS-1:0] trans_id_o,
// Load result - TO_BE_COMPLETED
output riscv::xlen_t result_o,
// Load exception - TO_BE_COMPLETED
output exception_t ex_o,
// MMU -> Address Translation
output logic translation_req_o, // request address translation
output logic [riscv::VLEN-1:0] vaddr_o, // virtual address out
input logic [riscv::PLEN-1:0] paddr_i, // physical address in
input exception_t ex_i, // exception which may has happened earlier. for example: mis-aligned exception
input logic dtlb_hit_i, // hit on the dtlb, send in the same cycle as the request
input logic [riscv::PPNW-1:0] dtlb_ppn_i, // ppn on the dtlb, send in the same cycle as the request
// address checker
// Request address translation - TO_BE_COMPLETED
output logic translation_req_o,
// Virtual address - TO_BE_COMPLETED
output logic [riscv::VLEN-1:0] vaddr_o,
// Physical address - TO_BE_COMPLETED
input logic [riscv::PLEN-1:0] paddr_i,
// Excepted which appears before load - TO_BE_COMPLETED
input exception_t ex_i,
// Data TLB hit - lsu
input logic dtlb_hit_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic [riscv::PPNW-1:0] dtlb_ppn_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output logic [11:0] page_offset_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic page_offset_matches_i,
input logic store_buffer_empty_i, // the entire store-buffer is empty
// Store buffer is empty - TO_BE_COMPLETED
input logic store_buffer_empty_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic [TRANS_ID_BITS-1:0] commit_tran_id_i,
// D$ interface
// Data cache request out - CACHES
input dcache_req_o_t req_port_i,
// Data cache request in - CACHES
output dcache_req_i_t req_port_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic dcache_wbuffer_not_ni_i
);
enum logic [3:0] {

9
core/lsu_bypass.sv
View file

@ -28,16 +28,25 @@ module lsu_bypass
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
// Asynchronous reset active low - SUBSYSTEM
input logic rst_ni,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic flush_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input lsu_ctrl_t lsu_req_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic lsu_req_valid_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic pop_ld_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic pop_st_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output lsu_ctrl_t lsu_ctrl_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output logic ready_o
);

9
core/mult.sv
View file

@ -5,14 +5,23 @@ module mult
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
// Asynchronous reset active low - SUBSYSTEM
input logic rst_ni,
// Flush - CONTROLLER
input logic flush_i,
// FU data needed to execute instruction - ISSUE_STAGE
input fu_data_t fu_data_i,
// Mult instruction is valid - ISSUE_STAGE
input logic mult_valid_i,
// Mult result - ISSUE_STAGE
output riscv::xlen_t result_o,
// Mult result is valid - ISSUE_STAGE
output logic mult_valid_o,
// Mutl is ready - ISSUE_STAGE
output logic mult_ready_o,
// Mult transaction ID - ISSUE_STAGE
output logic [TRANS_ID_BITS-1:0] mult_trans_id_o
);
logic mul_valid;

11
core/multiplier.sv
View file

@ -20,16 +20,27 @@ module multiplier
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
// Asynchronous reset active low - SUBSYSTEM
input logic rst_ni,
// Multiplier transaction ID - Mult
input logic [TRANS_ID_BITS-1:0] trans_id_i,
// Multiplier instruction is valid - Mult
input logic mult_valid_i,
// Multiplier operation - Mult
input fu_op operation_i,
// A operand - Mult
input riscv::xlen_t operand_a_i,
// B operand - Mult
input riscv::xlen_t operand_b_i,
// Multiplier result - Mult
output riscv::xlen_t result_o,
// Mutliplier result is valid - Mult
output logic mult_valid_o,
// Multiplier FU is ready - Mult
output logic mult_ready_o,
// Multiplier transaction ID - Mult
output logic [TRANS_ID_BITS-1:0] mult_trans_id_o
);
// Carry-less multiplication

59
core/scoreboard.sv
View file

@ -16,56 +16,87 @@ module scoreboard #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type rs3_len_t = logic
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
// Asynchronous reset active low - SUBSYSTEM
input logic rst_ni,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output logic sb_full_o,
input logic flush_unissued_instr_i, // flush only un-issued instructions
input logic flush_i, // flush whole scoreboard
input logic unresolved_branch_i, // we have an unresolved branch
// list of clobbered registers to issue stage
// Flush only un-issued instructions - TO_BE_COMPLETED
input logic flush_unissued_instr_i,
// Flush whole scoreboard - TO_BE_COMPLETED
input logic flush_i,
// We have an unresolved branch - TO_BE_COMPLETED
input logic unresolved_branch_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output ariane_pkg::fu_t [2**ariane_pkg::REG_ADDR_SIZE-1:0] rd_clobber_gpr_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output ariane_pkg::fu_t [2**ariane_pkg::REG_ADDR_SIZE-1:0] rd_clobber_fpr_o,
// regfile like interface to operand read stage
// rs1 operand address - issue_read_operands
input logic [ariane_pkg::REG_ADDR_SIZE-1:0] rs1_i,
// rs1 operand - issue_read_operands
output riscv::xlen_t rs1_o,
// rs1 operand is valid - issue_read_operands
output logic rs1_valid_o,
// rs2 operand address - issue_read_operands
input logic [ariane_pkg::REG_ADDR_SIZE-1:0] rs2_i,
// rs2 operand - issue_read_operands
output riscv::xlen_t rs2_o,
// rs2 operand is valid - issue_read_operands
output logic rs2_valid_o,
// rs3 operand address - issue_read_operands
input logic [ariane_pkg::REG_ADDR_SIZE-1:0] rs3_i,
// rs3 operand - issue_read_operands
output rs3_len_t rs3_o,
// rs3 operand is valid - issue_read_operands
output logic rs3_valid_o,
// advertise instruction to commit stage, if commit_ack_i is asserted advance the commit pointer
// TO_BE_COMPLETED - TO_BE_COMPLETED
output ariane_pkg::scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i,
// instruction to put on top of scoreboard e.g.: top pointer
// we can always put this instruction to the top unless we signal with asserted full_o
// TO_BE_COMPLETED - TO_BE_COMPLETED
input ariane_pkg::scoreboard_entry_t decoded_instr_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic [31:0] orig_instr_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic decoded_instr_valid_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output logic decoded_instr_ack_o,
// instruction to issue logic, if issue_instr_valid and issue_ready is asserted, advance the issue pointer
// Issue scoreboard entry - ACC_DISPATCHER
output ariane_pkg::scoreboard_entry_t issue_instr_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output logic [31:0] orig_instr_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output logic issue_instr_valid_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic issue_ack_i,
// write-back port
// TO_BE_COMPLETED - TO_BE_COMPLETED
input ariane_pkg::bp_resolve_t resolved_branch_i,
input logic [CVA6Cfg.NrWbPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0] trans_id_i, // transaction ID at which to write the result back
input logic [CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] wbdata_i, // write data in
input ariane_pkg::exception_t [CVA6Cfg.NrWbPorts-1:0] ex_i, // exception from a functional unit (e.g.: ld/st exception)
input logic [CVA6Cfg.NrWbPorts-1:0] wt_valid_i, // data in is valid
input logic x_we_i, // cvxif we for writeback
// Transaction ID at which to write the result back - TO_BE_COMPLETED
input logic [CVA6Cfg.NrWbPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0] trans_id_i,
// Results to write back - TO_BE_COMPLETED
input logic [CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] wbdata_i,
// Exception from a functional unit (e.g.: ld/st exception) - TO_BE_COMPLETED
input ariane_pkg::exception_t [CVA6Cfg.NrWbPorts-1:0] ex_i,
// Indicates valid results - TO_BE_COMPLETED
input logic [CVA6Cfg.NrWbPorts-1:0] wt_valid_i,
// Cvxif we for writeback - TO_BE_COMPLETED
input logic x_we_i,
// RVFI
// TO_BE_COMPLETED - RVFI
output logic [ariane_pkg::TRANS_ID_BITS-1:0] rvfi_issue_pointer_o,
// TO_BE_COMPLETED - RVFI
output logic [CVA6Cfg.NrCommitPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0] rvfi_commit_pointer_o
);

18
core/serdiv.sv
View file

@ -22,21 +22,31 @@ module serdiv
parameter WIDTH = 64,
parameter STABLE_HANDSHAKE = 0 // Guarantee a stable in_rdy_o during the input handshake. Keep it at 0 in CVA6
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
// Asynchronous reset active low - SUBSYSTEM
input logic rst_ni,
// input IF
// Serdiv translation ID - Mult
input logic [TRANS_ID_BITS-1:0] id_i,
// A operand - Mult
input logic [WIDTH-1:0] op_a_i,
// B operand - Mult
input logic [WIDTH-1:0] op_b_i,
// Serdiv operation - Mult
input logic [1:0] opcode_i, // 0: udiv, 2: urem, 1: div, 3: rem
// handshake
input logic in_vld_i, // there is a cycle delay from in_rdy_o->in_vld_i, see issue_read_operands.sv stage
// Serdiv instruction is valid - Mult
input logic in_vld_i,
// Serdiv FU is ready - Mult
output logic in_rdy_o,
// Flush - CONTROLLER
input logic flush_i,
// output IF
// Serdiv result is valid - Mult
output logic out_vld_o,
// Serdiv is ready - Mult
input logic out_rdy_i,
// Serdiv transaction ID - Mult
output logic [TRANS_ID_BITS-1:0] id_o,
// Serdiv result - Mult
output logic [WIDTH-1:0] res_o
);

45
core/store_unit.sv
View file

@ -18,38 +18,61 @@ module store_unit
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
// Asynchronous reset active low - SUBSYSTEM
input logic rst_ni,
// Flush - CONTROLLER
input logic flush_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic stall_st_pending_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output logic no_st_pending_o,
// Store buffer is empty - TO_BE_COMPLETED
output logic store_buffer_empty_o,
// store unit input port
// Store instruction is valid - ISSUE_STAGE
input logic valid_i,
// Data input - ISSUE_STAGE
input lsu_ctrl_t lsu_ctrl_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output logic pop_st_o,
// Instruction commit - TO_BE_COMPLETED
input logic commit_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output logic commit_ready_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic amo_valid_commit_i,
// store unit output port
// Store result is valid - ISSUE_STAGE
output logic valid_o,
// Transaction ID - ISSUE_STAGE
output logic [TRANS_ID_BITS-1:0] trans_id_o,
// Store result - ISSUE_STAGE
output riscv::xlen_t result_o,
// Store exception output - TO_BE_COMPLETED
output exception_t ex_o,
// MMU -> Address Translation
output logic translation_req_o, // request address translation
output logic [riscv::VLEN-1:0] vaddr_o, // virtual address out
// Address translation request - TO_BE_COMPLETED
output logic translation_req_o,
// Virtual address - TO_BE_COMPLETED
output logic [riscv::VLEN-1:0] vaddr_o,
// RVFI information - RVFI
output [riscv::PLEN-1:0] rvfi_mem_paddr_o,
input logic [riscv::PLEN-1:0] paddr_i, // physical address in
// Physical address - TO_BE_COMPLETED
input logic [riscv::PLEN-1:0] paddr_i,
// Exception raised before store - TO_BE_COMPLETED
input exception_t ex_i,
input logic dtlb_hit_i, // will be one in the same cycle translation_req was asserted if it hits
// address checker
// Data TLB hit - lsu
input logic dtlb_hit_i,
// Address to be checked - load_unit
input logic [11:0] page_offset_i,
// Address check result - load_unit
output logic page_offset_matches_o,
// D$ interface
// AMO request - CACHES
output amo_req_t amo_req_o,
// AMO response - CACHES
input amo_resp_t amo_resp_i,
// Data cache request - CACHES
input dcache_req_o_t req_port_i,
// Data cache response - CACHES
output dcache_req_i_t req_port_o
);
// it doesn't matter what we are writing back as stores don't return anything

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84
docs/04_cv32a65x_design/source/cv32a6_execute.rst
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@ -9,8 +9,7 @@ Description
***********
The EX_STAGE module is a logical stage which implements the execute stage.
It encapsulates the following functional units:
ALU, Branch Unit, CSR buffer, Mult, load and store and CVXIF.
It encapsulates the following functional units: ALU, Branch Unit, CSR buffer, Mult, load and store and CVXIF.
The module is connected to:
@ -37,28 +36,38 @@ Submodules
EX_STAGE submodules
ALU
alu
===
TO BE COMPLETED
The arithmetic logic unit (ALU) is a small piece of hardware which performs 32 and 64-bit arithmetic and bitwise operations: subtraction, addition, shifts, comparisons...
It always completes its operation in a single cycle.
.. include:: port_alu.rst
Branch Unit
branch_unit
===========
TO BE COMPLETED
The branch unit module manages all kinds of control flow changes i.e.: conditional and unconditional jumps.
It calculates the target address and decides whether to take the branch or not.
It also decides if a branch was mis-predicted or not and reports corrective actions to the pipeline stages.
.. include:: port_branch_unit.rst
CSR Buffer
CSR_buffer
==========
TO BE COMPLETED
The CSR buffer module stores the CSR address at which the instruction is going to read/write.
As the CSR instruction alters the processor architectural state, this instruction has to be buffered until the commit stage decides to execute the instruction.
.. include:: port_csr_buffer.rst
Mult
mult
====
TO BE COMPLETED
The multiplier module supports the division and multiplication operations.
.. figure:: ../images/mult_modules.png
:name: mult submodules
@ -67,24 +76,35 @@ TO BE COMPLETED
mult submodules
.. include:: port_mult.rst
----------
multiplier
----------
TO BE COMPLETED
Multiplication is performed in two cycles and is fully pipelined.
.. include:: port_multiplier.rst
------
serdiv
------
TO BE COMPLETED
The division is a simple serial divider which needs 64 cycles in the worst case.
.. include:: port_serdiv.rst
Load Store Unit (LSU)
load_store_unit (LSU)
=====================
TO BE COMPLETED
The load store module interfaces with the data cache (D$) to manage the load and store operations.
The LSU does not handle misaligned accesses.
Misaligned accesses are double word accesses which are not aligned to a 64-bit boundary, word accesses which are not aligned to a 32-bit boundary and half word accesses which are not aligned on 16-bit boundary.
If the LSU encounters a misaligned load or store, it throws a misaligned exception.
.. figure:: ../images/load_store_unit_modules.png
:name: load_store_unit submodules
@ -93,18 +113,44 @@ TO BE COMPLETED
load_store_unit submodules
.. include:: port_load_store_unit.rst
----------
store_unit
----------
TO BE COMPLETED
The store_unit module manages the data store operations.
As stores can be speculative, the store instructions need to be committed by ISSUE_STAGE module before possibily altering the processor state.
Store buffer keeps track of store requests.
Outstanding store instructions (which are speculative) are differentiated from committed stores.
When ISSUE_STAGE module commits a store instruction, outstanding stores
become committed.
When commit buffer is not empty, the buffer automatically tries to write the oldest store to the data cache.
Furthermore, the store_unit module provides information to the load_unit to know if an outstanding store matches addresses with a load.
.. include:: port_store_unit.rst
---------
load unit
load_unit
---------
TO BE COMPLETED
The load_unit module manages the data load operations.
Before issuing a load, the load unit needs to check the store buffer for potential aliasing.
It inserts stalls until it can satisfy the current request. This means:
* Two loads to the same address are allowed.
* Two stores to the same address are allowed.
* A store followed by a load to the same address can only be satisfied if the store has already been committed (marked as committed in the store buffer).
.. TO_BE_COMPLETED, But once the store is committed, do we do forwarding without waiting for the store to actually be finished? Or do we authorize the outcome of the load, which will be carried out in memory/cache?
.. include:: port_load_unit.rst
----------
@ -113,9 +159,13 @@ lsu_bypass
TO BE COMPLETED
.. include:: port_lsu_bypass.rst
CVXIF_fu
========
TO BE COMPLETED
.. include:: port_cvxif_fu.rst

137
docs/04_cv32a65x_design/source/cv32a6_frontend.rst
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@ -18,16 +18,11 @@ Description
The FRONTEND module implements two first stages of the cva6 pipeline,
PC gen and Fetch stages.
PC gen stage is responsible for generating the next program counter
hosting a Branch Target Buffer (BTB) a Branch History Table (BHT) and
a Return Address Stack (RAS) to speculate on the branch target address.
PC gen stage is responsible for generating the next program counter.
It hosts a Branch Target Buffer (BTB), a Branch History Table (BHT) and a Return Address Stack (RAS) to speculate on control flow instructions.
Fetch stage requests data to the CACHE module, realigns the data to
store them in instruction queue and transmits the instructions to the
DECODE module.
FRONTEND can fetch up to 2 instructions per cycles when
C extension instructions is used, but as instruction queue limits the
data rate, up to one instruction per cycle can be sent to DECODE.
Fetch stage requests data to the CACHE module, realigns the data to store them in instruction queue and transmits the instructions to the DECODE module.
FRONTEND can fetch up to 2 instructions per cycles when C extension instructions is enabled, but DECODE module decodes up to one instruction per cycles.
The module is connected to:
@ -51,40 +46,58 @@ PC gen generates the next program counter. The next PC can originate from the fo
* **Branch Predict:** Fetched instruction is predecoded thanks to instr_scan submodule. When instruction is a control flow, three cases need to be considered:
+ 1) If instruction is a JALR and BTB (Branch Target Buffer) returns a valid address, next PC is predicted by BTB. Else JALR is not considered as a control flow instruction, which will generate a mispredict.
+ 1) If instruction is a JALR and BTB (Branch Target Buffer) returns a valid address, next PC is predicted by BTB.
Else JALR is not considered as a control flow instruction, which will generate a mispredict.
+ 2) If instruction is a branch and BTH (Branch History table) returns a valid address, next PC is predicted by BHT. Else branch is not considered as an control flow instruction, which will generate a mispredict when branch is taken.
+ 3) If instruction is a RET and RAS (Return Address Stack) returns a valid address and RET has already been consummed by instruction queue. Else RET is considered as a control flow instruction but next PC is not predicted. A mispredict wil be generated.
+ 3) If instruction is a RET and RAS (Return Address Stack) returns a valid address and RET has already been consummed by instruction queue.
Else RET is considered as a control flow instruction but next PC is not predicted.
A mispredict wil be generated.
Then the PC gen informs the Fetch stage that it performed a prediction on the PC. *In CV32A6 v0.1.0, Branch Prediction is simplified: no information is stored in BTB, BHT and RAS. JALR, branch and RET instructions are not considered as control flow instruction and will generates mispredict.*
Then the PC gen informs the Fetch stage that it performed a prediction on the PC. *In CV32A6 v0.1.0, Branch Prediction is simplified: no information is stored in BTB, BHT and RAS.
JALR, branch and RET instructions are not considered as control flow instruction and will generates mispredict.*
* **Default:** PC + 4 is fetched. PC Gen always fetches on a word boundary (32-bit). Compressed instructions are handled by fetch stage.
* **Mispredict:** When a branch prediction is mispredicted, the EXECUTE feedbacks a misprediction. This can either be a 'real' mis-prediction or a branch which was not recognized as one. In any case we need to correct our action and start fetching from the correct address.
* **Mispredict:** When a branch prediction is mispredicted, the EXECUTE feedbacks a misprediction. This can either be a 'real' mis-prediction or a branch which was not recognized as one.
In any case we need to correct our action and start fetching from the correct address.
* **Replay instruction fetch:** When the instruction queue is full, the instr_queue submodule asks the fetch replay and provides the address to be replayed.
* **Return from environment call:** When CSR asks a return from an environment call, the PC is assigned to the successive PC to the one stored in the CSR [m-s]epc register.
* **Exception/Interrupt:** If an exception (or interrupt, which is in the context of RISC-V subsystems quite similar) is triggered by the COMMIT, the next PC Gen is assigned to the CSR trap vector base address. The trap vector base address can be different depending on whether the exception traps to S-Mode or M-Mode (user mode exceptions are currently not supported). It is the purpose of the CSR Unit to figure out where to trap to and present the correct address to PC Gen.
* **Exception/Interrupt:** If an exception (or interrupt, which is in the context of RISC-V subsystems quite similar) is triggered by the COMMIT, the next PC Gen is assigned to the CSR trap vector base address.
The trap vector base address can be different depending on whether the exception traps to S-Mode or M-Mode (user mode exceptions are currently not supported).
It is the purpose of the CSR Unit to figure out where to trap to and present the correct address to PC Gen.
* **Pipeline Flush:** When a CSR with side-effects gets written the whole pipeline is flushed by CONTROLLER and FRONTEND starts fetching from the next instruction again in order to take the up-dated information into account (for example virtual memory base pointer changes). The PC related to the flush action is provided by the COMMIT. Moreover flush is also transmitted to the CACHES through the next fetch CACHES access and instruction queue is reset.
* **Pipeline Flush:** When a CSR with side-effects gets written the whole pipeline is flushed by CONTROLLER and FRONTEND starts fetching from the next instruction again in order to take the up-dated information into account (for example virtual memory base pointer changes).
The PC related to the flush action is provided by the COMMIT.
Moreover flush is also transmitted to the CACHES through the next fetch CACHES access and instruction queue is reset.
* **Debug:** Debug has the highest order of precedence as it can interrupt any control flow requests. It also the only source of control flow change which can actually happen simultaneously to any other of the forced control flow changes. The debug jump is requested by CSR. The address to be jumped into is HW coded. This debug feature is not supported by CV32A6 v0.1.0.
* **Debug:** Debug has the highest order of precedence as it can interrupt any control flow requests. It also the only source of control flow change which can actually happen simultaneously to any other of the forced control flow changes.
The debug jump is requested by CSR.
The address to be jumped into is HW coded.
This debug feature is not supported by CV32A6 v0.1.0.
All program counters are logical addressed. If the logical to physical mapping changes a fence.vm instruction should used to flush the pipeline *and TLBs (MMU is not enabled in CV32A6 v0.1.0)*.
All program counters are logical addressed.
If the logical to physical mapping changes, a ``fence.vm`` instruction should be used to flush the pipeline *and TLBs (MMU is not enabled in CV32A6 v0.1.0)*.
Fetch Stage
~~~~~~~~~~~
Fetch stage controls by handshake protocol the CACHE module. Fetched data are 32-bit block with word aligned address. A granted fetch is realigned into instr_realign submodule to produce instructions. Then instructions are pushed into an internal instruction FIFO called instruction queue (instr_queue submodule). This submodule stores the instructions and related information which allow to identify the outstanding transactions. In the case CONTROLLER decides to flush the instruction queue, the outstanding transactions are discarded.
Fetch stage controls the CACHE module by a handshaking protocol.
Fetched data is a 32-bit block with a word-aligned address.
A granted fetch is processed by the instr_realign submodule to produce instructions.
Then instructions are pushed into an internal instruction FIFO called instruction queue (instr_queue submodule).
This submodule stores the instructions and sends them to the DECODE module.
*The Fetch stage asks the MMU (MMU is not enabled in CV32A6 v0.1.0) to translate the requested address.*
.. TO_BE_COMPLETED MMU also feedback an exception, but not present in 65X
Memory *and MMU (MMU is not enabled in CV32A6 v0.1.0)* can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults.
Memory can feedback potential exceptions generated by the memory fetch request.
They can be bus errors, invalid accesses or instruction page faults.
@ -102,7 +115,13 @@ Submodules
Instr_realign submodule
~~~~~~~~~~~~~~~~~~~~~~~
The 32-bit aligned block coming from the CACHE module enters the instr_realign submodule. This submodule extracts the instructions from the 32-bit blocks, up to two instructions because it is possible to fetch two instructions when C extension is used. If the instructions are not compressed, it is possible that the instruction is not aligned on the block size but rather interleaved with two cache blocks. In that case, two cache accesses are needed. The instr_realign submodule provides at maximum one instruction per cycle. Not complete instruction is stored in instr_realign submodule before being provided in the next cycles.
The 32-bit aligned block coming from the CACHE module enters the instr_realign submodule.
This submodule extracts the instructions from the 32-bit blocks.
It is possible to fetch up to two instructions per cycle when C extension is used.
An not-compressed instruction can be misaligned on the block size, interleaved with two cache blocks.
In that case, two cache accesses are needed to get the whole instruction.
The instr_realign submodule provides at maximum two instructions per cycle when compressed extensionis enabled, else one instruction per cycle.
Incomplete instruction is stored in instr_realign submodule until its second half is fetched.
In case of mispredict, flush, replay or branch predict, the instr_realign is re-initialized, the internal register storing the instruction alignment state is reset.
@ -112,7 +131,9 @@ In case of mispredict, flush, replay or branch predict, the instr_realign is re-
Instr_queue submodule
~~~~~~~~~~~~~~~~~~~~~
The instr_queue receives 32bit block from CACHES to create a valid stream of instructions to be decoded (by DECODE), to be issued (by ISSUE) and executed (by EXECUTE). FRONTEND pushes in FIFO to store the instructions and related information needed in case of mispredict or exception: instructions, instruction control flow type, exception, exception address and predicted address. DECODE pops them when decode stage is ready and indicates to the FRONTEND the instruction has been consummed.
The instr_queue receives mutliple instructions from instr_realign submodule to create a valid stream of instructions to be decoded (by DECODE), to be issued (by ISSUE) and executed (by EXECUTE).
FRONTEND pushes in FIFO to store the instructions and related information needed in case of mispredict or exception: instructions, instruction control flow type, exception, exception address and predicted address.
DECODE pops them when decode stage is ready and indicates to the FRONTEND the instruction has been consummed.
The instruction queue contains max 4 instructions.
@ -125,10 +146,14 @@ The instruction queue can be flushed by CONTROLLER.
.. include:: port_instr_queue.rst
Instr_scan submodule
instr_scan submodule
~~~~~~~~~~~~~~~~~~~~
The instr_scan submodule pre-decodes the fetched instructions, instructions could be compressed or not. The outputs are used by the branch prediction feature. The instr_scan submodule tells if the instruction is compressed and provides the intruction type: branch, jump, return, jalr, imm, call or others.
When compressed extnsino is enabled, two instr_scan are instantiated to handle up to two instructions per cycle.
Each instr_scan submodule pre-decodes the fetched instructions coming from the instr_realign module, instructions could be compressed or not.
The instr_scan submodule is a flox controler which provides the intruction type: branch, jump, return, jalr, imm, call or others.
These outputs are used by the branch prediction feature.
.. include:: port_instr_scan.rst
@ -141,13 +166,13 @@ BHT (Branch History Table) submodule
When a branch instruction is resolved by the EXECUTE, the relative
information is stored in the Branch History Table.
The information is stored in a 1024 entry table.
The information is stored in a *BHTDepth configuration parameter* entry table.
The Branch History table is a two-bit saturation counter that takes the
virtual address of the current fetched instruction by the CACHE.
.. TO_BE_COMPLETED: Specify the behaviour when BHT is saturated
The Branch History Table is a table of two-bit saturating counters that takes the virtual address of the current fetched instruction by the CACHE.
It states whether the current branch request should be taken or not.
The two bit counter is updated by the successive execution of the current
instructions as shown in the following figure.
The two bit counter is updated by the successive execution of the instructions as shown in the following figure.
.. figure:: ../images/bht.png
:name: BHT saturation
@ -156,55 +181,57 @@ instructions as shown in the following figure.
BHT saturation
The BHT is not updated if processor is in debug mode.
.. TO_BE_COMPLETED if debug enable, The BHT is not updated if processor is in debug mode.
When a branch instruction is pre-decoded by instr_scan submodule, the BHT
informs whether the PC address is in the BHT. In this case, the BHT
predicts whether the branch is taken and provides the corresponding target
address.
When a branch instruction is pre-decoded by instr_scan submodule, the BHT valids whether the PC address is in the BHT and provides the taken or not prediction.
The BHT is never flushed.
.. include:: port_bht.rst
BTB (Branch Target Buffer) submodule
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. As BTB is unsed in cv32a65x, comment the chapter
BTB (Branch Target Buffer) submodule
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
When a unconditional jumps to a register (JALR instruction) is mispredicted
by the EXECUTE, the relative information is stored into the BTB, that is
to say the JALR PC and the target address.
When an JALR instruction jump to a register is mispredicted by the EXECUTE module, the JALR PC and the target address are stored into the BTB.
The information is stored in a 8 entry table.
The information is stored in a *BTBDepth configuration parameter* entry table.
The BTB is not updated if processor is in debug mode.
.. TO_BE_COMPLETED: Specify the behaviour when BTB is saturated
When a branch instruction is pre-decoded by instr_scan submodule, the BTB
informs whether the input PC address is in BTB. In this case, the BTB
provides the corresponding target address.
.. TO_BE_COMPLETED when debug enabled, The BTB is not updated if processor is in debug mode.
The BTB is never flushed.
When a JALR instruction is pre-decoded by instr_scan submodule, the BTB informs whether the input PC address is in the BTB.
In this case, the BTB provides the predicted target address.
.. include:: port_btb.rst
The BTB is never flushed.
.. include:: port_btb.rst
RAS (Return Address Stack) submodule
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
RAS is implemented as a FIFO which is composed of *RASDepth configuration parameter* entries.
When an unconditional jumps to a known target address (JAL instruction)
is consummed by the instr_queue, the next pc after the JAL instruction
and the return address are stored into a FIFO.
A JAL instruction pushes the return address onto the RAS only when rd=x1 or rd=x5.
The RAS FIFO depth is 2.
When a branch instruction is pre-decoded by instr_scan submodule, the
RAS informs whether the input PC address is in RAS. In this case, the
RAS provides the corresponding target address.
JALR instruction pushes/pops a RAS as follows.
In the below, *link* is true when the register is either x1 or x5.
* when rd=!link and rs1=!link, none
* when rd=!link and rs1=link, pop
* when rd=link and rs1=!link, push
* when rd=link and rs1=link and rd!=rs1, pop then push
* when rd=link and rs1=link and rd=rs1, push
The RAS is never flushed.
Mispredicted JAL or JALR instructions must not alter the RAS content.
.. TO_BE_COMPLETED: Specify the behaviour when RAS is saturated
.. include:: port_ras.rst

8
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@ -15,7 +15,13 @@ COMMIT_STAGE Module
Description
-----------
The COMMIT_STAGE module implements ... TO BE COMPLETED
The COMMIT_STAGE module implements the commit stage, which is the last stage in the processor’s pipeline.
For the instructions for which the execution is completed, it updates the architectural state: writing CSR registers, committing stores and writing back data to the register file.
The commit stage controls the stalling and the flushing of the processor.
The commit stage also manages the exceptions.
An exception can occur during the first four pipeline stages (PCgen cannot generate an exception) or happen in commit stage, coming from the CSR_REGFILE or from an interrupt.
Exceptions are precise: they are considered during the commit only and associated with the related instruction.
The module is connected to:

13
docs/04_cv32a65x_design/source/cva6_id_stage.rst
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@ -66,17 +66,14 @@ All compressed instructions have a 32-bit equivalent.
Decoder
~~~~~~~
The decoder module takes the output of compressed_decoder module and decodes
it.
It transforms the instruction to the most fundamental control structure
in pipeline, a scoreboard entry.
The decoder module takes the output of compressed_decoder module and decodes it.
It transforms the instruction to the most fundamental control structure in pipeline, a scoreboard entry.
The scoreboard entry contains an exception entry which is composed of a
valid field, a cause and a value called TVAL.
The scoreboard entry contains an exception entry which is composed of a valid field, a cause and a value called TVAL.
As TVALEn configuration parameter is zero, the TVAL field is not implemented.
A potential illegal instruction exception can be detected during decoding.
If no exception has happened previously in fetch stage, the decoder will
valid the exception and add the cause and tval value to the scoreboard entry.
If no exception has happened previously in fetch stage, the decoder will valid the exception and add the cause and tval value to the scoreboard entry.
.. include:: port_decoder.rst

14
docs/04_cv32a65x_design/source/cva6_issue_stage.rst
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@ -15,15 +15,11 @@ ISSUE_STAGE Module
Description
-----------
The execution can be roughly divided into four parts: issue(1),
read operands(2), execute(3) and write-back(4).
The execution can be roughly divided into four parts: issue(1), read operands(2), execute(3) and write-back(4).
The ISSUE_STAGE module handles step one, two and four.
The ISSUE_STAGE module receives the decoded instructions and issues them
to the various functional units.
The ISSUE_STAGE module receives the decoded instructions and issues them to the various functional units.
A data-structure called scoreboard is used to keep track of data related
to the issue instruction: which functional unit it is in and which
register it will write-back to.
A data structure called scoreboard is used to keep track of data related to the issue instruction: which functional unit and which destination register they are.
The scoreboard handle the write-back data received from the COMMIT_STAGE module.
Furthermore it contains the CPU’s register file.
@ -54,7 +50,9 @@ Submodules
Scoreboard
~~~~~~~~~~
TO BE COMPLETED
The scoreboard contains a FIFO to store the decoded instructions.
Issued instruction is pushed to the FIFO if it is not full.
It indicates which registers are going to be clobbered by a previously issued instruction.
.. include:: port_scoreboard.rst

15
docs/04_cv32a65x_design/source/mmu.rst
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@ -15,7 +15,10 @@ The Memory Management Unit (MMU) SV32 module is a crucial component in the RISC-
**Figure 1:** Inputs and Outputs of CVA6 MMU SV32
At its core, the MMU SV32 plays a pivotal role in translating virtual addresses into their corresponding physical counterparts. This translation process is paramount for providing memory protection, isolation, and efficient memory management in modern computer systems. Importantly, it handles both instruction and data accesses, ensuring a seamless interaction between the processor and virtual memory. Within the MMU, several major blocks play pivotal roles in this address translation process. These includes:
At its core, the MMU SV32 plays a pivotal role in translating virtual addresses into their corresponding physical counterparts.
This translation process is paramount for providing memory protection, isolation, and efficient memory management in modern computer systems.
Importantly, it handles both instruction and data accesses, ensuring a seamless interaction between the processor and virtual memory.
Within the MMU, several major blocks play pivotal roles in this address translation process. These includes:
* Instruction TLB (ITLB)
* Data TLB (DTLB)
@ -30,15 +33,19 @@ At its core, the MMU SV32 plays a pivotal role in translating virtual addresses
**Figure 2:** Major Blocks in CVA6 MMU SV32
The MMU SV32 manages privilege levels and access control, enforcing permissions for user and supervisor modes while handling access exceptions. It employs Translation Lookaside Buffers (TLBs) for efficient address translation, reducing the need for page table access. TLB hits yield quick translations, but on misses, the shared TLB is consulted, and if necessary, the Page Table Walker (PTW) performs page table walks, updating TLBs and managing exceptions during the process.
The MMU SV32 manages privilege levels and access control, enforcing permissions for user and supervisor modes while handling access exceptions.
It employs Translation Lookaside Buffers (TLBs) for efficient address translation, reducing the need for page table access.
TLB hits yield quick translations, but on misses, the shared TLB is consulted, and if necessary, the Page Table Walker (PTW) performs page table walks, updating TLBs and managing exceptions during the process.
In addition to these functionalities, the MMU SV32 seamlessly integrates support for Physical Memory Protection (PMP), enabling it to enforce access permissions and memory protection configurations as specified by the PMP settings. This additional layer of security and control enhances the management of memory accesses
In addition to these functionalities, the MMU SV32 seamlessly integrates support for Physical Memory Protection (PMP), enabling it to enforce access permissions and memory protection configurations as specified by the PMP settings.
This additional layer of security and control enhances the management of memory accesses
.. raw:: html
<span style="font-size:18px; font-weight:bold;">Instruction and Data Interfaces</span>
The MMU SV32 maintains interfaces with the instruction cache (ICache) and the load-store unit (LSU). It receives virtual addresses from these components and proceeds to translate them into physical addresses, a fundamental task for ensuring proper program execution and memory access.
The MMU SV32 maintains interfaces with the instruction cache (ICache) and the load-store unit (LSU).
It receives virtual addresses from these components and proceeds to translate them into physical addresses, a fundamental task for ensuring proper program execution and memory access.
.. raw:: html

32
docs/04_cv32a65x_design/source/parameters_cv32a65x.rst
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@ -37,23 +37,23 @@
- 32
* - NrLoadBufEntries
- TO_BE_COMPLETED
- Load buffer entry buffer
- 1
* - FpuEn
- FPU is enabled
- Floating Point
- 0
* - XF16
- TO_BE_COMPLETED
- Non standard 16bits Floating Point
- 0
* - XF16ALT
- TO_BE_COMPLETED
- Non standard 16bits Floating Point Alt
- 0
* - XF8
- TO_BE_COMPLETED
- Non standard 8bits Floating Point
- 0
* - RVA
@ -77,7 +77,7 @@
- 1
* - XFVec
- TO_BE_COMPLETED
- Non standard Vector Floating Point
- 0
* - CvxifEn
@ -85,7 +85,7 @@
- 1
* - ZiCondExtEn
- Zicond RISC-V extension is enabled
- Zicond RISC-V extension
- 0
* - RVF
@ -97,31 +97,31 @@
- 0
* - FpPresent
- Floating point is present
- Floating Point is present
- 0
* - NSX
- TO_BE_COMPLETED
- Non standard Floating is Point present
- 0
* - FLen
- TO_BE_COMPLETED
- Floating Point lenght
- 0
* - RVFVec
- Vector floating point extension
- Vector Floating Point extension
- 0
* - XF16Vec
- 16 bits vector floating point extension
- 16 bits vector Floating Point extension
- 0
* - XF16ALTVec
- TO_BE_COMPLETED
- 16 bits vector Floating Point Alt extension
- 0
* - XF8Vec
- 8 bits vector floating point extension
- 8 bits vector Floating Point extension
- 0
* - NrRgprPorts
@ -129,7 +129,7 @@
- 0
* - NrWbPorts
- TO_BE_COMPLETED
- Function Unit write back port number
- 0
* - EnableAccelerator
@ -233,7 +233,7 @@
- 7
* - DebugEn
- Debug mode
- Debug support
- 0
* - NonIdemPotenceEn

51
docs/04_cv32a65x_design/source/port_alu.rst Normal file
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@ -0,0 +1,51 @@
..
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
.. _CVA6_alu_ports:
.. list-table:: **alu module** IO ports
:header-rows: 1
* - Signal
- IO
- Description
- connexion
- Type
* - ``clk_i``
- in
- Subsystem Clock
- SUBSYSTEM
- logic
* - ``rst_ni``
- in
- Asynchronous reset active low
- SUBSYSTEM
- logic
* - ``fu_data_i``
- in
- FU data needed to execute instruction
- ISSUE_STAGE
- fu_data_t
* - ``result_o``
- out
- ALU result
- ISSUE_STAGE
- riscv::xlen_t
* - ``alu_branch_res_o``
- out
- ALU branch compare result
- branch_unit
- logic

3
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@ -9,7 +9,7 @@
.. _CVA6_bht_ports:
.. list-table:: bht module IO ports
.. list-table:: **bht module** IO ports
:header-rows: 1
* - Signal
@ -58,3 +58,4 @@ Due to cv32a65x configuration, some ports are tied to a static value. These port
| As DebugEn = 0,
| ``debug_mode_i`` input is tied to 0

103
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@ -0,0 +1,103 @@
..
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
.. _CVA6_branch_unit_ports:
.. list-table:: **branch_unit module** IO ports
:header-rows: 1
* - Signal
- IO
- Description
- connexion
- Type
* - ``clk_i``
- in
- Subsystem Clock
- SUBSYSTEM
- logic
* - ``rst_ni``
- in
- Asynchronous reset active low
- SUBSYSTEM
- logic
* - ``fu_data_i``
- in
- FU data needed to execute instruction
- ISSUE_STAGE
- ariane_pkg::fu_data_t
* - ``pc_i``
- in
- Instruction PC
- ISSUE_STAGE
- logic[riscv::VLEN-1:0]
* - ``is_compressed_instr_i``
- in
- Instruction is compressed
- ISSUE_STAGE
- logic
* - ``fu_valid_i``
- in
- any functional unit is valid, check that there is no accidental mis-predict
- TO_BE_COMPLETED
- logic
* - ``branch_valid_i``
- in
- Branch unit instruction is valid
- ISSUE_STAGE
- logic
* - ``branch_comp_res_i``
- in
- ALU branch compare result
- ALU
- logic
* - ``branch_result_o``
- out
- Brach unit result
- ISSUE_STAGE
- logic[riscv::VLEN-1:0]
* - ``branch_predict_i``
- in
- Information of branch prediction
- ISSUE_STAGE
- ariane_pkg::branchpredict_sbe_t
* - ``resolved_branch_o``
- out
- Signaling that we resolved the branch
- ISSUE_STAGE
- ariane_pkg::bp_resolve_t
* - ``resolve_branch_o``
- out
- Branch is resolved, new entries can be accepted by scoreboard
- ID_STAGE
- logic
* - ``branch_exception_o``
- out
- Branch exception out
- TO_BE_COMPLETED
- ariane_pkg::exception_t
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
| As DebugEn = 0,
| ``debug_mode_i`` input is tied to 0

3
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@ -9,7 +9,7 @@
.. _CVA6_btb_ports:
.. list-table:: btb module IO ports
.. list-table:: **btb module** IO ports
:header-rows: 1
* - Signal
@ -58,3 +58,4 @@ Due to cv32a65x configuration, some ports are tied to a static value. These port
| As DebugEn = 0,
| ``debug_mode_i`` input is tied to 0

64
docs/04_cv32a65x_design/source/port_commit_stage.rst
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@ -9,7 +9,7 @@
.. _CVA6_commit_stage_ports:
.. list-table:: commit_stage module IO ports
.. list-table:: **commit_stage module** IO ports
:header-rows: 1
* - Signal
@ -48,18 +48,6 @@
- EX_STAGE
- exception_t
* - ``dirty_fp_state_o``
- out
- Mark the F state as dirty
- CSR_REGFILE
- logic
* - ``single_step_i``
- in
- TO_BE_COMPLETED
- CSR_REGFILE
- logic
* - ``commit_instr_i``
- in
- The instruction we want to commit
@ -75,25 +63,25 @@
* - ``waddr_o``
- out
- Register file write address
- ID_STAGE
- ISSUE_STAGE
- logic[CVA6Cfg.NrCommitPorts-1:0][4:0]
* - ``wdata_o``
- out
- Register file write data
- ID_STAGE
- ISSUE_STAGE
- logic[CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0]
* - ``we_gpr_o``
- out
- Register file write enable
- ID_STAGE
- ISSUE_STAGE
- logic[CVA6Cfg.NrCommitPorts-1:0]
* - ``we_fpr_o``
- out
- Floating point register enable
- ID_STAGE
- ISSUE_STAGE
- logic[CVA6Cfg.NrCommitPorts-1:0]
* - ``pc_o``
@ -126,12 +114,6 @@
- CSR_REGFILE
- exception_t
* - ``csr_write_fflags_o``
- out
- Write the fflags CSR
- CSR_REGFILE
- logic
* - ``commit_lsu_o``
- out
- Commit the pending store
@ -150,12 +132,6 @@
- ID_STAGE
- logic[TRANS_ID_BITS-1:0]
* - ``amo_valid_commit_o``
- out
- Valid AMO in commit stage
- EX_STAGE
- logic
* - ``no_st_pending_i``
- in
- no store is pending
@ -168,31 +144,25 @@
- EX_STAGE
- logic
* - ``fence_i_o``
- out
- Flush I$ and pipeline
- CONTROLLER
- logic
* - ``fence_o``
- out
- Flush D$ and pipeline
- CONTROLLER
- logic
* - ``flush_commit_o``
- out
- Request a pipeline flush
- CONTROLLER
- logic
* - ``sfence_vma_o``
- out
- Flush TLBs and pipeline
- CONTROLLER
- logic
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
| As RVF = 0,
| ``dirty_fp_state_o`` output is tied to 0
| ``csr_write_fflags_o`` output is tied to 0
| As DebugEn = 0,
| ``single_step_i`` input is tied to 0
| As RVA = 0,
| ``amo_resp_i`` input is tied to 0
| ``amo_valid_commit_o`` output is tied to 0
| As FenceEn = 0,
| ``fence_i_o`` output is tied to 0
| ``fence_o`` output is tied to 0
| As RVS = 0,
| ``sfence_vma_o`` output is tied to 0

4
docs/04_cv32a65x_design/source/port_compressed_decoder.rst
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@ -9,7 +9,7 @@
.. _CVA6_compressed_decoder_ports:
.. list-table:: compressed_decoder module IO ports
.. list-table:: **compressed_decoder module** IO ports
:header-rows: 1
* - Signal
@ -42,6 +42,4 @@
- decoder
- logic
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
none

34
docs/04_cv32a65x_design/source/port_controller.rst
View file

@ -9,7 +9,7 @@
.. _CVA6_controller_ports:
.. list-table:: controller module IO ports
.. list-table:: **controller module** IO ports
:header-rows: 1
* - Signal
@ -84,12 +84,6 @@
- CACHE
- logic
* - ``flush_tlb_o``
- out
- Flush TLBs
- EX_STAGE
- logic
* - ``halt_csr_i``
- in
- Halt request from CSR (WFI instruction)
@ -126,24 +120,6 @@
- CSR_REGFILE
- logic
* - ``fence_i_i``
- in
- fence.i in
- ACC_DISPATCH
- logic
* - ``fence_i``
- in
- fence in
- ACC_DISPATCH
- logic
* - ``sfence_vma_i``
- in
- We got an instruction to flush the TLBs and pipeline
- COMMIT_STAGE
- logic
* - ``flush_commit_i``
- in
- Flush request from commit stage
@ -152,8 +128,16 @@
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
| As MMUPresent = 0,
| ``flush_tlb_o`` output is tied to 0
| As EnableAccelerator = 0,
| ``halt_acc_i`` input is tied to 0
| ``flush_acc_i`` input is tied to 0
| As DebugEn = 0,
| ``set_debug_pc_i`` input is tied to 0
| As FenceEn = 0,
| ``fence_i_i`` input is tied to 0
| ``fence_i`` input is tied to 0
| As RVS = 0,
| ``sfence_vma_i`` input is tied to 0

75
docs/04_cv32a65x_design/source/port_csr_buffer.rst Normal file
View file

@ -0,0 +1,75 @@
..
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
.. _CVA6_csr_buffer_ports:
.. list-table:: **csr_buffer module** IO ports
:header-rows: 1
* - Signal
- IO
- Description
- connexion
- Type
* - ``clk_i``
- in
- Subsystem Clock
- SUBSYSTEM
- logic
* - ``rst_ni``
- in
- Asynchronous reset active low
- SUBSYSTEM
- logic
* - ``flush_i``
- in
- Flush CSR
- CONTROLLER
- logic
* - ``fu_data_i``
- in
- FU data needed to execute instruction
- ISSUE_STAGE
- fu_data_t
* - ``csr_ready_o``
- out
- CSR FU is ready
- ISSUE_STAGE
- logic
* - ``csr_valid_i``
- in
- CSR instruction is valid
- ISSUE_STAGE
- logic
* - ``csr_result_o``
- out
- CSR buffer result
- ISSUE_STAGE
- riscv::xlen_t
* - ``csr_commit_i``
- in
- commit the pending CSR OP
- TO_BE_COMPLETED
- logic
* - ``csr_addr_o``
- out
- CSR address to write
- COMMIT_STAGE
- logic[11:0]

154
docs/04_cv32a65x_design/source/port_csr_regfile.rst
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@ -9,7 +9,7 @@
.. _CVA6_csr_regfile_ports:
.. list-table:: csr_regfile module IO ports
.. list-table:: **csr_regfile module** IO ports
:header-rows: 1
* - Signal
@ -102,18 +102,6 @@
- COMMIT_STAGE
- logic[riscv::XLEN-1:0]
* - ``dirty_fp_state_i``
- in
- Mark the FP sate as dirty
- COMMIT_STAGE
- logic
* - ``csr_write_fflags_i``
- in
- Write fflags register e.g.: we are retiring a floating point instruction
- COMMIT_STAGE
- logic
* - ``pc_i``
- in
- PC of instruction accessing the CSR
@ -144,90 +132,12 @@
- FRONTEND
- logic[riscv::VLEN-1:0]
* - ``priv_lvl_o``
- out
- Current privilege level the CPU is in
- EX_STAGE
- riscv::priv_lvl_t
* - ``fs_o``
- out
- Floating point extension status
- ID_STAGE
- riscv::xs_t
* - ``fflags_o``
- out
- Floating-Point Accured Exceptions
- COMMIT_STAGE
- logic[4:0]
* - ``frm_o``
- out
- Floating-Point Dynamic Rounding Mode
- EX_STAGE
- logic[2:0]
* - ``fprec_o``
- out
- Floating-Point Precision Control
- EX_STAGE
- logic[6:0]
* - ``vs_o``
- out
- Vector extension status
- ID_STAGE
- riscv::xs_t
* - ``irq_ctrl_o``
- out
- interrupt management to id stage
- ID_STAGE
- irq_ctrl_t
* - ``en_translation_o``
- out
- enable VA translation
- EX_STAGE
- logic
* - ``en_ld_st_translation_o``
- out
- enable VA translation for load and stores
- EX_STAGE
- logic
* - ``ld_st_priv_lvl_o``
- out
- Privilege level at which load and stores should happen
- EX_STAGE
- riscv::priv_lvl_t
* - ``sum_o``
- out
- TO_BE_COMPLETED
- EX_STAGE
- logic
* - ``mxr_o``
- out
- TO_BE_COMPLETED
- EX_STAGE
- logic
* - ``satp_ppn_o``
- out
- TO_BE_COMPLETED
- EX_STAGE
- logic[riscv::PPNW-1:0]
* - ``asid_o``
- out
- TO_BE_COMPLETED
- EX_STAGE
- logic[AsidWidth-1:0]
* - ``irq_i``
- in
- external interrupt in
@ -240,42 +150,6 @@
- SUBSYSTEM
- logic
* - ``set_debug_pc_o``
- out
- TO_BE_COMPLETED
- FRONTEND
- logic
* - ``tvm_o``
- out
- trap virtual memory
- ID_STAGE
- logic
* - ``tw_o``
- out
- timeout wait
- ID_STAGE
- logic
* - ``tsr_o``
- out
- trap sret
- ID_STAGE
- logic
* - ``debug_mode_o``
- out
- we are in debug mode -> that will change some decoding
- EX_STAGE
- logic
* - ``single_step_o``
- out
- we are in single-step mode
- COMMIT_STAGE
- logic
* - ``icache_en_o``
- out
- L1 ICache Enable
@ -290,6 +164,13 @@
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
| As RVF = 0,
| ``dirty_fp_state_i`` input is tied to 0
| ``csr_write_fflags_i`` input is tied to 0
| ``fs_o`` output is tied to 0
| ``fflags_o`` output is tied to 0
| ``frm_o`` output is tied to 0
| ``fprec_o`` output is tied to 0
| As EnableAccelerator = 0,
| ``dirty_v_state_i`` input is tied to 0
| ``acc_fflags_ex_i`` input is tied to 0
@ -297,11 +178,30 @@ Due to cv32a65x configuration, some ports are tied to a static value. These port
| ``acc_cons_en_o`` output is tied to 0
| ``pmpcfg_o`` output is tied to 0
| ``pmpaddr_o`` output is tied to 0
| As PRIV = MachineOnly,
| ``priv_lvl_o`` output is tied to MachineMode
| ``ld_st_priv_lvl_o`` output is tied to MAchineMode
| ``tvm_o`` output is tied to 0
| ``tw_o`` output is tied to 0
| ``tsr_o`` output is tied to 0
| As RVV = 0,
| ``vs_o`` output is tied to 0
| As RVS = 0,
| ``en_translation_o`` output is tied to 0
| ``en_ld_st_translation_o`` output is tied to 0
| ``sum_o`` output is tied to 0
| ``mxr_o`` output is tied to 0
| ``satp_ppn_o`` output is tied to 0
| ``asid_o`` output is tied to 0
| As DebugEn = 0,
| ``debug_req_i`` input is tied to 0
| ``set_debug_pc_o`` output is tied to 0
| ``debug_mode_o`` output is tied to 0
| ``single_step_o`` output is tied to 0
| As PerfCounterEn = 0,
| ``perf_addr_o`` output is tied to 0
| ``perf_data_o`` output is tied to 0
| ``perf_data_i`` input is tied to 0
| ``perf_we_o`` output is tied to 0
| ``mcountinhibit_o`` output is tied to 0

11
docs/04_cv32a65x_design/source/port_cva6.rst
View file

@ -9,7 +9,7 @@
.. _CVA6_cva6_ports:
.. list-table:: cva6 module IO ports
.. list-table:: **cva6 module** IO ports
:header-rows: 1
* - Signal
@ -60,12 +60,6 @@
- SUBSYSTEM
- logic
* - ``rvfi_probes_o``
- out
- Probes to build RVFI, can be left open when not used
- SUBSYSTEM
- rvfi_probes_t
* - ``cvxif_req_o``
- out
- CVXIF request
@ -94,3 +88,6 @@ Due to cv32a65x configuration, some ports are tied to a static value. These port
| As DebugEn = 0,
| ``debug_req_i`` input is tied to 0
| As IsRVFI = 0,
| ``rvfi_probes_o`` output is tied to 0

103
docs/04_cv32a65x_design/source/port_cvxif_fu.rst Normal file
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@ -0,0 +1,103 @@
..
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
.. _CVA6_cvxif_fu_ports:
.. list-table:: **cvxif_fu module** IO ports
:header-rows: 1
* - Signal
- IO
- Description
- connexion
- Type
* - ``clk_i``
- in
- Subsystem Clock
- SUBSYSTEM
- logic
* - ``rst_ni``
- in
- Asynchronous reset active low
- SUBSYSTEM
- logic
* - ``fu_data_i``
- in
- FU data needed to execute instruction
- ISSUE_STAGE
- fu_data_t
* - ``x_valid_i``
- in
- CVXIF instruction is valid
- ISSUE_STAGE
- logic
* - ``x_ready_o``
- out
- CVXIF is ready
- ISSUE_STAGE
- logic
* - ``x_off_instr_i``
- in
- Offloaded instruction
- ISSUE_STAGE
- logic[31:0]
* - ``x_trans_id_o``
- out
- CVXIF transaction ID
- ISSUE_STAGE
- logic[TRANS_ID_BITS-1:0]
* - ``x_exception_o``
- out
- CVXIF exception
- ISSUE_STAGE
- exception_t
* - ``x_result_o``
- out
- CVXIF FU result
- ISSUE_STAGE
- riscv::xlen_t
* - ``x_valid_o``
- out
- CVXIF result valid
- ISSUE_STAGE
- logic
* - ``x_we_o``
- out
- CVXIF write enable
- ISSUE_STAGE
- logic
* - ``cvxif_req_o``
- out
- CVXIF request
- SUBSYSTEM
- cvxif_pkg::cvxif_req_t
* - ``cvxif_resp_i``
- in
- CVXIF response
- SUBSYSTEM
- cvxif_pkg::cvxif_resp_t
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
| As PRIV = MachineOnly,
| ``priv_lvl_i`` input is tied to MachineMode

24
docs/04_cv32a65x_design/source/port_decoder.rst
View file

@ -9,7 +9,7 @@
.. _CVA6_decoder_ports:
.. list-table:: decoder module IO ports
.. list-table:: **decoder module** IO ports
:header-rows: 1
* - Signal
@ -72,24 +72,6 @@
- CSR_REGFILE
- irq_ctrl_t
* - ``tvm_i``
- in
- Trap virtual memory
- CSR_REGFILE
- logic
* - ``tw_i``
- in
- Timeout wait
- CSR_REGFILE
- logic
* - ``tsr_i``
- in
- Trap sret
- CSR_REGFILE
- logic
* - ``instruction_o``
- out
- Instruction to be added to scoreboard entry
@ -115,8 +97,12 @@ Due to cv32a65x configuration, some ports are tied to a static value. These port
| ``debug_mode_i`` input is tied to 0
| As PRIV = MachineOnly,
| ``priv_lvl_i`` input is tied to MachineMode
| ``tvm_i`` input is tied to 0
| ``tw_i`` input is tied to 0
| ``tsr_i`` input is tied to 0
| As RVF = 0,
| ``fs_i`` input is tied to 0
| ``frm_i`` input is tied to 0
| As RVV = 0,
| ``vs_i`` input is tied to 0

160
docs/04_cv32a65x_design/source/port_ex_stage.rst
View file

@ -9,7 +9,7 @@
.. _CVA6_ex_stage_ports:
.. list-table:: ex_stage module IO ports
.. list-table:: **ex_stage module** IO ports
:header-rows: 1
* - Signal
@ -39,79 +39,79 @@
* - ``rs1_forwarding_i``
- in
- rs1 forwarding
- ID_STAGE
- ISSUE_STAGE
- logic[riscv::VLEN-1:0]
* - ``rs2_forwarding_i``
- in
- rs2 forwarding
- ID_STAGE
- ISSUE_STAGE
- logic[riscv::VLEN-1:0]
* - ``fu_data_i``
- in
- FU data useful to execute instruction
- ID_STAGE
- ISSUE_STAGE
- fu_data_t
* - ``pc_i``
- in
- PC of the current instruction
- ID_STAGE
- ISSUE_STAGE
- logic[riscv::VLEN-1:0]
* - ``is_compressed_instr_i``
- in
- Report whether isntruction is compressed
- ID_STAGE
- ISSUE_STAGE
- logic
* - ``flu_result_o``
- out
- TO_BE_COMPLETED
- ID_STAGE
- Fixed Latency Unit result
- ISSUE_STAGE
- riscv::xlen_t
* - ``flu_trans_id_o``
- out
- ID of the scoreboard entry at which a=to write back
- ID_STAGE
- ISSUE_STAGE
- logic[TRANS_ID_BITS-1:0]
* - ``flu_exception_o``
- out
- TO_BE_COMPLETED
- ID_STAGE
- Fixed Latency Unit exception
- ISSUE_STAGE
- exception_t
* - ``flu_ready_o``
- out
- FLU is ready
- ID_STAGE
- ISSUE_STAGE
- logic
* - ``flu_valid_o``
- out
- FLU result is valid
- ID_STAGE
- ISSUE_STAGE
- logic
* - ``alu_valid_i``
- in
- ALU result is valid
- ID_STAGE
- ALU instruction is valid
- ISSUE_STAGE
- logic
* - ``branch_valid_i``
- in
- Branch unit result is valid
- ID_STAGE
- Branch unit instruction is valid
- ISSUE_STAGE
- logic
* - ``branch_predict_i``
- in
- Information of branch prediction
- ID_STAGE
- ISSUE_STAGE
- branchpredict_sbe_t
* - ``resolved_branch_o``
@ -122,97 +122,97 @@
* - ``resolve_branch_o``
- out
- ID signaling that we resolved the branch
- ID_STAGE
- Signaling that we resolved the branch
- ISSUE_STAGE
- logic
* - ``csr_valid_i``
- in
- CSR result is valid
- ID_STAGE
- CSR instruction is valid
- ISSUE_STAGE
- logic
* - ``csr_addr_o``
- out
- TO_BE_COMPLETED
- CSR_REGISTERS
- CSR address to write
- COMMIT_STAGE
- logic[11:0]
* - ``csr_commit_i``
- in
- TO_BE_COMPLETED
- CSR commit
- COMMIT_STAGE
- logic
* - ``mult_valid_i``
- in
- MULT result is valid
- ID_STAGE
- MULT instruction is valid
- ISSUE_STAGE
- logic
* - ``lsu_ready_o``
- out
- FU is ready
- ID_STAGE
- LSU is ready
- ISSUE_STAGE
- logic
* - ``lsu_valid_i``
- in
- LSU result is valid
- ID_STAGE
- LSU instruction is valid
- ISSUE_STAGE
- logic
* - ``load_valid_o``
- out
- Load result is valid
- ID_STAGE
- ISSUE_STAGE
- logic
* - ``load_result_o``
- out
- Load result valid
- ID_STAGE
- ISSUE_STAGE
- riscv::xlen_t
* - ``load_trans_id_o``
- out
- Load instruction ID
- ID_STAGE
- ISSUE_STAGE
- logic[TRANS_ID_BITS-1:0]
* - ``load_exception_o``
- out
- Exception generated by load instruction
- ID_STAGE
- ISSUE_STAGE
- exception_t
* - ``store_valid_o``
- out
- Store result is valid
- ID_STAGE
- ISSUe_STAGE
- logic
* - ``store_result_o``
- out
- Store result
- ID_STAGE
- ISSUE_STAGE
- riscv::xlen_t
* - ``store_trans_id_o``
- out
- Store instruction ID
- ID_STAGE
- ISSUE_STAGE
- logic[TRANS_ID_BITS-1:0]
* - ``store_exception_o``
- out
- Exception generated by store instruction
- ID_STAGE
- ISSUE_STAGE
- exception_t
* - ``lsu_commit_i``
- in
- TO_BE_COMPLETED
- LSU commit
- COMMIT_STAGE
- logic
@ -224,7 +224,7 @@
* - ``commit_tran_id_i``
- in
- TO_BE_COMPLETED
- Commit transaction ID
- COMMIT_STAGE
- logic[TRANS_ID_BITS-1:0]
@ -248,88 +248,52 @@
* - ``x_off_instr_i``
- in
- TO_BE_COMPLETED
- ID_STAGE
- undecoded instruction
- ISSUE_STAGE
- logic[31:0]
* - ``x_trans_id_o``
- out
- TO_BE_COMPLETED
- ID_STAGE
- CVXIF transaction ID
- ISSUE_STAGE
- logic[TRANS_ID_BITS-1:0]
* - ``x_exception_o``
- out
- TO_BE_COMPLETED
- ID_STAGE
- CVXIF exception
- ISSUE_STAGE
- exception_t
* - ``x_result_o``
- out
- TO_BE_COMPLETED
- ID_STAGE
- CVXIF result
- ISSUE_STAGE
- riscv::xlen_t
* - ``x_valid_o``
- out
- TO_BE_COMPLETED
- ID_STAGE
- CVXIF result valid
- ISSUE_STAGE
- logic
* - ``x_we_o``
- out
- TO_BE_COMPLETED
- ID_STAGE
- CVXIF write enable
- ISSUE_STAGE
- logic
* - ``cvxif_req_o``
- out
- TO_BE_COMPLETED
- CVXIF request
- SUBSYSTEM
- cvxif_pkg::cvxif_req_t
* - ``cvxif_resp_i``
- in
- TO_BE_COMPLETED
- CVXIF response
- SUBSYSTEM
- cvxif_pkg::cvxif_resp_t
* - ``enable_translation_i``
- in
- TO_BE_COMPLETED
- CSR_REGFILE
- logic
* - ``en_ld_st_translation_i``
- in
- TO_BE_COMPLETED
- CSR_REGFILE
- logic
* - ``sum_i``
- in
- Supervisor user memory
- CSR_REGFILE
- logic
* - ``mxr_i``
- in
- Make executable readable
- CSR_REGFILE
- logic
* - ``satp_ppn_i``
- in
- TO_BE_COMPLETED
- CSR_REGFILE
- logic[riscv::PPNW-1:0]
* - ``asid_i``
- in
- TO_BE_COMPLETED
- CSR_REGFILE
- logic[ASID_WIDTH-1:0]
* - ``icache_areq_i``
- in
- icache translation response
@ -344,19 +308,19 @@
* - ``dcache_req_ports_i``
- in
- TO_BE_COMPLETED
- Data cache request ouput
- CACHE
- dcache_req_o_t[2:0]
* - ``dcache_req_ports_o``
- out
- TO_BE_COMPLETED
- Data cache request input
- CACHE
- dcache_req_i_t[2:0]
* - ``dcache_wbuffer_empty_i``
- in
- TO_BE_COMPLETED
- Write buffer is empty
- CACHE
- logic
@ -400,6 +364,13 @@ Due to cv32a65x configuration, some ports are tied to a static value. These port
| ``fpu_result_o`` output is tied to 0
| ``fpu_valid_o`` output is tied to 0
| ``fpu_exception_o`` output is tied to 0
| As RVS = 0,
| ``enable_translation_i`` input is tied to 0
| ``en_ld_st_translation_i`` input is tied to 0
| ``sum_i`` input is tied to 0
| ``mxr_i`` input is tied to 0
| ``satp_ppn_i`` input is tied to 0
| ``asid_i`` input is tied to 0
| As MMUPresent = 0,
| ``flush_tlb_i`` input is tied to 0
| As PRIV = MachineOnly,
@ -411,3 +382,4 @@ Due to cv32a65x configuration, some ports are tied to a static value. These port
| As IsRVFI = 0,
| ``rvfi_lsu_ctrl_o`` output is tied to 0
| ``rvfi_mem_paddr_o`` output is tied to 0

5
docs/04_cv32a65x_design/source/port_frontend.rst
View file

@ -9,7 +9,7 @@
.. _CVA6_frontend_ports:
.. list-table:: frontend module IO ports
.. list-table:: **frontend module** IO ports
:header-rows: 1
* - Signal
@ -123,7 +123,8 @@
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
| For any HW configuration,
| ``flush_bp_i`` input is tied to zero
| ``flush_bp_i`` input is tied to 0
| As DebugEn = 0,
| ``debug_mode_i`` input is tied to 0
| ``set_debug_pc_i`` input is tied to 0

24
docs/04_cv32a65x_design/source/port_id_stage.rst
View file

@ -9,7 +9,7 @@
.. _CVA6_id_stage_ports:
.. list-table:: id_stage module IO ports
.. list-table:: **id_stage module** IO ports
:header-rows: 1
* - Signal
@ -96,24 +96,6 @@
- CSR_REGFILE
- ariane_pkg::irq_ctrl_t
* - ``tvm_i``
- in
- Trap virtual memory
- CSR_REGFILE
- logic
* - ``tw_i``
- in
- Timeout wait
- CSR_REGFILE
- logic
* - ``tsr_i``
- in
- Trap sret
- CSR_REGFILE
- logic
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
| As DebugEn = 0,
@ -123,8 +105,12 @@ Due to cv32a65x configuration, some ports are tied to a static value. These port
| ``rvfi_is_compressed_o`` output is tied to 0
| As PRIV = MachineOnly,
| ``priv_lvl_i`` input is tied to MachineMode
| ``tvm_i`` input is tied to 0
| ``tw_i`` input is tied to 0
| ``tsr_i`` input is tied to 0
| As RVF = 0,
| ``fs_i`` input is tied to 0
| ``frm_i`` input is tied to 0
| As RVV = 0,
| ``vs_i`` input is tied to 0

4
docs/04_cv32a65x_design/source/port_instr_queue.rst
View file

@ -9,7 +9,7 @@
.. _CVA6_instr_queue_ports:
.. list-table:: instr_queue module IO ports
.. list-table:: **instr_queue module** IO ports
:header-rows: 1
* - Signal
@ -120,6 +120,4 @@
- ID_STAGE
- logic
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
none

4
docs/04_cv32a65x_design/source/port_instr_realign.rst
View file

@ -9,7 +9,7 @@
.. _CVA6_instr_realign_ports:
.. list-table:: instr_realign module IO ports
.. list-table:: **instr_realign module** IO ports
:header-rows: 1
* - Signal
@ -78,6 +78,4 @@
- instr_scan&instr_queue
- logic[INSTR_PER_FETCH-1:0][31:0]
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
none

4
docs/04_cv32a65x_design/source/port_instr_scan.rst
View file

@ -9,7 +9,7 @@
.. _CVA6_instr_scan_ports:
.. list-table:: instr_scan module IO ports
.. list-table:: **instr_scan module** IO ports
:header-rows: 1
* - Signal
@ -102,6 +102,4 @@
- FRONTEND
- logic[riscv::VLEN-1:0]
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
none

248
docs/04_cv32a65x_design/source/port_issue_read_operands.rst
View file

@ -9,7 +9,7 @@
.. _CVA6_issue_read_operands_ports:
.. list-table:: issue_read_operands module IO ports
.. list-table:: **issue_read_operands module** IO ports
:header-rows: 1
* - Signal
@ -18,270 +18,242 @@
- connexion
- Type
* - ``Clock``
* - ``clk_i``
- in
- none
- none
- logicclk_i,//
- Subsystem Clock
- SUBSYSTEM
- logic
* - ``low``
* - ``rst_ni``
- in
- none
- none
- logicrst_ni,//Asynchronousresetactive
- Asynchronous reset active low
- SUBSYSTEM
- logic
* - ``flush_i``
- in
- none
- none
- logic
* - ``stall_i``
- in
- none
- none
- Flush
- CONTROLLER
- logic
* - ``issue_instr_i``
- in
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- scoreboard_entry_t
* - ``orig_instr_i``
- in
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic[31:0]
* - ``issue_instr_valid_i``
- in
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``issue_ack_o``
- out
- none
- none
- Issue stage acknowledge
- TO_BE_COMPLETED
- logic
* - ``rs1_o``
- out
- none
- none
- rs1 operand address
- scoreboard
- logic[REG_ADDR_SIZE-1:0]
* - ``rs1_i``
- in
- none
- none
- rs1 operand
- scoreboard
- riscv::xlen_t
* - ``rs1_valid_i``
- in
- none
- none
- rs1 operand is valid
- scoreboard
- logic
* - ``rs2_o``
- out
- none
- none
- rs2 operand address
- scoreboard
- logic[REG_ADDR_SIZE-1:0]
* - ``rs2_i``
- in
- none
- none
- rs2 operand
- scoreboard
- riscv::xlen_t
* - ``rs2_valid_i``
- in
- none
- none
- rs2 operand is valid
- scoreboard
- logic
* - ``rs3_o``
- out
- none
- none
- rs3 operand address
- scoreboard
- logic[REG_ADDR_SIZE-1:0]
* - ``rs3_i``
- in
- none
- none
- rs3 operand
- scoreboard
- rs3_len_t
* - ``rs3_valid_i``
- in
- none
- none
- rs3 operand is valid
- scoreboard
- logic
* - ``rd_clobber_gpr_i``
- in
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- fu_t[2**REG_ADDR_SIZE-1:0]
* - ``rd_clobber_fpr_i``
- in
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- fu_t[2**REG_ADDR_SIZE-1:0]
* - ``fu_data_o``
- out
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- fu_data_t
* - ``fu_data_o.operanda``
* - ``rs1_forwarding_o``
- out
- none
- none
- riscv::xlen_trs1_forwarding_o,//unregisteredversionof
- Unregistered version of fu_data_o.operanda
- TO_BE_COMPLETED
- riscv::xlen_t
* - ``fu_data_o.operandb``
* - ``rs2_forwarding_o``
- out
- none
- none
- riscv::xlen_trs2_forwarding_o,//unregisteredversionof
- Unregistered version of fu_data_o.operandb
- TO_BE_COMPLETED
- riscv::xlen_t
* - ``pc_o``
- out
- none
- none
- Instruction pc
- TO_BE_COMPLETED
- logic[riscv::VLEN-1:0]
* - ``is_compressed_instr_o``
- out
- none
- none
- Is compressed instruction
- TO_BE_COMPLETED
- logic
* - ``request``
* - ``flu_ready_i``
- in
- none
- none
- logicflu_ready_i,//Fixedlatencyunitreadytoacceptanew
- Fixed Latency Unit ready to accept new request
- TO_BE_COMPLETED
- logic
* - ``valid``
* - ``alu_valid_o``
- out
- none
- none
- logicalu_valid_o,//Outputis
- ALU output is valid
- TO_BE_COMPLETED
- logic
* - ``instruction``
* - ``branch_valid_o``
- out
- none
- none
- logicbranch_valid_o,//thisisavalidbranch
- Branch instruction is valid
- TO_BE_COMPLETED
- logic
* - ``branch_predict_o``
- out
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- branchpredict_sbe_t
* - ``ready``
* - ``lsu_ready_i``
- in
- none
- none
- logiclsu_ready_i,//FUis
- Load Store Unit is ready
- TO_BE_COMPLETED
- logic
* - ``valid``
* - ``lsu_valid_o``
- out
- none
- none
- logiclsu_valid_o,//Outputis
- Load Store Unit result is valid
- TO_BE_COMPLETED
- logic
* - ``valid``
* - ``mult_valid_o``
- out
- none
- none
- logicmult_valid_o,//Outputis
- Mult result is valid
- TO_BE_COMPLETED
- logic
* - ``ready``
- in
- none
- none
- logicfpu_ready_i,//FUis
* - ``valid``
* - ``csr_valid_o``
- out
- none
- none
- logicfpu_valid_o,//Outputis
* - ``instr.``
- out
- none
- none
- logic[1:0]fpu_fmt_o,//FPfmtfieldfrom
* - ``instr.``
- out
- none
- none
- logic[2:0]fpu_rm_o,//FPrmfieldfrom
* - ``valid``
- out
- none
- none
- logiccsr_valid_o,//Outputis
- CSR result is valid
- TO_BE_COMPLETED
- logic
* - ``cvxif_valid_o``
- out
- none
- none
- CVXIF result is valid
- TO_BE_COMPLETED
- logic
* - ``cvxif_ready_i``
- in
- none
- none
- CVXIF is ready
- TO_BE_COMPLETED
- logic
* - ``cvxif_off_instr_o``
- out
- none
- none
- CVXIF offloaded instruction
- TO_BE_COMPLETED
- logic[31:0]
* - ``waddr_i``
- in
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic[CVA6Cfg.NrCommitPorts-1:0][4:0]
* - ``wdata_i``
- in
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic[CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0]
* - ``we_gpr_i``
- in
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic[CVA6Cfg.NrCommitPorts-1:0]
* - ``we_fpr_i``
- in
- none
- none
- logic[CVA6Cfg.NrCommitPorts-1:0]
* - ``entries``
* - ``stall_issue_o``
- out
- none
- none
- logicstall_issue_o//stallsignal,wedonotwanttofetchanymore
- Stall signal, we do not want to fetch any more entries
- TO_BE_COMPLETED
- logic
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
none
| As EnableAccelerator = 0,
| ``stall_i`` input is tied to 0
| As RVF = 0,
| ``fpu_ready_i`` input is tied to 0
| ``fpu_valid_o`` output is tied to 0
| ``fpu_fmt_o`` output is tied to 0
| ``fpu_rm_o`` output is tied to 0
| ``we_fpr_i`` input is tied to 0

35
docs/04_cv32a65x_design/source/port_issue_stage.rst
View file

@ -9,7 +9,7 @@
.. _CVA6_issue_stage_ports:
.. list-table:: issue_stage module IO ports
.. list-table:: **issue_stage module** IO ports
:header-rows: 1
* - Signal
@ -92,7 +92,7 @@
* - ``pc_o``
- out
- TO_BE_COMPLETED
- Program Counter
- EX_STAGE
- logic[riscv::VLEN-1:0]
@ -104,7 +104,7 @@
* - ``flu_ready_i``
- in
- TO_BE_COMPLETED
- Fixed Latency Unit is ready
- EX_STAGE
- logic
@ -116,7 +116,7 @@
* - ``resolve_branch_i``
- in
- TO_BE_COMPLETED
- Signaling that we resolved the branch
- EX_STAGE
- logic
@ -150,12 +150,6 @@
- EX_STAGE
- logic
* - ``fpu_ready_i``
- in
- FPU FU is ready
- EX_STAGE
- logic
* - ``csr_valid_o``
- out
- CSR is valid
@ -182,13 +176,13 @@
* - ``trans_id_i``
- in
- TO_BE_COMPLETED
- Transaction ID
- EX_STAGE
- logic[CVA6Cfg.NrWbPorts-1:0][TRANS_ID_BITS-1:0]
* - ``resolved_branch_i``
- in
- TO_BE_COMPLETED
- The branch engine uses the write back from the ALU
- EX_STAGE
- bp_resolve_t
@ -212,7 +206,7 @@
* - ``x_we_i``
- in
- TO_BE_COMPLETED
- CVXIF write enable
- EX_STAGE
- logic
@ -230,25 +224,19 @@
* - ``we_gpr_i``
- in
- TO_BE_COMPLETED
- EX_STAGE
- logic[CVA6Cfg.NrCommitPorts-1:0]
* - ``we_fpr_i``
- in
- TO_BE_COMPLETED
- GPR write enable
- EX_STAGE
- logic[CVA6Cfg.NrCommitPorts-1:0]
* - ``commit_instr_o``
- out
- TO_BE_COMPLETED
- Instructions to commit
- COMMIT_STAGE
- scoreboard_entry_t[CVA6Cfg.NrCommitPorts-1:0]
* - ``commit_ack_i``
- in
- TO_BE_COMPLETED
- Commit acknowledge
- COMMIT_STAGE
- logic[CVA6Cfg.NrCommitPorts-1:0]
@ -262,9 +250,12 @@ Due to cv32a65x configuration, some ports are tied to a static value. These port
| ``issue_instr_o`` output is tied to 0
| ``issue_instr_hs_o`` output is tied to 0
| As RVF = 0,
| ``fpu_ready_i`` input is tied to 0
| ``fpu_valid_o`` output is tied to 0
| ``fpu_fmt_o`` output is tied to 0
| ``fpu_rm_o`` output is tied to 0
| ``we_fpr_i`` input is tied to 0
| As IsRVFI = 0,
| ``rvfi_issue_pointer_o`` output is tied to 0
| ``rvfi_commit_pointer_o`` output is tied to 0

209
docs/04_cv32a65x_design/source/port_load_store_unit.rst Normal file
View file

@ -0,0 +1,209 @@
..
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
.. _CVA6_load_store_unit_ports:
.. list-table:: **load_store_unit module** IO ports
:header-rows: 1
* - Signal
- IO
- Description
- connexion
- Type
* - ``clk_i``
- in
- Subsystem Clock
- SUBSYSTEM
- logic
* - ``rst_ni``
- in
- Asynchronous reset active low
- SUBSYSTEM
- logic
* - ``flush_i``
- in
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``stall_st_pending_i``
- in
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``no_st_pending_o``
- out
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``fu_data_i``
- in
- FU data needed to execute instruction
- ISSUE_STAGE
- fu_data_t
* - ``lsu_ready_o``
- out
- Load Store Unit is ready
- ISSUE_STAGE
- logic
* - ``lsu_valid_i``
- in
- Load Store Unit instruction is valid
- ISSUE_STAGE
- logic
* - ``load_trans_id_o``
- out
- Load transaction ID
- ISSUE_STAGE
- logic[TRANS_ID_BITS-1:0]
* - ``load_result_o``
- out
- Load result
- ISSUE_STAGE
- riscv::xlen_t
* - ``load_valid_o``
- out
- Load result is valid
- ISSUE_STAGE
- logic
* - ``load_exception_o``
- out
- Load exception
- ISSUE_STAGE
- exception_t
* - ``store_trans_id_o``
- out
- Store transaction ID
- ISSUE_STAGE
- logic[TRANS_ID_BITS-1:0]
* - ``store_result_o``
- out
- Store result
- ISSUE_STAGE
- riscv::xlen_t
* - ``store_valid_o``
- out
- Store result is valid
- ISSUE_STAGE
- logic
* - ``store_exception_o``
- out
- Store exception
- ISSUE_STAGE
- exception_t
* - ``commit_i``
- in
- Commit the first pending store
- TO_BE_COMPLETED
- logic
* - ``commit_ready_o``
- out
- Commit queue is ready to accept another commit request
- TO_BE_COMPLETED
- logic
* - ``commit_tran_id_i``
- in
- Commit transaction ID
- TO_BE_COMPLETED
- logic[TRANS_ID_BITS-1:0]
* - ``icache_areq_i``
- in
- Instruction cache input request
- CACHES
- icache_arsp_t
* - ``icache_areq_o``
- out
- Instruction cache output request
- CACHES
- icache_areq_t
* - ``dcache_req_ports_i``
- in
- Data cache request output
- CACHES
- dcache_req_o_t[2:0]
* - ``dcache_req_ports_o``
- out
- Data cache request input
- CACHES
- dcache_req_i_t[2:0]
* - ``dcache_wbuffer_empty_i``
- in
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``dcache_wbuffer_not_ni_i``
- in
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``pmpcfg_i``
- in
- PMP configuration
- CSR_REGFILE
- riscv::pmpcfg_t[15:0]
* - ``pmpaddr_i``
- in
- PMP address
- CSR_REGFILE
- logic[15:0][riscv::PLEN-3:0]
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
| As RVA = 0,
| ``amo_valid_commit_i`` input is tied to 0
| ``amo_req_o`` output is tied to 0
| ``amo_resp_i`` input is tied to 0
| As RVS = 0,
| ``enable_translation_i`` input is tied to 0
| ``en_ld_st_translation_i`` input is tied to 0
| ``sum_i`` input is tied to 0
| ``mxr_i`` input is tied to 0
| ``satp_ppn_i`` input is tied to 0
| ``asid_i`` input is tied to 0
| ``asid_to_be_flushed_i`` input is tied to 0
| ``vaddr_to_be_flushed_i`` input is tied to 0
| As PRIV = MachineOnly,
| ``priv_lvl_i`` input is tied to MachineMode
| ``ld_st_priv_lvl_i`` input is tied to MAchineMode
| As MMUPresent = 0,
| ``flush_tlb_i`` input is tied to 0
| As PerfCounterEn = 0,
| ``itlb_miss_o`` output is tied to 0
| ``dtlb_miss_o`` output is tied to 0
| As IsRVFI = 0,
| ``rvfi_lsu_ctrl_o`` output is tied to 0
| ``rvfi_mem_paddr_o`` output is tied to 0

153
docs/04_cv32a65x_design/source/port_load_unit.rst Normal file
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@ -0,0 +1,153 @@
..
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
.. _CVA6_load_unit_ports:
.. list-table:: **load_unit module** IO ports
:header-rows: 1
* - Signal
- IO
- Description
- connexion
- Type
* - ``clk_i``
- in
- Subsystem Clock
- SUBSYSTEM
- logic
* - ``rst_ni``
- in
- Asynchronous reset active low
- SUBSYSTEM
- logic
* - ``flush_i``
- in
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``valid_i``
- in
- Load unit input port
- TO_BE_COMPLETED
- logic
* - ``lsu_ctrl_i``
- in
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- lsu_ctrl_t
* - ``pop_ld_o``
- out
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``valid_o``
- out
- Load unit result is valid
- TO_BE_COMPLETED
- logic
* - ``trans_id_o``
- out
- Load transaction ID
- TO_BE_COMPLETED
- logic[TRANS_ID_BITS-1:0]
* - ``result_o``
- out
- Load result
- TO_BE_COMPLETED
- riscv::xlen_t
* - ``ex_o``
- out
- Load exception
- TO_BE_COMPLETED
- exception_t
* - ``translation_req_o``
- out
- Request address translation
- TO_BE_COMPLETED
- logic
* - ``vaddr_o``
- out
- Virtual address
- TO_BE_COMPLETED
- logic[riscv::VLEN-1:0]
* - ``paddr_i``
- in
- Physical address
- TO_BE_COMPLETED
- logic[riscv::PLEN-1:0]
* - ``ex_i``
- in
- Excepted which appears before load
- TO_BE_COMPLETED
- exception_t
* - ``page_offset_o``
- out
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic[11:0]
* - ``page_offset_matches_i``
- in
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``store_buffer_empty_i``
- in
- Store buffer is empty
- TO_BE_COMPLETED
- logic
* - ``commit_tran_id_i``
- in
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic[TRANS_ID_BITS-1:0]
* - ``req_port_i``
- in
- Data cache request out
- CACHES
- dcache_req_o_t
* - ``req_port_o``
- out
- Data cache request in
- CACHES
- dcache_req_i_t
* - ``dcache_wbuffer_not_ni_i``
- in
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
| For any HW configuration,
| ``dtlb_hit_i`` input is tied to 1
| As MMUPresent = 0,
| ``dtlb_ppn_i`` input is tied to 0

75
docs/04_cv32a65x_design/source/port_lsu_bypass.rst Normal file
View file

@ -0,0 +1,75 @@
..
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
.. _CVA6_lsu_bypass_ports:
.. list-table:: **lsu_bypass module** IO ports
:header-rows: 1
* - Signal
- IO
- Description
- connexion
- Type
* - ``clk_i``
- in
- Subsystem Clock
- SUBSYSTEM
- logic
* - ``rst_ni``
- in
- Asynchronous reset active low
- SUBSYSTEM
- logic
* - ``flush_i``
- in
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``lsu_req_i``
- in
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- lsu_ctrl_t
* - ``lsu_req_valid_i``
- in
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``pop_ld_i``
- in
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``pop_st_i``
- in
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``lsu_ctrl_o``
- out
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- lsu_ctrl_t
* - ``ready_o``
- out
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic

75
docs/04_cv32a65x_design/source/port_mult.rst Normal file
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@ -0,0 +1,75 @@
..
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
.. _CVA6_mult_ports:
.. list-table:: **mult module** IO ports
:header-rows: 1
* - Signal
- IO
- Description
- connexion
- Type
* - ``clk_i``
- in
- Subsystem Clock
- SUBSYSTEM
- logic
* - ``rst_ni``
- in
- Asynchronous reset active low
- SUBSYSTEM
- logic
* - ``flush_i``
- in
- Flush
- CONTROLLER
- logic
* - ``fu_data_i``
- in
- FU data needed to execute instruction
- ISSUE_STAGE
- fu_data_t
* - ``mult_valid_i``
- in
- Mult instruction is valid
- ISSUE_STAGE
- logic
* - ``result_o``
- out
- Mult result
- ISSUE_STAGE
- riscv::xlen_t
* - ``mult_valid_o``
- out
- Mult result is valid
- ISSUE_STAGE
- logic
* - ``mult_ready_o``
- out
- Mutl is ready
- ISSUE_STAGE
- logic
* - ``mult_trans_id_o``
- out
- Mult transaction ID
- ISSUE_STAGE
- logic[TRANS_ID_BITS-1:0]

87
docs/04_cv32a65x_design/source/port_multiplier.rst Normal file
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@ -0,0 +1,87 @@
..
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
.. _CVA6_multiplier_ports:
.. list-table:: **multiplier module** IO ports
:header-rows: 1
* - Signal
- IO
- Description
- connexion
- Type
* - ``clk_i``
- in
- Subsystem Clock
- SUBSYSTEM
- logic
* - ``rst_ni``
- in
- Asynchronous reset active low
- SUBSYSTEM
- logic
* - ``trans_id_i``
- in
- Multiplier transaction ID
- Mult
- logic[TRANS_ID_BITS-1:0]
* - ``mult_valid_i``
- in
- Multiplier instruction is valid
- Mult
- logic
* - ``operation_i``
- in
- Multiplier operation
- Mult
- fu_op
* - ``operand_a_i``
- in
- A operand
- Mult
- riscv::xlen_t
* - ``operand_b_i``
- in
- B operand
- Mult
- riscv::xlen_t
* - ``result_o``
- out
- Multiplier result
- Mult
- riscv::xlen_t
* - ``mult_valid_o``
- out
- Mutliplier result is valid
- Mult
- logic
* - ``mult_ready_o``
- out
- Multiplier FU is ready
- Mult
- logic
* - ``mult_trans_id_o``
- out
- Multiplier transaction ID
- Mult
- logic[TRANS_ID_BITS-1:0]

4
docs/04_cv32a65x_design/source/port_ras.rst
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@ -9,7 +9,7 @@
.. _CVA6_ras_ports:
.. list-table:: ras module IO ports
.. list-table:: **ras module** IO ports
:header-rows: 1
* - Signal
@ -60,6 +60,4 @@
- FRONTEND
- ariane_pkg::ras_t
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
none

195
docs/04_cv32a65x_design/source/port_scoreboard.rst
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@ -9,7 +9,7 @@
.. _CVA6_scoreboard_ports:
.. list-table:: scoreboard module IO ports
.. list-table:: **scoreboard module** IO ports
:header-rows: 1
* - Signal
@ -18,216 +18,203 @@
- connexion
- Type
* - ``Clock``
* - ``clk_i``
- in
- none
- none
- logicclk_i,//
- Subsystem Clock
- SUBSYSTEM
- logic
* - ``low``
* - ``rst_ni``
- in
- none
- none
- logicrst_ni,//Asynchronousresetactive
- Asynchronous reset active low
- SUBSYSTEM
- logic
* - ``sb_full_o``
- out
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``instructions``
* - ``flush_unissued_instr_i``
- in
- none
- none
- logicflush_unissued_instr_i,//flushonlyun-issued
- Flush only un-issued instructions
- TO_BE_COMPLETED
- logic
* - ``scoreboard``
* - ``flush_i``
- in
- none
- none
- logicflush_i,//flushwhole
- Flush whole scoreboard
- TO_BE_COMPLETED
- logic
* - ``branch``
* - ``unresolved_branch_i``
- in
- none
- none
- logicunresolved_branch_i,//wehaveanunresolved
- We have an unresolved branch
- TO_BE_COMPLETED
- logic
* - ``rd_clobber_gpr_o``
- out
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- ariane_pkg::fu_t[2**ariane_pkg::REG_ADDR_SIZE-1:0]
* - ``rd_clobber_fpr_o``
- out
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- ariane_pkg::fu_t[2**ariane_pkg::REG_ADDR_SIZE-1:0]
* - ``rs1_i``
- in
- none
- none
- rs1 operand address
- issue_read_operands
- logic[ariane_pkg::REG_ADDR_SIZE-1:0]
* - ``rs1_o``
- out
- none
- none
- rs1 operand
- issue_read_operands
- riscv::xlen_t
* - ``rs1_valid_o``
- out
- none
- none
- rs1 operand is valid
- issue_read_operands
- logic
* - ``rs2_i``
- in
- none
- none
- rs2 operand address
- issue_read_operands
- logic[ariane_pkg::REG_ADDR_SIZE-1:0]
* - ``rs2_o``
- out
- none
- none
- rs2 operand
- issue_read_operands
- riscv::xlen_t
* - ``rs2_valid_o``
- out
- none
- none
- rs2 operand is valid
- issue_read_operands
- logic
* - ``rs3_i``
- in
- none
- none
- rs3 operand address
- issue_read_operands
- logic[ariane_pkg::REG_ADDR_SIZE-1:0]
* - ``rs3_o``
- out
- none
- none
- rs3 operand
- issue_read_operands
- rs3_len_t
* - ``rs3_valid_o``
- out
- none
- none
- rs3 operand is valid
- issue_read_operands
- logic
* - ``commit_instr_o``
- out
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- ariane_pkg::scoreboard_entry_t[CVA6Cfg.NrCommitPorts-1:0]
* - ``commit_ack_i``
- in
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic[CVA6Cfg.NrCommitPorts-1:0]
* - ``decoded_instr_i``
- in
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- ariane_pkg::scoreboard_entry_t
* - ``orig_instr_i``
- in
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic[31:0]
* - ``decoded_instr_valid_i``
- in
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``decoded_instr_ack_o``
- out
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``issue_instr_o``
- out
- none
- none
- ariane_pkg::scoreboard_entry_t
* - ``orig_instr_o``
- out
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic[31:0]
* - ``issue_instr_valid_o``
- out
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``issue_ack_i``
- in
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``resolved_branch_i``
- in
- none
- none
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- ariane_pkg::bp_resolve_t
* - ``back``
* - ``trans_id_i``
- in
- none
- none
- logic[CVA6Cfg.NrWbPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0]trans_id_i,//transactionIDatwhichtowritetheresult
- Transaction ID at which to write the result back
- TO_BE_COMPLETED
- logic[CVA6Cfg.NrWbPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0]
* - ``in``
* - ``wbdata_i``
- in
- none
- none
- logic[CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0]wbdata_i,//writedata
- Results to write back
- TO_BE_COMPLETED
- logic[CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0]
* - ``exception)``
* - ``ex_i``
- in
- none
- none
- ariane_pkg::exception_t[CVA6Cfg.NrWbPorts-1:0]ex_i,//exceptionfromafunctionalunit(e.g.:ld/st
- Exception from a functional unit (e.g.: ld/st exception)
- TO_BE_COMPLETED
- ariane_pkg::exception_t[CVA6Cfg.NrWbPorts-1:0]
* - ``valid``
* - ``wt_valid_i``
- in
- none
- none
- logic[CVA6Cfg.NrWbPorts-1:0]wt_valid_i,//datainis
- Indicates valid results
- TO_BE_COMPLETED
- logic[CVA6Cfg.NrWbPorts-1:0]
* - ``writeback``
* - ``x_we_i``
- in
- none
- none
- logicx_we_i,//cvxifwefor
* - ``rvfi_issue_pointer_o``
- out
- none
- none
- logic[ariane_pkg::TRANS_ID_BITS-1:0]
* - ``rvfi_commit_pointer_o``
- out
- none
- none
- logic[CVA6Cfg.NrCommitPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0]
- Cvxif we for writeback
- TO_BE_COMPLETED
- logic
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
none
| As EnableAccelerator = 0,
| ``issue_instr_o`` output is tied to 0
| As IsRVFI = 0,
| ``rvfi_issue_pointer_o`` output is tied to 0
| ``rvfi_commit_pointer_o`` output is tied to 0

99
docs/04_cv32a65x_design/source/port_serdiv.rst Normal file
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@ -0,0 +1,99 @@
..
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
.. _CVA6_serdiv_ports:
.. list-table:: **serdiv module** IO ports
:header-rows: 1
* - Signal
- IO
- Description
- connexion
- Type
* - ``clk_i``
- in
- Subsystem Clock
- SUBSYSTEM
- logic
* - ``rst_ni``
- in
- Asynchronous reset active low
- SUBSYSTEM
- logic
* - ``id_i``
- in
- Serdiv translation ID
- Mult
- logic[TRANS_ID_BITS-1:0]
* - ``op_a_i``
- in
- A operand
- Mult
- logic[WIDTH-1:0]
* - ``op_b_i``
- in
- B operand
- Mult
- logic[WIDTH-1:0]
* - ``rem``
- in
- Serdiv operation
- Mult
- logic[1:0]opcode_i,//0:udiv,2:urem,1:div,3:
* - ``in_vld_i``
- in
- Serdiv instruction is valid
- Mult
- logic
* - ``in_rdy_o``
- out
- Serdiv FU is ready
- Mult
- logic
* - ``flush_i``
- in
- Flush
- CONTROLLER
- logic
* - ``out_vld_o``
- out
- Serdiv result is valid
- Mult
- logic
* - ``out_rdy_i``
- in
- Serdiv is ready
- Mult
- logic
* - ``id_o``
- out
- Serdiv transaction ID
- Mult
- logic[TRANS_ID_BITS-1:0]
* - ``res_o``
- out
- Serdiv result
- Mult
- logic[WIDTH-1:0]

169
docs/04_cv32a65x_design/source/port_store_unit.rst Normal file
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@ -0,0 +1,169 @@
..
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
.. _CVA6_store_unit_ports:
.. list-table:: **store_unit module** IO ports
:header-rows: 1
* - Signal
- IO
- Description
- connexion
- Type
* - ``clk_i``
- in
- Subsystem Clock
- SUBSYSTEM
- logic
* - ``rst_ni``
- in
- Asynchronous reset active low
- SUBSYSTEM
- logic
* - ``flush_i``
- in
- Flush
- CONTROLLER
- logic
* - ``stall_st_pending_i``
- in
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``no_st_pending_o``
- out
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``store_buffer_empty_o``
- out
- Store buffer is empty
- TO_BE_COMPLETED
- logic
* - ``valid_i``
- in
- Store instruction is valid
- ISSUE_STAGE
- logic
* - ``lsu_ctrl_i``
- in
- Data input
- ISSUE_STAGE
- lsu_ctrl_t
* - ``pop_st_o``
- out
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``commit_i``
- in
- Instruction commit
- TO_BE_COMPLETED
- logic
* - ``commit_ready_o``
- out
- TO_BE_COMPLETED
- TO_BE_COMPLETED
- logic
* - ``valid_o``
- out
- Store result is valid
- ISSUE_STAGE
- logic
* - ``trans_id_o``
- out
- Transaction ID
- ISSUE_STAGE
- logic[TRANS_ID_BITS-1:0]
* - ``result_o``
- out
- Store result
- ISSUE_STAGE
- riscv::xlen_t
* - ``ex_o``
- out
- Store exception output
- TO_BE_COMPLETED
- exception_t
* - ``translation_req_o``
- out
- Address translation request
- TO_BE_COMPLETED
- logic
* - ``vaddr_o``
- out
- Virtual address
- TO_BE_COMPLETED
- logic[riscv::VLEN-1:0]
* - ``paddr_i``
- in
- Physical address
- TO_BE_COMPLETED
- logic[riscv::PLEN-1:0]
* - ``ex_i``
- in
- Exception raised before store
- TO_BE_COMPLETED
- exception_t
* - ``page_offset_i``
- in
- Address to be checked
- load_unit
- logic[11:0]
* - ``page_offset_matches_o``
- out
- Address check result
- load_unit
- logic
* - ``req_port_i``
- in
- Data cache request
- CACHES
- dcache_req_o_t
* - ``req_port_o``
- out
- Data cache response
- CACHES
- dcache_req_i_t
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
| As RVA = 0,
| ``amo_valid_commit_i`` input is tied to 0
| ``amo_req_o`` output is tied to 0
| ``amo_resp_i`` input is tied to 0
| As IsRVFI = 0,
| ``rvfi_mem_paddr_o`` output is tied to 0
| For any HW configuration,
| ``dtlb_hit_i`` input is tied to 1

63
docs/scripts/define_blacklist.py
View file

@ -13,7 +13,8 @@
def define_blacklist(parameters):
black_list = {}
black_list["flush_bp_i"] = ["For any HW configuration", "zero"]
black_list["flush_bp_i"] = ["For any HW configuration", "0"]
black_list["dtlb_hit_i"] = ["For any HW configuration", "1"]
param = "IsRVFI"
paramvalue = "0"
@ -23,14 +24,42 @@ def define_blacklist(parameters):
param = "DebugEn"
paramvalue = parameters[param].value
if paramvalue == "0":
black_list["set_debug_pc_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["set_debug_pc_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["debug_mode_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["debug_mode_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["debug_req_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["single_step_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["single_step_i"] = [f"As {param} = {paramvalue}", "0"]
param = "RVV"
paramvalue = parameters[param].value
if paramvalue == "0":
black_list["vs_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["vs_o"] = [f"As {param} = {paramvalue}", "0"]
param = "RVS"
paramvalue = parameters[param].value
if paramvalue == "0":
black_list["en_translation_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["enable_translation_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["enable_translation_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["en_ld_st_translation_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["en_ld_st_translation_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["sum_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["sum_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["satp_ppn_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["satp_ppn_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["vaddr_to_be_flushed_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["vaddr_to_be_flushed_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["asid_to_be_flushed_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["asid_to_be_flushed_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["mxr_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["mxr_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["asid_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["asid_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["sfence_vma_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["sfence_vma_i"] = [f"As {param} = {paramvalue}", "0"]
param = "EnableAccelerator"
paramvalue = parameters[param].value
@ -40,10 +69,13 @@ def define_blacklist(parameters):
param = "RVF"
paramvalue = parameters[param].value
if paramvalue == "0":
black_list["fs_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["fs_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["frm_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["frm_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["fpu_valid_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["fpu_ready_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["fpu_ready_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["fpu_fmt_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["fpu_rm_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["fpu_valid_i"] = [f"As {param} = {paramvalue}", "0"]
@ -54,31 +86,54 @@ def define_blacklist(parameters):
black_list["fpu_trans_id_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["fpu_result_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["fpu_exception_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["csr_write_fflags_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["fflags_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["csr_write_fflags_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["fprec_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["dirty_fp_state_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["dirty_fp_state_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["we_fpr_i"] = [f"As {param} = {paramvalue}", "0"]
param = "RVA"
paramvalue = parameters[param].value
if paramvalue == "0":
black_list["amo_req_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["amo_resp_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["amo_valid_commit_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["amo_valid_commit_i"] = [f"As {param} = {paramvalue}", "0"]
param = "PRIV"
paramvalue = "MachineOnly"
if paramvalue == "MachineOnly": # TODO PRIV to be added to RTL parameters
black_list["ld_st_priv_lvl_o"] = [f"As {param} = {paramvalue}", "MAchineMode"]
black_list["ld_st_priv_lvl_i"] = [f"As {param} = {paramvalue}", "MAchineMode"]
black_list["priv_lvl_o"] = [f"As {param} = {paramvalue}", "MachineMode"]
black_list["priv_lvl_i"] = [f"As {param} = {paramvalue}", "MachineMode"]
# black_list["tvm_i"] = [f"As {param} = {paramvalue}", "0"]
# black_list["tw_i"] = [f"As {param} = {paramvalue}", "0"]
# black_list["tsr_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["tvm_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["tvm_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["tw_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["tw_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["tsr_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["tsr_i"] = [f"As {param} = {paramvalue}", "0"]
param = "PerfCounterEn"
paramvalue = "0"
if paramvalue == "0": # TODO PerfCounterEn to be added to RTL parameters
black_list["PERF_COUNTERS"] = [f"As {param} = {paramvalue}", "0"]
param = "FenceEn"
paramvalue = "0"
if paramvalue == "0": # TODO FenceEn to be added to RTL parameters
black_list["fence_i_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["fence_i_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["fence_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["fence_i"] = [f"As {param} = {paramvalue}", "0"]
param = "MMUPresent"
paramvalue = "0"
if paramvalue == "0": # TODO the MMUPresent to be added to RTL parameters
black_list["flush_tlb_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["flush_tlb_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["dtlb_ppn_i"] = [f"As {param} = {paramvalue}", "0"]
return black_list

27
docs/scripts/spec_builder.py
View file

@ -48,6 +48,17 @@ if __name__ == "__main__":
file.append("../core/compressed_decoder.sv")
file.append("../core/scoreboard.sv")
file.append("../core/issue_read_operands.sv")
file.append("../core/alu.sv")
file.append("../core/branch_unit.sv")
file.append("../core/csr_buffer.sv")
file.append("../core/mult.sv")
file.append("../core/multiplier.sv")
file.append("../core/serdiv.sv")
file.append("../core/load_store_unit.sv")
file.append("../core/load_unit.sv")
file.append("../core/store_unit.sv")
file.append("../core/lsu_bypass.sv")
file.append("../core/cvxif_fu.sv")
black_list = define_blacklist(parameters)
@ -128,7 +139,7 @@ if __name__ == "__main__":
)
fout.write(" Original Author: Jean-Roch COULON - Thales\n\n")
fout.write(f".. _CVA6_{module}_ports:\n\n")
fout.write(f".. list-table:: {module} module IO ports\n")
fout.write(f".. list-table:: **{module} module** IO ports\n")
fout.write(" :header-rows: 1\n")
fout.write("\n")
fout.write(" * - Signal\n")
@ -144,11 +155,11 @@ if __name__ == "__main__":
fout.write(f" - {port.connexion}\n")
fout.write(f" - {port.data_type}\n")
fout.write("\n")
fout.write(
f"Due to {target} configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below\n"
)
if len(comments) != 0:
fout.write(
f"Due to {target} configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below\n"
)
fout.write("\n")
for comment in comments:
fout.write(f"| {comment[0]},\n| {comment[1]}\n")
fout.write("\n")
for comment in comments:
fout.write(f"| {comment[0]},\n| {comment[1]}\n")
if len(comments) == 0:
fout.write("none\n")