github-mirrors/cva6
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva6.git synced 2025-04-23 13:47:13 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 7

Condition RTL to improve code coverage (#2815)
Some checks failed
bender-up-to-date / bender-up-to-date (push) Has been cancelled
Details
ci / build-riscv-tests (push) Has been cancelled
Details
ci / execute-riscv64-tests (push) Has been cancelled
Details
ci / execute-riscv32-tests (push) Has been cancelled
Details

Browse source 
* decoder.sv : mideleg isn't supported only if RVS is enabled
* commit_stage.sv : commit_drop is high only if we support supercalar
This commit is contained in:
Jalali 2025-03-07 21:00:47 +00:00 • committed by GitHub
parent 9cd5c7711f
commit f36651b857
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
2 changed files with 3 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

4
core/commit_stage.sv
View file

@ -163,7 +163,7 @@ module commit_stage
// we will not commit the instruction if we took an exception
if (commit_instr_i[0].ex.valid) begin
// However we can drop it (with its exception)
if (commit_drop_i[0]) begin
if (CVA6Cfg.SpeculativeSb && commit_drop_i[0]) begin
commit_ack_o[0] = 1'b1;
end
end else begin
@ -378,7 +378,7 @@ module commit_stage
exception_o.gva = 1'b0;
// we need a valid instruction in the commit stage
if (commit_instr_i[0].valid && !commit_drop_i[0]) begin
if (commit_instr_i[0].valid && !(CVA6Cfg.SpeculativeSb && commit_drop_i[0])) begin
// ------------------------
// check for CSR exception
// ------------------------

2
core/decoder.sv
View file

@ -1686,7 +1686,7 @@ module decoder
// However, if bit i in mideleg is set, interrupts are considered to be globally enabled if the hart’s current privilege
// mode equals the delegated privilege mode (S or U) and that mode’s interrupt enable bit
// (SIE or UIE in mstatus) is set, or if the current privilege mode is less than the delegated privilege mode.
if (irq_ctrl_i.mideleg[interrupt_cause[$clog2(CVA6Cfg.XLEN)-1:0]]) begin
if (CVA6Cfg.RVS && irq_ctrl_i.mideleg[interrupt_cause[$clog2(CVA6Cfg.XLEN)-1:0]]) begin
if (CVA6Cfg.RVH) begin : hyp_int_gen
if (v_i && irq_ctrl_i.hideleg[interrupt_cause[$clog2(CVA6Cfg.XLEN)-1:0]]) begin
if ((irq_ctrl_i.sie && priv_lvl_i == riscv::PRIV_LVL_S) || priv_lvl_i == riscv::PRIV_LVL_U) begin