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Add CV64A6_MMU core in user manual (#2324)
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25
docs/01_cva6_user/CSR_CV64A6_MMU.rst
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25
docs/01_cva6_user/CSR_CV64A6_MMU.rst
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..
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Copyright (c) 2023 OpenHW Group
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Copyright (c) 2023 Thales DIS design services SAS
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SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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.. Level 1
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=======
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Level 2
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-------
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Level 3
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~~~~~~~
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Level 4
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^^^^^^^
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.. _CSR_CV64A6_MMU:
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CV64A6_MMU Control Status Registers
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==================================
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*This chapter is not yet available.*
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docs/01_cva6_user/CSR_CV64A6_MMU_list.rst
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docs/01_cva6_user/CSR_CV64A6_MMU_list.rst
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..
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Copyright (c) 2023 OpenHW Group
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Copyright (c) 2023 Thales DIS design services SAS
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SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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.. Level 1
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=======
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Level 2
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-------
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Level 3
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~~~~~~~
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Level 4
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^^^^^^^
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.. _CSR_CV64A6_MMU_list:
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CV64A6_MMU Control Status Registers List
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=======================================
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*This chapter is not yet available.*
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@ -27,6 +27,7 @@
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"CV32A60AX", "Performance counters included"
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"CV32A60X", "No performance counters"
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"CV64A6_MMU", "No performance counters"
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CSR performance counters control
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================================
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@ -33,6 +33,7 @@ with external coprocessors.
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"CV32A60AX", "CV-X-IF included"
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"CV32A60X", "CV-X-IF included"
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"CV64A6_MMU", "CV-X-IF included"
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CV-X-IF interface specification
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@ -34,6 +34,7 @@ The AXI interface is described in a separate chapter.
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"CV32A60AX", "AXI implemented"
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"CV32A60X", "AXI implemented"
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"CV64A6_MMU", "AXI implemented"
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Debug Interface
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---------------
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@ -52,6 +53,7 @@ Debug Interface
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"CV32A60AX", "Debug interface implemented"
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"CV32A60X", "No debug interface"
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"CV64A6_MMU", "Debug interface implemented"
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Interrupt Interface
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-------------------
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@ -77,3 +79,4 @@ For more information, refer to OpenPiton documents.
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"CV32A60AX", "No TRI interface"
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"CV32A60X", "No TRI interface"
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"CV64A6_MMU", "No TRI interface"
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@ -102,6 +102,7 @@ As of today, two configurations are being verified and addressed in this documen
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"**CV32A60AX**", "32-bit **application** core", "ASIC", "Machine, Supervisor, User", "RV32IMACZicsr_Zifencei_Zicount_Zba_Zbb_Zbc_Zbs_Zcb_Zicond", "Included"
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"**CV32A60X**", "32-bit **embedded** core", "ASIC", "Machine only", "RV32IMCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs_Zcb", "Included"
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"**CV64A6_MMU**", "64-bit **embedded** core with MMU", "ASIC", "Machine, Supervisor, User", "RV64IMCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs_Zcb", "Included"
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CV32A60X is an interim part number until the team can decide if this configuration is single- or dual-issue.
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If the dual-issue architecture is selected, the part number will become CV32A65X to denote the extra performance.
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@ -108,6 +108,29 @@ These extensions are available in CV32A60X:
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"RVZifencei - Instruction-Fetch Fence", "✔"
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"RVZicond - Integer Conditional Operations(Ratification pending)", ""
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CV64A6_MMU extensions
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~~~~~~~~~~~~~~~~~~~
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These extensions are available in CV64A6_MMU:
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.. csv-table::
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:widths: auto
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:align: left
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:header: "Extension", "Available in CV64A6_MMU"
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"RV32I - Base Integer Instruction Set", "✔"
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"RV32A - Atomic Instructions", ""
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"RV32Zb* - Bit-Manipulation (Zba, Zbb, Zbc, Zbs)", "✔"
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"RV32C - Compressed Instructions ", "✔"
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"RV32Zcb - Code Size Reduction", "✔"
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"RVZcmp - Code Size Reduction", "✔"
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"RV32D - Double precision floating-point", ""
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"RV32F - Single precision floating-point", ""
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"RV32M - Integer Multiply/Divide", "✔"
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"RVZicount - Performance Counters", ""
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"RVZicsr - Control and Status Register Instructions", "✔"
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"RVZifencei - Instruction-Fetch Fence", "✔"
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"RVZicond - Integer Conditional Operations(Ratification pending)", ""
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RISC-V Privileges
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-----------------
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@ -158,6 +181,19 @@ These privilege modes are available in CV32A60X:
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"S - Supervior", ""
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"U - User", ""
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CV64A6_MMU privilege modes
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~~~~~~~~~~~~~~~~~~~~~~~~~
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These privilege modes are available in CV64A6_MMU:
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.. csv-table::
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:widths: auto
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:align: left
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:header: "Privileges", "Available in CV64A6_MMU"
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"M - Machine", "✔"
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"S - Supervior", "✔"
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"U - User", "✔"
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RISC-V Virtual Memory
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---------------------
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@ -209,6 +245,10 @@ CV32A60X virtual memory
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CV32A60X integrates no MMU and only supports the **Bare** addressing mode.
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CV64A6_MMU virtual memory
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~~~~~~~~~~~~~~~~~~~~~~~~
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CV64A6_MMU integrates an MMU and supports both the **Bare** and **Sv39** addressing modes.
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Memory Alignment
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----------------
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@ -27,6 +27,7 @@
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"CV32A60AX", "Implemented extension"
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"CV32A60X", "Not implemented extension"
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"CV64A6_MMU", "Not implemented extension"
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**Note**: This chapter is specific to CV32A6 configurations. CV64A6 configurations implement as an option RV64A, that includes additional instructions.
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@ -27,6 +27,7 @@
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"CV32A60AX", "Implemented extension"
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"CV32A60X", "Implemented extension"
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"CV64A6_MMU", "Implemented extension"
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**Note**: This chapter is specific to CV32A6 configurations. CV64A6 configurations implement as an option RV64C, that includes a different list of instructions.
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@ -29,6 +29,7 @@ This chapter is applicable to all CV32A6 configurations.
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"CV32A60AX", "Implemented extension"
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"CV32A60X", "Implemented extension"
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"CV64A6_MMU", "Implemented extension"
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**Note**: CV64A6 implements RV64I that includes additional instructions.
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@ -29,6 +29,7 @@ This chapter is applicable to all CV32A6 configurations.
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"CV32A60AX", "Implemented extension"
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"CV32A60X", "Implemented extension"
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"CV64A6_MMU", "Implemented extension"
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**Note**: CV64A6 implements RV64M that includes additional instructions.
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"CV32A60AX", "Implemented extension"
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"CV32A60X", "Implemented extension"
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"CV64A6_MMU", "Implemented extension"
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**Note**: This chapter is specific to CV32A6 configurations. CV64A6 configurations implement as an option RV64Zcb, that includes one additional instruction.
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@ -27,6 +27,7 @@
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"CV32A60AX", "Implemented extension"
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"CV32A60X", "Implemented extension"
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"CV64A6_MMU", "Implemented extension"
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======================================
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@ -27,6 +27,7 @@
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"CV32A60AX", "Implemented extension"
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"CV32A60X", "Implemented extension"
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"CV64A6_MMU", "Implemented extension"
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=============================
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RVZbb: Basic bit-manipulation
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@ -27,6 +27,7 @@
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"CV32A60AX", "Implemented extension"
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"CV32A60X", "Implemented extension"
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"CV64A6_MMU", "Implemented extension"
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=================================
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@ -27,6 +27,7 @@
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"CV32A60AX", "Implemented extension"
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"CV32A60X", "Implemented extension"
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"CV64A6_MMU", "Implemented extension"
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==============================
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:header: "Configuration", "Implementation"
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"CV32A60X", "Implemented extension"
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"CV64A6_MMU", "Implemented extension"
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**Note**: Zcmp is primarily targeted at embedded class CPUs due to implementation complexity. Additionally, it is not compatible with architecture class profiles.
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@ -27,6 +27,7 @@
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"CV32A60AX", "Implemented extension"
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"CV32A60X", "Not implemented extension"
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"CV64A6_MMU", "Not implemented extension"
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**Note**: RV32Zicond and RV64Zicond are identical.
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@ -49,6 +49,8 @@ CVA6 User Manual
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CV32A60X CSR Details <CSR_CV32A60X>
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CV32A60AX CSR List <CSR_CV32A60AX_list>
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CV32A60AX CSR Details <CSR_CV32A60AX>
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CV64A6_MMU CSR List <CSR_CV64A6_MMU_list>
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CV64A6_MMU CSR Details <CSR_CV64A6_MMU>
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CV64A6 CSR <CV64A6_Control_Status_Registers>
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CSR_Cache_Control
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CSR Performance Counters <CSR_Performance_Counters>
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