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Fix MIE CSR described in #2004 and #2008 Github issue (#2017)

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JeanRochCoulon 2024-04-08 19:54:55 +02:00 • committed by GitHub
parent 90d780eb14
commit f4ec364bf4
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2 changed files with 17 additions and 9 deletions
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4
.gitlab-ci/expected_synth.yml
View file

@ -1,4 +1,4 @@
cv32a6_embedded:
gates: 110738
gates: 110095
cv32a65x:
gates: 110129
gates: 109555

22
core/csr_regfile.sv
View file

@ -1306,12 +1306,18 @@ module csr_regfile
| CVA6Cfg.XLEN'(riscv::MIP_MTIP)
| CVA6Cfg.XLEN'(riscv::MIP_MEIP);
end else begin
mask = CVA6Cfg.XLEN'(riscv::MIP_SSIP)
| CVA6Cfg.XLEN'(riscv::MIP_STIP)
| CVA6Cfg.XLEN'(riscv::MIP_SEIP)
| CVA6Cfg.XLEN'(riscv::MIP_MSIP)
| CVA6Cfg.XLEN'(riscv::MIP_MTIP)
| CVA6Cfg.XLEN'(riscv::MIP_MEIP);
if (CVA6Cfg.RVS) begin
mask = CVA6Cfg.XLEN'(riscv::MIP_SSIP)
| CVA6Cfg.XLEN'(riscv::MIP_STIP)
| CVA6Cfg.XLEN'(riscv::MIP_SEIP)
| CVA6Cfg.XLEN'(riscv::MIP_MSIP)
| CVA6Cfg.XLEN'(riscv::MIP_MTIP)
| CVA6Cfg.XLEN'(riscv::MIP_MEIP);
end else begin
mask = CVA6Cfg.XLEN'(riscv::MIP_MSIP)
| CVA6Cfg.XLEN'(riscv::MIP_MTIP)
| CVA6Cfg.XLEN'(riscv::MIP_MEIP);
end
end
mie_d = (mie_q & ~mask) | (csr_wdata & mask); // we only support supervisor and M-mode interrupts
end
@ -1346,10 +1352,12 @@ module csr_regfile
| CVA6Cfg.XLEN'(riscv::MIP_STIP)
| CVA6Cfg.XLEN'(riscv::MIP_SEIP)
| CVA6Cfg.XLEN'(riscv::MIP_VSSIP);
end else begin
end else if (CVA6Cfg.RVS) begin
mask = CVA6Cfg.XLEN'(riscv::MIP_SSIP)
| CVA6Cfg.XLEN'(riscv::MIP_STIP)
| CVA6Cfg.XLEN'(riscv::MIP_SEIP);
end else begin
mask = '0;
end
mip_d = (mip_q & ~mask) | (csr_wdata & mask);
end