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Merge branch 'master' into JeanRochCoulon-patch-1
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JeanRochCoulon 2024-12-16 11:53:58 +01:00 • committed by GitHub
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3 changed files with 13 additions and 10 deletions
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2
.gitlab-ci/expected_synth.yml
View file

@ -1,2 +1,2 @@
cv32a65x: cv32a65x:
gates: 188627 gates: 187456

11
core/cva6_mmu/cva6_mmu.sv
View file

@ -133,6 +133,7 @@ module cva6_mmu
logic iaccess_err; // insufficient privilege to access this instruction page logic iaccess_err; // insufficient privilege to access this instruction page
logic i_g_st_access_err; // insufficient privilege at g stage to access this instruction page logic i_g_st_access_err; // insufficient privilege at g stage to access this instruction page
logic daccess_err; // insufficient privilege to access this data page logic daccess_err; // insufficient privilege to access this data page
logic canonical_addr_check; // canonical check on the virtual address for SV39
logic d_g_st_access_err; // insufficient privilege to access this data page logic d_g_st_access_err; // insufficient privilege to access this data page
logic ptw_active; // PTW is currently walking a page table logic ptw_active; // PTW is currently walking a page table
logic walking_instr; // PTW is walking because of an ITLB miss logic walking_instr; // PTW is walking because of an ITLB miss
@ -380,7 +381,7 @@ module cva6_mmu
// we work with SV39 or SV32, so if VM is enabled, check that all bits [CVA6Cfg.VLEN-1:CVA6Cfg.SV-1] are equal // we work with SV39 or SV32, so if VM is enabled, check that all bits [CVA6Cfg.VLEN-1:CVA6Cfg.SV-1] are equal
if (icache_areq_i.fetch_req && !((&icache_areq_i.fetch_vaddr[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b1 || (|icache_areq_i.fetch_vaddr[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b0)) begin if (icache_areq_i.fetch_req && !((&icache_areq_i.fetch_vaddr[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b1 || (|icache_areq_i.fetch_vaddr[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b0)) begin
icache_areq_o.fetch_exception.cause = riscv::INSTR_ACCESS_FAULT; icache_areq_o.fetch_exception.cause = riscv::INSTR_PAGE_FAULT;
icache_areq_o.fetch_exception.valid = 1'b1; icache_areq_o.fetch_exception.valid = 1'b1;
if (CVA6Cfg.TvalEn) if (CVA6Cfg.TvalEn)
icache_areq_o.fetch_exception.tval = CVA6Cfg.XLEN'(icache_areq_i.fetch_vaddr); icache_areq_o.fetch_exception.tval = CVA6Cfg.XLEN'(icache_areq_i.fetch_vaddr);
@ -512,6 +513,10 @@ module cva6_mmu
lsu_valid_o = lsu_req_q; lsu_valid_o = lsu_req_q;
lsu_exception_o = misaligned_ex_i; lsu_exception_o = misaligned_ex_i;
// we work with SV39 or SV32, so if VM is enabled, check that all bits [CVA6Cfg.VLEN-1:CVA6Cfg.SV-1] are equal to bit [CVA6Cfg.SV]
canonical_addr_check = (lsu_req_i && en_ld_st_translation_i &&
!((&lsu_vaddr_i[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b1 || (|lsu_vaddr_i[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b0));
// Check if the User flag is set, then we may only access it in supervisor mode // Check if the User flag is set, then we may only access it in supervisor mode
// if SUM is enabled // if SUM is enabled
daccess_err = en_ld_st_translation_i && daccess_err = en_ld_st_translation_i &&
@ -578,7 +583,7 @@ module cva6_mmu
lsu_exception_o.tinst = '0; lsu_exception_o.tinst = '0;
lsu_exception_o.gva = ld_st_v_i; lsu_exception_o.gva = ld_st_v_i;
end end
end else if ((en_ld_st_translation_i || !CVA6Cfg.RVH) && (!dtlb_pte_q.w || daccess_err || !dtlb_pte_q.d)) begin end else if ((en_ld_st_translation_i || !CVA6Cfg.RVH) && (!dtlb_pte_q.w || daccess_err || canonical_addr_check || !dtlb_pte_q.d)) begin
lsu_exception_o.cause = riscv::STORE_PAGE_FAULT; lsu_exception_o.cause = riscv::STORE_PAGE_FAULT;
lsu_exception_o.valid = 1'b1; lsu_exception_o.valid = 1'b1;
if (CVA6Cfg.TvalEn) if (CVA6Cfg.TvalEn)
@ -606,7 +611,7 @@ module cva6_mmu
lsu_exception_o.gva = ld_st_v_i; lsu_exception_o.gva = ld_st_v_i;
end end
// check for sufficient access privileges - throw a page fault if necessary // check for sufficient access privileges - throw a page fault if necessary
end else if (daccess_err) begin end else if (daccess_err || canonical_addr_check) begin
lsu_exception_o.cause = riscv::LOAD_PAGE_FAULT; lsu_exception_o.cause = riscv::LOAD_PAGE_FAULT;
lsu_exception_o.valid = 1'b1; lsu_exception_o.valid = 1'b1;
if (CVA6Cfg.TvalEn) if (CVA6Cfg.TvalEn)

2
core/serdiv.sv
View file

@ -218,8 +218,6 @@ module serdiv
endcase endcase
if (flush_i) begin if (flush_i) begin
in_rdy_o = 1'b0;
out_vld_o = 1'b0;
a_reg_en = 1'b0; a_reg_en = 1'b0;
b_reg_en = 1'b0; b_reg_en = 1'b0;
load_en = 1'b0; load_en = 1'b0;