Altera apu agilex7 (#2647)

This PR is adding the APU design adapted to Altera Agilex7 FPGA.

It does not include integration in the Makefile nor automatic generation of Altera IPs, that will be the last PR of the Altera support.

.gitmodules

@@ -49,3 +49,9 @@
 [submodule "docs/06_cv32a65x_riscv/riscv-isa-manual"]
 	path = docs/riscv-isa/riscv-isa-manual
 	url = https://github.com/riscv/riscv-isa-manual.git
+[submodule "corev_apu/fpga/src/apb"]
+	path = corev_apu/fpga/src/apb
+	url = https://github.com/pulp-platform/apb.git
+[submodule "corev_apu/fpga/src/gpio"]
+	path = corev_apu/fpga/src/gpio
+	url = https://github.com/pulp-platform/gpio.git

corev_apu/altera/src/cva6_altera_peripherals.sv

@@ -0,0 +1,743 @@
+// Copyright 2018 ETH Zurich and University of Bologna.
+// Copyright 2024 PlanV Technology
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+// Intel Peripherals
+
+`include "register_interface/assign.svh"
+`include "register_interface/typedef.svh"
+
+module cva6_peripherals #(
+    parameter int AxiAddrWidth = -1,
+    parameter int AxiDataWidth = -1,
+    parameter int AxiIdWidth   = -1,
+    parameter int AxiUserWidth = 1,
+    parameter bit InclUART     = 1,
+    parameter bit InclSPI      = 0,
+    parameter bit InclEthernet = 0,
+    parameter bit InclGPIO     = 0,
+    parameter bit InclTimer    = 1
+) (
+    input  logic       clk_i           , // Clock
+    input  logic       clk_200MHz_i    ,
+    input  logic       rst_ni          , // Asynchronous reset active low
+    AXI_BUS.Slave      plic            ,
+    AXI_BUS.Slave      uart            ,
+    AXI_BUS.Slave      spi             ,
+    AXI_BUS.Slave      gpio            ,
+    AXI_BUS.Slave      ethernet        ,
+    AXI_BUS.Slave      timer           ,
+    output logic [1:0] irq_o           ,
+    // UART
+    input  logic       rx_i            ,
+    output logic       tx_o            ,
+    // Ethernet
+    input  logic       eth_clk_i       ,
+    input  wire        eth_rxck        ,
+    input  wire        eth_rxctl       ,
+    input  wire [3:0]  eth_rxd         ,
+    output wire        eth_txck        ,
+    output wire        eth_txctl       ,
+    output wire [3:0]  eth_txd         ,
+    output wire        eth_rst_n       ,
+    input  logic       phy_tx_clk_i    , // 125 MHz Clock
+    // MDIO Interface
+    inout  wire        eth_mdio        ,
+    output logic       eth_mdc         ,
+    // SPI
+    output logic       spi_clk_o       ,
+    output logic       spi_mosi        ,
+    input  logic       spi_miso        ,
+    output logic       spi_ss          ,
+    // SD Card
+    input  logic       sd_clk_i        ,
+    output logic [7:0] leds_o          ,
+    input  logic [7:0] dip_switches_i
+);
+
+    // ---------------
+    // 1. PLIC
+    // ---------------
+    logic [ariane_soc::NumSources-1:0] irq_sources;
+
+    // Unused interrupt sources
+    assign irq_sources[ariane_soc::NumSources-1:7] = '0;
+
+    REG_BUS #(
+        .ADDR_WIDTH ( 32 ),
+        .DATA_WIDTH ( 32 )
+    ) reg_bus (clk_i);
+
+    logic         plic_penable;
+    logic         plic_pwrite;
+    logic [31:0]  plic_paddr;
+    logic         plic_psel;
+    logic [31:0]  plic_pwdata;
+    logic [31:0]  plic_prdata;
+    logic         plic_pready;
+    logic         plic_pslverr;
+
+    axi2apb_64_32 #(
+        .AXI4_ADDRESS_WIDTH ( AxiAddrWidth  ),
+        .AXI4_RDATA_WIDTH   ( AxiDataWidth  ),
+        .AXI4_WDATA_WIDTH   ( AxiDataWidth  ),
+        .AXI4_ID_WIDTH      ( AxiIdWidth    ),
+        .AXI4_USER_WIDTH    ( AxiUserWidth  ),
+        .BUFF_DEPTH_SLAVE   ( 2             ),
+        .APB_ADDR_WIDTH     ( 32            )
+    ) i_axi2apb_64_32_plic (
+        .ACLK      ( clk_i          ),
+        .ARESETn   ( rst_ni         ),
+        .test_en_i ( 1'b0           ),
+        .AWID_i    ( plic.aw_id     ),
+        .AWADDR_i  ( plic.aw_addr   ),
+        .AWLEN_i   ( plic.aw_len    ),
+        .AWSIZE_i  ( plic.aw_size   ),
+        .AWBURST_i ( plic.aw_burst  ),
+        .AWLOCK_i  ( plic.aw_lock   ),
+        .AWCACHE_i ( plic.aw_cache  ),
+        .AWPROT_i  ( plic.aw_prot   ),
+        .AWREGION_i( plic.aw_region ),
+        .AWUSER_i  ( plic.aw_user   ),
+        .AWQOS_i   ( plic.aw_qos    ),
+        .AWVALID_i ( plic.aw_valid  ),
+        .AWREADY_o ( plic.aw_ready  ),
+        .WDATA_i   ( plic.w_data    ),
+        .WSTRB_i   ( plic.w_strb    ),
+        .WLAST_i   ( plic.w_last    ),
+        .WUSER_i   ( plic.w_user    ),
+        .WVALID_i  ( plic.w_valid   ),
+        .WREADY_o  ( plic.w_ready   ),
+        .BID_o     ( plic.b_id      ),
+        .BRESP_o   ( plic.b_resp    ),
+        .BVALID_o  ( plic.b_valid   ),
+        .BUSER_o   ( plic.b_user    ),
+        .BREADY_i  ( plic.b_ready   ),
+        .ARID_i    ( plic.ar_id     ),
+        .ARADDR_i  ( plic.ar_addr   ),
+        .ARLEN_i   ( plic.ar_len    ),
+        .ARSIZE_i  ( plic.ar_size   ),
+        .ARBURST_i ( plic.ar_burst  ),
+        .ARLOCK_i  ( plic.ar_lock   ),
+        .ARCACHE_i ( plic.ar_cache  ),
+        .ARPROT_i  ( plic.ar_prot   ),
+        .ARREGION_i( plic.ar_region ),
+        .ARUSER_i  ( plic.ar_user   ),
+        .ARQOS_i   ( plic.ar_qos    ),
+        .ARVALID_i ( plic.ar_valid  ),
+        .ARREADY_o ( plic.ar_ready  ),
+        .RID_o     ( plic.r_id      ),
+        .RDATA_o   ( plic.r_data    ),
+        .RRESP_o   ( plic.r_resp    ),
+        .RLAST_o   ( plic.r_last    ),
+        .RUSER_o   ( plic.r_user    ),
+        .RVALID_o  ( plic.r_valid   ),
+        .RREADY_i  ( plic.r_ready   ),
+        .PENABLE   ( plic_penable   ),
+        .PWRITE    ( plic_pwrite    ),
+        .PADDR     ( plic_paddr     ),
+        .PSEL      ( plic_psel      ),
+        .PWDATA    ( plic_pwdata    ),
+        .PRDATA    ( plic_prdata    ),
+        .PREADY    ( plic_pready    ),
+        .PSLVERR   ( plic_pslverr   )
+    );
+
+    apb_to_reg i_apb_to_reg (
+        .clk_i     ( clk_i        ),
+        .rst_ni    ( rst_ni       ),
+        .penable_i ( plic_penable ),
+        .pwrite_i  ( plic_pwrite  ),
+        .paddr_i   ( plic_paddr   ),
+        .psel_i    ( plic_psel    ),
+        .pwdata_i  ( plic_pwdata  ),
+        .prdata_o  ( plic_prdata  ),
+        .pready_o  ( plic_pready  ),
+        .pslverr_o ( plic_pslverr ),
+        .reg_o     ( reg_bus      )
+    );
+
+    // define reg type according to REG_BUS above
+    `REG_BUS_TYPEDEF_ALL(plic, logic[31:0], logic[31:0], logic[3:0])
+    plic_req_t plic_req;
+    plic_rsp_t plic_rsp;
+
+    // assign REG_BUS.out to (req_t, rsp_t) pair 
+    `REG_BUS_ASSIGN_TO_REQ(plic_req, reg_bus)
+    `REG_BUS_ASSIGN_FROM_RSP(reg_bus, plic_rsp)
+
+    plic_top #(
+      .N_SOURCE    ( ariane_soc::NumSources  ),
+      .N_TARGET    ( ariane_soc::NumTargets  ),
+      .MAX_PRIO    ( ariane_soc::MaxPriority ),
+      .reg_req_t   ( plic_req_t              ),
+      .reg_rsp_t   ( plic_rsp_t              )
+    ) i_plic (
+      .clk_i,
+      .rst_ni,
+      .req_i         ( plic_req    ),
+      .resp_o        ( plic_rsp    ),
+      .le_i          ( '0          ), // 0:level 1:edge
+      .irq_sources_i ( irq_sources ),
+      .eip_targets_o ( irq_o       )
+    );
+
+    // ---------------
+    // 2. UART
+    // ---------------
+    logic         uart_penable;
+    logic         uart_pwrite;
+    logic [31:0]  uart_paddr;
+    logic         uart_psel;
+    logic [31:0]  uart_pwdata;
+    logic [31:0]  uart_prdata;
+    logic         uart_pready;
+    logic         uart_pslverr;
+
+    axi2apb_64_32 #(
+        .AXI4_ADDRESS_WIDTH ( AxiAddrWidth ),
+        .AXI4_RDATA_WIDTH   ( AxiDataWidth ),
+        .AXI4_WDATA_WIDTH   ( AxiDataWidth ),
+        .AXI4_ID_WIDTH      ( AxiIdWidth   ),
+        .AXI4_USER_WIDTH    ( AxiUserWidth ),
+        .BUFF_DEPTH_SLAVE   ( 2            ),
+        .APB_ADDR_WIDTH     ( 32           )
+    ) i_axi2apb_64_32_uart (
+        .ACLK      ( clk_i          ),
+        .ARESETn   ( rst_ni         ),
+        .test_en_i ( 1'b0           ),
+        .AWID_i    ( uart.aw_id     ),
+        .AWADDR_i  ( uart.aw_addr   ),
+        .AWLEN_i   ( uart.aw_len    ),
+        .AWSIZE_i  ( uart.aw_size   ),
+        .AWBURST_i ( uart.aw_burst  ),
+        .AWLOCK_i  ( uart.aw_lock   ),
+        .AWCACHE_i ( uart.aw_cache  ),
+        .AWPROT_i  ( uart.aw_prot   ),
+        .AWREGION_i( uart.aw_region ),
+        .AWUSER_i  ( uart.aw_user   ),
+        .AWQOS_i   ( uart.aw_qos    ),
+        .AWVALID_i ( uart.aw_valid  ),
+        .AWREADY_o ( uart.aw_ready  ),
+        .WDATA_i   ( uart.w_data    ),
+        .WSTRB_i   ( uart.w_strb    ),
+        .WLAST_i   ( uart.w_last    ),
+        .WUSER_i   ( uart.w_user    ),
+        .WVALID_i  ( uart.w_valid   ),
+        .WREADY_o  ( uart.w_ready   ),
+        .BID_o     ( uart.b_id      ),
+        .BRESP_o   ( uart.b_resp    ),
+        .BVALID_o  ( uart.b_valid   ),
+        .BUSER_o   ( uart.b_user    ),
+        .BREADY_i  ( uart.b_ready   ),
+        .ARID_i    ( uart.ar_id     ),
+        .ARADDR_i  ( uart.ar_addr   ),
+        .ARLEN_i   ( uart.ar_len    ),
+        .ARSIZE_i  ( uart.ar_size   ),
+        .ARBURST_i ( uart.ar_burst  ),
+        .ARLOCK_i  ( uart.ar_lock   ),
+        .ARCACHE_i ( uart.ar_cache  ),
+        .ARPROT_i  ( uart.ar_prot   ),
+        .ARREGION_i( uart.ar_region ),
+        .ARUSER_i  ( uart.ar_user   ),
+        .ARQOS_i   ( uart.ar_qos    ),
+        .ARVALID_i ( uart.ar_valid  ),
+        .ARREADY_o ( uart.ar_ready  ),
+        .RID_o     ( uart.r_id      ),
+        .RDATA_o   ( uart.r_data    ),
+        .RRESP_o   ( uart.r_resp    ),
+        .RLAST_o   ( uart.r_last    ),
+        .RUSER_o   ( uart.r_user    ),
+        .RVALID_o  ( uart.r_valid   ),
+        .RREADY_i  ( uart.r_ready   ),
+        .PENABLE   ( uart_penable   ),
+        .PWRITE    ( uart_pwrite    ),
+        .PADDR     ( uart_paddr     ),
+        .PSEL      ( uart_psel      ),
+        .PWDATA    ( uart_pwdata    ),
+        .PRDATA    ( uart_prdata    ),
+        .PREADY    ( uart_pready    ),
+        .PSLVERR   ( uart_pslverr   )
+    );
+
+    if (InclUART) begin : gen_uart
+        apb_uart i_apb_uart (
+            .CLK     ( clk_i           ),
+            .RSTN    ( rst_ni          ),
+            .PSEL    ( uart_psel       ),
+            .PENABLE ( uart_penable    ),
+            .PWRITE  ( uart_pwrite     ),
+            .PADDR   ( uart_paddr[4:2] ),
+            .PWDATA  ( uart_pwdata     ),
+            .PRDATA  ( uart_prdata     ),
+            .PREADY  ( uart_pready     ),
+            .PSLVERR ( uart_pslverr    ),
+            .INT     ( irq_sources[0]  ),
+            .OUT1N   (                 ), // keep open
+            .OUT2N   (                 ), // keep open
+            .RTSN    (                 ), // no flow control
+            .DTRN    (                 ), // no flow control
+            .CTSN    ( 1'b0            ),
+            .DSRN    ( 1'b0            ),
+            .DCDN    ( 1'b0            ),
+            .RIN     ( 1'b0            ),
+            .SIN     ( rx_i            ),
+            .SOUT    ( tx_o            )
+        );
+    end else begin
+        /* pragma translate_off */
+        `ifndef VERILATOR
+        mock_uart i_mock_uart (
+            .clk_i     ( clk_i        ),
+            .rst_ni    ( rst_ni       ),
+            .penable_i ( uart_penable ),
+            .pwrite_i  ( uart_pwrite  ),
+            .paddr_i   ( uart_paddr   ),
+            .psel_i    ( uart_psel    ),
+            .pwdata_i  ( uart_pwdata  ),
+            .prdata_o  ( uart_prdata  ),
+            .pready_o  ( uart_pready  ),
+            .pslverr_o ( uart_pslverr )
+        );
+        `endif
+        /* pragma translate_on */
+    end
+
+    // ---------------
+    // 3. SPI
+    // ---------------
+   assign spi.b_user = 1'b0;
+   assign spi.r_user = 1'b0;
+
+    if (InclSPI) begin : gen_spi
+        logic         spi_penable;
+        logic         spi_pwrite;
+        logic [31:0]  spi_paddr;
+        logic         spi_psel;
+        logic [31:0]  spi_pwdata;
+        logic [31:0]  spi_prdata;
+        logic         spi_pready;
+        logic         spi_pslverr;
+
+        axi2apb_64_32 #(
+            .AXI4_ADDRESS_WIDTH ( AxiAddrWidth ),
+            .AXI4_RDATA_WIDTH   ( AxiDataWidth ),
+            .AXI4_WDATA_WIDTH   ( AxiDataWidth ),
+            .AXI4_ID_WIDTH      ( AxiIdWidth   ),
+            .AXI4_USER_WIDTH    ( AxiUserWidth ),
+            .BUFF_DEPTH_SLAVE   ( 2            ),
+            .APB_ADDR_WIDTH     ( 32           )
+        ) i_axi2apb_64_32_spi (
+            .ACLK      ( clk_i          ),
+            .ARESETn   ( rst_ni         ),
+            .test_en_i ( 1'b0           ),
+            .AWID_i    ( spi.aw_id     ),
+            .AWADDR_i  ( spi.aw_addr   ),
+            .AWLEN_i   ( spi.aw_len    ),
+            .AWSIZE_i  ( spi.aw_size   ),
+            .AWBURST_i ( spi.aw_burst  ),
+            .AWLOCK_i  ( spi.aw_lock   ),
+            .AWCACHE_i ( spi.aw_cache  ),
+            .AWPROT_i  ( spi.aw_prot   ),
+            .AWREGION_i( spi.aw_region ),
+            .AWUSER_i  ( spi.aw_user   ),
+            .AWQOS_i   ( spi.aw_qos    ),
+            .AWVALID_i ( spi.aw_valid  ),
+            .AWREADY_o ( spi.aw_ready  ),
+            .WDATA_i   ( spi.w_data    ),
+            .WSTRB_i   ( spi.w_strb    ),
+            .WLAST_i   ( spi.w_last    ),
+            .WUSER_i   ( spi.w_user    ),
+            .WVALID_i  ( spi.w_valid   ),
+            .WREADY_o  ( spi.w_ready   ),
+            .BID_o     ( spi.b_id      ),
+            .BRESP_o   ( spi.b_resp    ),
+            .BVALID_o  ( spi.b_valid   ),
+            // .BUSER_o   ( spi.b_user    ),
+            .BREADY_i  ( spi.b_ready   ),
+            .ARID_i    ( spi.ar_id     ),
+            .ARADDR_i  ( spi.ar_addr   ),
+            .ARLEN_i   ( spi.ar_len    ),
+            .ARSIZE_i  ( spi.ar_size   ),
+            .ARBURST_i ( spi.ar_burst  ),
+            .ARLOCK_i  ( spi.ar_lock   ),
+            .ARCACHE_i ( spi.ar_cache  ),
+            .ARPROT_i  ( spi.ar_prot   ),
+            .ARREGION_i( spi.ar_region ),
+            .ARUSER_i  ( spi.ar_user   ),
+            .ARQOS_i   ( spi.ar_qos    ),
+            .ARVALID_i ( spi.ar_valid  ),
+            .ARREADY_o ( spi.ar_ready  ),
+            .RID_o     ( spi.r_id      ),
+            .RDATA_o   ( spi.r_data    ),
+            .RRESP_o   ( spi.r_resp    ),
+            .RLAST_o   ( spi.r_last    ),
+            // .RUSER_o   ( spi.r_user    ),
+            .RVALID_o  ( spi.r_valid   ),
+            .RREADY_i  ( spi.r_ready   ),
+            .PENABLE   ( spi_penable   ),
+            .PWRITE    ( spi_pwrite    ),
+            .PADDR     ( spi_paddr     ),
+            .PSEL      ( spi_psel      ),
+            .PWDATA    ( spi_pwdata    ),
+            .PRDATA    ( spi_prdata    ),
+            .PREADY    ( spi_pready    ),
+            .PSLVERR   ( spi_pslverr   )
+        );
+
+        apb_spi_master #(
+            .BUFFER_DEPTH  (10),
+            .APB_ADDR_WIDTH(32)  //APB slaves are 4KB by default
+        ) SPI0(
+            .HCLK(clk_i),
+            .HRESETn(rst_ni),
+            .PADDR(spi_paddr),
+            .PWDATA(spi_pwdata),
+            .PWRITE(spi_pwrite),
+            .PSEL(spi_psel),
+            .PENABLE(spi_penable),
+            .PRDATA(spi_prdata),
+            .PREADY(spi_pready),
+            .PSLVERR(spi_pslverr),
+            .events_o(irq_sources[1]),
+            .spi_mode(  ),
+            .spi_clk(spi_clk_o),
+            .spi_csn0(spi_ss),
+            .spi_sdo0(spi_mosi),
+            .spi_sdi0(  ),
+            .spi_csn1(  ),
+            .spi_sdo1(  ),
+            .spi_sdi1(spi_miso),
+            .spi_csn2(  ),
+            .spi_sdo2(  ),
+            .spi_sdi2(  ),
+            .spi_csn3(  ),
+            .spi_sdo3(  ),
+            .spi_sdi3(  )
+        );
+
+    end else begin
+        assign spi_clk_o = 1'b0;
+        assign spi_mosi = 1'b0;
+        assign spi_ss = 1'b0;
+
+        // assign irq_sources [1] = 1'b0;
+        assign spi.aw_ready = 1'b1;
+        assign spi.ar_ready = 1'b1;
+        assign spi.w_ready = 1'b1;
+
+        assign spi.b_valid = spi.aw_valid;
+        assign spi.b_id = spi.aw_id;
+        assign spi.b_resp = axi_pkg::RESP_SLVERR;
+        assign spi.b_user = '0;
+
+        assign spi.r_valid = spi.ar_valid;
+        assign spi.r_resp = axi_pkg::RESP_SLVERR;
+        assign spi.r_data = 'hdeadbeef;
+        assign spi.r_last = 1'b1;
+    end
+
+
+    // ---------------
+    // 4. Ethernet
+    // ---------------
+
+    if (InclEthernet) begin : gen_ethernet
+
+    logic                    clk_200_int, clk_rgmii, clk_rgmii_quad;
+    logic                    eth_en, eth_we, eth_int_n, eth_pme_n, eth_mdio_i, eth_mdio_o, eth_mdio_oe;
+    logic [AxiAddrWidth-1:0] eth_addr;
+    logic [AxiDataWidth-1:0] eth_wrdata, eth_rdata;
+    logic [AxiDataWidth/8-1:0] eth_be;
+
+    axi2mem #(
+        .AXI_ID_WIDTH   ( AxiIdWidth       ),
+        .AXI_ADDR_WIDTH ( AxiAddrWidth     ),
+        .AXI_DATA_WIDTH ( AxiDataWidth     ),
+        .AXI_USER_WIDTH ( AxiUserWidth     )
+    ) i_axi2rom (
+        .clk_i  ( clk_i                   ),
+        .rst_ni ( rst_ni                  ),
+        .slave  ( ethernet                ),
+        .req_o  ( eth_en                  ),
+        .we_o   ( eth_we                  ),
+        .addr_o ( eth_addr                ),
+        .be_o   ( eth_be                  ),
+        .data_o ( eth_wrdata              ),
+        .data_i ( eth_rdata               )
+    );
+
+    framing_top  #(
+        .TARGET("ALTERA")
+    ) eth_rgmii (
+       .msoc_clk(clk_i),
+       .core_lsu_addr(eth_addr[14:0]),
+       .core_lsu_wdata(eth_wrdata),
+       .core_lsu_be(eth_be),
+       .ce_d(eth_en),
+       .we_d(eth_en & eth_we),
+       .framing_sel(eth_en),
+       .framing_rdata(eth_rdata),
+       .rst_int(!rst_ni),
+       .clk_int(phy_tx_clk_i), // 125 MHz in-phase
+       .clk90_int(eth_clk_i),    // 125 MHz quadrature
+       .clk_200_int(clk_200MHz_i),
+       /*
+        * Ethernet: 1000BASE-T RGMII
+        */
+       .phy_rx_clk(eth_rxck),
+       .phy_rxd(eth_rxd),
+       .phy_rx_ctl(eth_rxctl),
+       .phy_tx_clk(eth_txck),
+       .phy_txd(eth_txd),
+       .phy_tx_ctl(eth_txctl),
+       .phy_reset_n(eth_rst_n),
+       .phy_int_n(eth_int_n),
+       .phy_pme_n(eth_pme_n),
+       .phy_mdc(eth_mdc),
+       .phy_mdio_i(eth_mdio_i),
+       .phy_mdio_o(eth_mdio_o),
+       .phy_mdio_oe(eth_mdio_oe),
+       .eth_irq(irq_sources[2])
+    );
+
+    iobuf iobuf_inst (
+		.dout   (eth_mdio_i),   //  output,  width = 1,   dout.export
+		.din    (eth_mdio_o),    //   input,  width = 1,    din.export
+		.oe     (~eth_mdio_oe),     //   input,  width = 1,     oe.export
+		.pad_io (eth_mdio)  //   inout,  width = 1, pad_io.export
+	);
+
+    end else begin
+        assign irq_sources [2] = 1'b0;
+        assign ethernet.aw_ready = 1'b1;
+        assign ethernet.ar_ready = 1'b1;
+        assign ethernet.w_ready = 1'b1;
+
+        assign ethernet.b_valid = ethernet.aw_valid;
+        assign ethernet.b_id = ethernet.aw_id;
+        assign ethernet.b_resp = axi_pkg::RESP_SLVERR;
+        assign ethernet.b_user = '0;
+
+        assign ethernet.r_valid = ethernet.ar_valid;
+        assign ethernet.r_resp = axi_pkg::RESP_SLVERR;
+        assign ethernet.r_data = 'hdeadbeef;
+        assign ethernet.r_last = 1'b1;
+    end
+
+    // 5. GPIO
+    assign gpio.b_user = 1'b0;
+    assign gpio.r_user = 1'b0;
+
+    if (InclGPIO) begin : gen_gpio
+
+        logic         gpio_penable;
+        logic         gpio_pwrite;
+        logic [31:0]  gpio_paddr;
+        logic         gpio_psel;
+        logic [31:0]  gpio_pwdata;
+        logic [31:0]  gpio_prdata;
+        logic         gpio_pready;
+        logic         gpio_pslverr;
+
+        axi2apb_64_32 #(
+            .AXI4_ADDRESS_WIDTH ( AxiAddrWidth ),
+            .AXI4_RDATA_WIDTH   ( AxiDataWidth ),
+            .AXI4_WDATA_WIDTH   ( AxiDataWidth ),
+            .AXI4_ID_WIDTH      ( AxiIdWidth   ),
+            .AXI4_USER_WIDTH    ( AxiUserWidth ),
+            .BUFF_DEPTH_SLAVE   ( 2            ),
+            .APB_ADDR_WIDTH     ( 32           )
+        ) i_axi2apb_64_32_gpio (
+            .ACLK      ( clk_i          ),
+            .ARESETn   ( rst_ni         ),
+            .test_en_i ( 1'b0           ),
+            .AWID_i    ( gpio.aw_id     ),
+            .AWADDR_i  ( gpio.aw_addr   ),
+            .AWLEN_i   ( gpio.aw_len    ),
+            .AWSIZE_i  ( gpio.aw_size   ),
+            .AWBURST_i ( gpio.aw_burst  ),
+            .AWLOCK_i  ( gpio.aw_lock   ),
+            .AWCACHE_i ( gpio.aw_cache  ),
+            .AWPROT_i  ( gpio.aw_prot   ),
+            .AWREGION_i( gpio.aw_region ),
+            .AWUSER_i  ( gpio.aw_user   ),
+            .AWQOS_i   ( gpio.aw_qos    ),
+            .AWVALID_i ( gpio.aw_valid  ),
+            .AWREADY_o ( gpio.aw_ready  ),
+            .WDATA_i   ( gpio.w_data    ),
+            .WSTRB_i   ( gpio.w_strb    ),
+            .WLAST_i   ( gpio.w_last    ),
+            .WUSER_i   ( gpio.w_user    ),
+            .WVALID_i  ( gpio.w_valid   ),
+            .WREADY_o  ( gpio.w_ready   ),
+            .BID_o     ( gpio.b_id      ),
+            .BRESP_o   ( gpio.b_resp    ),
+            .BVALID_o  ( gpio.b_valid   ),
+            // .BUSER_o   ( gpio.b_user    ),
+            .BREADY_i  ( gpio.b_ready   ),
+            .ARID_i    ( gpio.ar_id     ),
+            .ARADDR_i  ( gpio.ar_addr   ),
+            .ARLEN_i   ( gpio.ar_len    ),
+            .ARSIZE_i  ( gpio.ar_size   ),
+            .ARBURST_i ( gpio.ar_burst  ),
+            .ARLOCK_i  ( gpio.ar_lock   ),
+            .ARCACHE_i ( gpio.ar_cache  ),
+            .ARPROT_i  ( gpio.ar_prot   ),
+            .ARREGION_i( gpio.ar_region ),
+            .ARUSER_i  ( gpio.ar_user   ),
+            .ARQOS_i   ( gpio.ar_qos    ),
+            .ARVALID_i ( gpio.ar_valid  ),
+            .ARREADY_o ( gpio.ar_ready  ),
+            .RID_o     ( gpio.r_id      ),
+            .RDATA_o   ( gpio.r_data    ),
+            .RRESP_o   ( gpio.r_resp    ),
+            .RLAST_o   ( gpio.r_last    ),
+            // .RUSER_o   ( gpio.r_user    ),
+            .RVALID_o  ( gpio.r_valid   ),
+            .RREADY_i  ( gpio.r_ready   ),
+            .PENABLE   ( gpio_penable   ),
+            .PWRITE    ( gpio_pwrite    ),
+            .PADDR     ( gpio_paddr     ),
+            .PSEL      ( gpio_psel      ),
+            .PWDATA    ( gpio_pwdata    ),
+            .PRDATA    ( gpio_prdata    ),
+            .PREADY    ( gpio_pready    ),
+            .PSLVERR   ( gpio_pslverr   )
+        );
+
+        APB #(.ADDR_WIDTH ( 32 ),
+            .DATA_WIDTH ( 32 )
+        ) apb_gpio();
+        assign apb_gpio.paddr   = gpio_paddr;
+        assign apb_gpio.pprot   = 3'b0;
+        assign apb_gpio.psel    = gpio_psel;
+        assign apb_gpio.penable = gpio_penable;
+        assign apb_gpio.pwrite  = gpio_pwrite;
+        assign apb_gpio.pwdata  = gpio_pwdata;
+        assign apb_gpio.pstrb   = {4{gpio_pwrite}};
+        assign gpio_prdata      = apb_gpio.prdata;
+        assign gpio_pready      = apb_gpio.pready;
+        assign gpio_pslverr     = apb_gpio.pslverr;
+
+        gpio_apb_wrap_intf # (
+            .ADDR_WIDTH(32),
+            // DATA_WIDTH of the APB interface
+            .DATA_WIDTH(32)
+        ) i_gpio(
+            .clk_i(clk_i),
+            .rst_ni(rst_ni),
+            .gpio_in('0),
+            .gpio_out(leds_o),
+            .gpio_tx_en_o(), // 0 -> input, 1 -> output
+            .gpio_in_sync_o(), // sampled and synchronized GPIO
+            // input.
+            .global_interrupt_o(),
+            .pin_level_interrupts_o(),
+            .apb_slave (apb_gpio)
+        );
+        
+    end
+
+    // 6. Timer
+    if (InclTimer) begin : gen_timer
+        logic         timer_penable;
+        logic         timer_pwrite;
+        logic [31:0]  timer_paddr;
+        logic         timer_psel;
+        logic [31:0]  timer_pwdata;
+        logic [31:0]  timer_prdata;
+        logic         timer_pready;
+        logic         timer_pslverr;
+
+        axi2apb_64_32 #(
+            .AXI4_ADDRESS_WIDTH ( AxiAddrWidth ),
+            .AXI4_RDATA_WIDTH   ( AxiDataWidth ),
+            .AXI4_WDATA_WIDTH   ( AxiDataWidth ),
+            .AXI4_ID_WIDTH      ( AxiIdWidth   ),
+            .AXI4_USER_WIDTH    ( AxiUserWidth ),
+            .BUFF_DEPTH_SLAVE   ( 2            ),
+            .APB_ADDR_WIDTH     ( 32           )
+        ) i_axi2apb_64_32_timer (
+            .ACLK      ( clk_i           ),
+            .ARESETn   ( rst_ni          ),
+            .test_en_i ( 1'b0            ),
+            .AWID_i    ( timer.aw_id     ),
+            .AWADDR_i  ( timer.aw_addr   ),
+            .AWLEN_i   ( timer.aw_len    ),
+            .AWSIZE_i  ( timer.aw_size   ),
+            .AWBURST_i ( timer.aw_burst  ),
+            .AWLOCK_i  ( timer.aw_lock   ),
+            .AWCACHE_i ( timer.aw_cache  ),
+            .AWPROT_i  ( timer.aw_prot   ),
+            .AWREGION_i( timer.aw_region ),
+            .AWUSER_i  ( timer.aw_user   ),
+            .AWQOS_i   ( timer.aw_qos    ),
+            .AWVALID_i ( timer.aw_valid  ),
+            .AWREADY_o ( timer.aw_ready  ),
+            .WDATA_i   ( timer.w_data    ),
+            .WSTRB_i   ( timer.w_strb    ),
+            .WLAST_i   ( timer.w_last    ),
+            .WUSER_i   ( timer.w_user    ),
+            .WVALID_i  ( timer.w_valid   ),
+            .WREADY_o  ( timer.w_ready   ),
+            .BID_o     ( timer.b_id      ),
+            .BRESP_o   ( timer.b_resp    ),
+            .BVALID_o  ( timer.b_valid   ),
+            .BUSER_o   ( timer.b_user    ),
+            .BREADY_i  ( timer.b_ready   ),
+            .ARID_i    ( timer.ar_id     ),
+            .ARADDR_i  ( timer.ar_addr   ),
+            .ARLEN_i   ( timer.ar_len    ),
+            .ARSIZE_i  ( timer.ar_size   ),
+            .ARBURST_i ( timer.ar_burst  ),
+            .ARLOCK_i  ( timer.ar_lock   ),
+            .ARCACHE_i ( timer.ar_cache  ),
+            .ARPROT_i  ( timer.ar_prot   ),
+            .ARREGION_i( timer.ar_region ),
+            .ARUSER_i  ( timer.ar_user   ),
+            .ARQOS_i   ( timer.ar_qos    ),
+            .ARVALID_i ( timer.ar_valid  ),
+            .ARREADY_o ( timer.ar_ready  ),
+            .RID_o     ( timer.r_id      ),
+            .RDATA_o   ( timer.r_data    ),
+            .RRESP_o   ( timer.r_resp    ),
+            .RLAST_o   ( timer.r_last    ),
+            .RUSER_o   ( timer.r_user    ),
+            .RVALID_o  ( timer.r_valid   ),
+            .RREADY_i  ( timer.r_ready   ),
+            .PENABLE   ( timer_penable   ),
+            .PWRITE    ( timer_pwrite    ),
+            .PADDR     ( timer_paddr     ),
+            .PSEL      ( timer_psel      ),
+            .PWDATA    ( timer_pwdata    ),
+            .PRDATA    ( timer_prdata    ),
+            .PREADY    ( timer_pready    ),
+            .PSLVERR   ( timer_pslverr   )
+        );
+
+        apb_timer #(
+                .APB_ADDR_WIDTH ( 32 ),
+                .TIMER_CNT      ( 2  )
+        ) i_timer (
+            .HCLK    ( clk_i            ),
+            .HRESETn ( rst_ni           ),
+            .PSEL    ( timer_psel       ),
+            .PENABLE ( timer_penable    ),
+            .PWRITE  ( timer_pwrite     ),
+            .PADDR   ( timer_paddr      ),
+            .PWDATA  ( timer_pwdata     ),
+            .PRDATA  ( timer_prdata     ),
+            .PREADY  ( timer_pready     ),
+            .PSLVERR ( timer_pslverr    ),
+            .irq_o   ( irq_sources[6:3] )
+        );
+    end
+endmodule

corev_apu/altera/src/dmi_vjtag.sv

@@ -0,0 +1,281 @@
+/* Copyright 2018 ETH Zurich and University of Bologna.
+* Copyright 2024 Thales AVS
+* Copyright and related rights are licensed under the Solderpad Hardware
+* License, Version 0.51 (the “License”); you may not use this file except in
+* compliance with the License.  You may obtain a copy of the License at
+* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+* or agreed to in writing, software, hardware and materials distributed under
+* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
+* CONDITIONS OF ANY KIND, either express or implied. See the License for the
+* specific language governing permissions and limitations under the License.
+*
+* File:   axi_riscv_debug_module.sv
+* Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
+* Date:   19.7.2018
+* Additional contributions by Nicolas Levasseur, Thales AVS
+* Date:   8.11.2024
+* Description: Virtual JTAG DMI (debug module interface)
+*
+*/
+
+module dmi_vjtag #(
+  parameter int unsigned IrLength = 10,
+  parameter logic [31:0] IdcodeValue = 32'h00000001
+) (
+  input  logic         clk_i,      // DMI Clock
+  input  logic         rst_ni,     // Asynchronous reset active low
+  input  logic         testmode_i,
+
+  output logic         dmi_rst_no, // hard reset
+  output dm::dmi_req_t dmi_req_o,
+  output logic         dmi_req_valid_o,
+  input  logic         dmi_req_ready_i,
+
+  input dm::dmi_resp_t dmi_resp_i,
+  output logic         dmi_resp_ready_o,
+  input  logic         dmi_resp_valid_i,
+
+  input  logic         tck_i,    // JTAG test clock pad
+  input  logic         trst_ni,  // JTAG test reset pad
+  input  logic         td_i,     // JTAG test data input pad
+  output logic         td_o,     // JTAG test data output pad
+  output logic         tdo_oe_o,  // Data out output enable
+  input  logic[IrLength-1:0]  ir_in_i,            // Virtual IR in
+  input  logic                jtag_state_tlr_i,     // Test logic reset
+  input  logic                virtual_state_cdr_i,  // Virtual Captude DR
+  input  logic                virtual_state_sdr_i,  // Virtual Shift DR
+  input  logic                virtual_state_udr_i  // Virutal Update DR
+);
+  assign       dmi_rst_no = rst_ni;
+
+  logic        dmi_access;
+  logic        dtmcs_select;
+  logic        dmi_reset;
+  logic        dmi_tdi;
+  logic        dmi_tdo;
+
+  dm::dmi_req_t  dmi_req;
+  logic          dmi_req_ready;
+  logic          dmi_req_valid;
+
+  dm::dmi_resp_t dmi_resp;
+  logic          dmi_resp_valid;
+  logic          dmi_resp_ready;
+
+  typedef struct packed {
+    logic [6:0]  address;
+    logic [31:0] data;
+    logic [1:0]  op;
+  } dmi_t;
+
+  typedef enum logic [1:0] {
+    DMINoError = 2'h0, DMIReservedError = 2'h1,
+    DMIOPFailed = 2'h2, DMIBusy = 2'h3
+  } dmi_error_e;
+
+  typedef enum logic [2:0] { Idle, Read, WaitReadValid, Write, WaitWriteValid } state_e;
+  state_e state_d, state_q;
+
+  logic [$bits(dmi_t)-1:0] dr_d, dr_q;
+  logic [6:0] address_d, address_q;
+  logic [31:0] data_d, data_q;
+
+  dmi_t  dmi;
+  assign dmi          = dmi_t'(dr_q);
+  assign dmi_req.addr = address_q;
+  assign dmi_req.data = data_q;
+  assign dmi_req.op   = (state_q == Write) ? dm::DTM_WRITE : dm::DTM_READ;
+  // we'will always be ready to accept the data we requested
+  assign dmi_resp_ready = 1'b1;
+
+  logic error_dmi_busy;
+  dmi_error_e error_d, error_q;
+
+  always_comb begin : p_fsm
+    error_dmi_busy = 1'b0;
+    // default assignments
+    state_d   = state_q;
+    address_d = address_q;
+    data_d    = data_q;
+    error_d   = error_q;
+
+    dmi_req_valid = 1'b0;
+
+    // STATE MACHINE
+    unique case (state_q)
+      Idle: begin
+        // make sure that no error is sticky
+        if (dmi_access && virtual_state_udr_i && (error_q == DMINoError)) begin
+          // save address and value
+          address_d = dmi.address;
+          data_d = dmi.data;
+          if (dm::dtm_op_e'(dmi.op) == dm::DTM_READ) begin
+            state_d = Read;
+          end else if (dm::dtm_op_e'(dmi.op) == dm::DTM_WRITE) begin
+            state_d = Write;
+          end
+          // else this is a nop and we can stay here
+        end
+      end
+
+      Read: begin
+        dmi_req_valid = 1'b1;
+        if (dmi_req_ready) begin
+          state_d = WaitReadValid;
+        end
+      end
+
+      WaitReadValid: begin
+        // load data into register and shift out
+        if (dmi_resp_valid) begin
+          data_d = dmi_resp.data;
+          state_d = Idle;
+        end
+      end
+
+      Write: begin
+        dmi_req_valid = 1'b1;
+        // request sent, wait for response before going back to idle
+        if (dmi_req_ready) begin
+          state_d = WaitWriteValid;
+        end
+      end
+
+      WaitWriteValid: begin
+        // got a valid answer go back to idle
+        if (dmi_resp_valid) begin
+          state_d = Idle;
+        end
+      end
+
+      default: begin
+        // just wait for idle here
+        if (dmi_resp_valid) begin
+          state_d = Idle;
+        end
+      end
+    endcase
+
+    // virtual_state_udr_i means we got another request but we didn't finish
+    // the one in progress, this state is sticky
+    if (virtual_state_udr_i && state_q != Idle) begin
+      error_dmi_busy = 1'b1;
+    end
+
+    // if virtual_state_cdr_i goes high while we are in the read state
+    // or in the corresponding wait state we are not giving back a valid word
+    // -> throw an error
+    if (virtual_state_cdr_i && state_q inside {Read, WaitReadValid}) begin
+      error_dmi_busy = 1'b1;
+    end
+
+    if (error_dmi_busy) begin
+      error_d = DMIBusy;
+    end
+    // clear sticky error flag
+    if (virtual_state_udr_i && dmi_reset && dtmcs_select) begin
+      error_d = DMINoError;
+    end
+  end
+
+  // shift register
+  // ---
+  // CHANGED FROM DR_Q TO DR_D BECAUSE OF 
+  // DELAY DUE TO THE ARCHITECTURE OF VJTAG
+  // ---
+  assign dmi_tdo = dr_d[0];
+  // ---
+
+  // JTAG DR operations
+  always_comb begin : p_shift
+    dr_d    = dr_q;
+
+    if (virtual_state_cdr_i) begin
+      if (dmi_access) begin
+        if (error_q == DMINoError && !error_dmi_busy) begin
+          dr_d = {address_q, data_q, DMINoError};
+        // DMI was busy, report an error
+        end else if (error_q == DMIBusy || error_dmi_busy) begin
+          dr_d = {address_q, data_q, DMIBusy};
+        end
+      end
+    end
+
+    if (virtual_state_sdr_i) begin
+      if (dmi_access) begin
+        dr_d = {dmi_tdi, dr_q[$bits(dr_q)-1:1]};
+      end
+    end
+
+    if (jtag_state_tlr_i) begin
+      dr_d = '0;
+    end
+  end
+
+  always_ff @(posedge tck_i or negedge trst_ni) begin : p_regs
+    if (!trst_ni) begin
+      dr_q      <= '0;
+      state_q   <= Idle;
+      address_q <= '0;
+      data_q    <= '0;
+      error_q   <= DMINoError;
+    end else begin
+      dr_q      <= dr_d;
+      state_q   <= state_d;
+      address_q <= address_d;
+      data_q    <= data_d;
+      error_q   <= error_d;
+    end
+  end
+
+  // ---------
+  // TAP
+  // ---------
+  dmi_vjtag_tap #(
+    .IrLength (IrLength),
+    .IdcodeValue(IdcodeValue)
+  ) i_dmi_jtag_tap (
+    .tck_i,
+    .trst_ni,
+    .td_i,
+    .td_o,
+    .tdo_oe_o,
+    .testmode_i,
+    .ir_in_i,
+    .jtag_state_tlr_i,
+    .virtual_state_cdr_i,
+    .virtual_state_sdr_i,
+    .virtual_state_udr_i,
+    .dmi_access_o       ( dmi_access       ),
+    .dtmcs_select_o     ( dtmcs_select     ),
+    .dmi_reset_o        ( dmi_reset        ),
+    .dmi_error_i        ( error_q          ),
+    .dmi_tdi_o          ( dmi_tdi          ),
+    .dmi_tdo_i          ( dmi_tdo          )
+  );
+
+  // ---------
+  // CDC
+  // ---------
+  dmi_cdc i_dmi_cdc (
+    // JTAG side (master side)
+    .tck_i,
+    .trst_ni,
+    .jtag_dmi_req_i    ( dmi_req          ),
+    .jtag_dmi_ready_o  ( dmi_req_ready    ),
+    .jtag_dmi_valid_i  ( dmi_req_valid    ),
+    .jtag_dmi_resp_o   ( dmi_resp         ),
+    .jtag_dmi_valid_o  ( dmi_resp_valid   ),
+    .jtag_dmi_ready_i  ( dmi_resp_ready   ),
+    // core side
+    .clk_i,
+    .rst_ni,
+    .core_dmi_req_o    ( dmi_req_o        ),
+    .core_dmi_valid_o  ( dmi_req_valid_o  ),
+    .core_dmi_ready_i  ( dmi_req_ready_i  ),
+    .core_dmi_resp_i   ( dmi_resp_i       ),
+    .core_dmi_ready_o  ( dmi_resp_ready_o ),
+    .core_dmi_valid_i  ( dmi_resp_valid_i )
+  );
+
+endmodule : dmi_vjtag

corev_apu/altera/src/dmi_vjtag_tap.sv

@@ -0,0 +1,199 @@
+/* Copyright 2018 ETH Zurich and University of Bologna.
+ * Copyright 2024 Thales AVS
+ * Copyright and related rights are licensed under the Solderpad Hardware
+ * License, Version 0.51 (the “License”); you may not use this file except in
+ * compliance with the License.  You may obtain a copy of the License at
+ * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+ * or agreed to in writing, software, hardware and materials distributed under
+ * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
+ * CONDITIONS OF ANY KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations under the License.
+ *
+ * File:   dmi_jtag_tap.sv
+ * Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
+ * Date:   19.7.2018
+ * Additional contributions by Nicolas Levasseur, Thales AVS
+ * Date:   8.11.2024
+ * Description: vJTAG TAP for DMI to be able to use vJTAG IP
+ *
+ */
+
+module dmi_vjtag_tap #(
+  parameter int unsigned IrLength = 10,
+  // JTAG IDCODE Value
+  parameter logic [31:0] IdcodeValue = 32'h00000001
+  // xxxx             version
+  // xxxxxxxxxxxxxxxx part number
+  // xxxxxxxxxxx      manufacturer id
+  // 1                required by standard
+) (
+  input   logic                tck_i,              // JTAG test clock pad
+  input   logic                trst_ni,            // JTAG test reset pad
+  input   logic                td_i,               // JTAG test data input pad
+  output  logic                td_o,               // JTAG test data output pad
+  output  logic                tdo_oe_o,           // Data output enable
+  input   logic                testmode_i,
+  input   logic[IrLength-1:0]  ir_in_i,            // Virtual IR in
+  input   logic                jtag_state_tlr_i,     // Test logic reset
+  input   logic                virtual_state_cdr_i,  // Virtual Captude DR
+  input   logic                virtual_state_sdr_i,  // Virtual Shift DR
+  input   logic                virtual_state_udr_i,  // Virutal Update DR
+
+  // we want to access DMI register
+  output logic        dmi_access_o,
+  // JTAG is interested in writing the DTM CSR register
+  output logic        dtmcs_select_o,
+  // clear error state
+  output logic        dmi_reset_o,
+  input  logic [1:0]  dmi_error_i,
+  // test data to submodule
+  output logic        dmi_tdi_o,
+  // test data in from submodule
+  input  logic        dmi_tdo_i
+);
+
+  // to submodule
+  assign dmi_tdi_o = td_i;
+
+  typedef enum logic [IrLength-1:0] {
+    BYPASS0   = (IrLength)'('h0),
+    IDCODE    = (IrLength)'('h1),
+    DTMCSR    = (IrLength)'('h10),
+    DMIACCESS = (IrLength)'('h11),
+    BYPASS1   = (IrLength)'('h1f)
+  } ir_reg_e;
+
+  typedef struct packed {
+    logic [31:18] zero1;
+    logic         dmihardreset;
+    logic         dmireset;
+    logic         zero0;
+    logic [14:12] idle;
+    logic [11:10] dmistat;
+    logic [9:4]   abits;
+    logic [3:0]   version;
+  } dtmcs_t;
+
+  // ----------------
+  // TAP DR Regs
+  // ----------------
+  // - Bypass
+  // - IDCODE
+  // - DTM CS
+  logic [31:0] idcode_d, idcode_q;
+  logic        idcode_select;
+  logic        bypass_select;
+  dtmcs_t      dtmcs_d, dtmcs_q;
+  logic        bypass_d, bypass_q;  // this is a 1-bit register
+
+  assign dmi_reset_o = dtmcs_q.dmireset;
+
+  always_comb begin
+    idcode_d = idcode_q;
+    bypass_d = bypass_q;
+    dtmcs_d  = dtmcs_q;
+
+    if (virtual_state_cdr_i) begin
+      if (idcode_select) idcode_d = IdcodeValue;
+      if (bypass_select) bypass_d = 1'b0;
+      if (dtmcs_select_o) begin
+        dtmcs_d  = '{
+                      zero1        : '0,
+                      dmihardreset : 1'b0,
+                      dmireset     : 1'b0,
+                      zero0        : '0,
+                      idle         : 3'd1, // 1: Enter Run-Test/Idle and leave it immediately
+                      dmistat      : dmi_error_i, // 0: No error, 2: Op failed, 3: too fast
+                      abits        : 6'd7, // The size of address in dmi
+                      version      : 4'd1  // Version described in spec version 0.13 (and later?)
+                    };
+      end
+    end
+
+    if (virtual_state_sdr_i) begin
+      if (idcode_select)  idcode_d = {td_i, 31'(idcode_q >> 1)};
+      if (bypass_select)  bypass_d = td_i;
+      if (dtmcs_select_o) dtmcs_d  = {td_i, 31'(dtmcs_q >> 1)};
+    end
+
+    if (jtag_state_tlr_i) begin
+      idcode_d = IdcodeValue;
+      bypass_d = 1'b0;
+    end
+  end
+
+  // ----------------
+  // Data reg select
+  // ----------------
+  always_comb begin : p_data_reg_sel
+    dmi_access_o   = 1'b0;
+    dtmcs_select_o = 1'b0;
+    idcode_select  = 1'b0;
+    bypass_select  = 1'b0;
+
+    unique case (ir_in_i)
+      BYPASS0:   bypass_select  = 1'b1;
+      IDCODE:    idcode_select  = 1'b1;
+      DTMCSR:    dtmcs_select_o = 1'b1;
+      DMIACCESS: dmi_access_o   = 1'b1;
+      BYPASS1:   bypass_select  = 1'b1;
+      default:   bypass_select  = 1'b1;
+    endcase
+  end
+
+  // ----------------
+  // Output select
+  // ----------------
+  logic tdo_mux;
+
+  always_comb begin : p_out_sel
+    // here we are shifting the DR register
+    unique case (ir_in_i)
+      IDCODE:         tdo_mux = idcode_d[0];     // Reading ID code
+      DTMCSR:         tdo_mux = dtmcs_d.version[0];
+      DMIACCESS:      tdo_mux = dmi_tdo_i;       // Read from DMI TDO
+      default:        tdo_mux = bypass_d;      // BYPASS instruction
+    endcase
+  end
+
+  // ----------------
+  // DFT
+  // ----------------
+  logic tck_n, tck_ni;
+
+  cluster_clock_inverter i_tck_inv (
+    .clk_i ( tck_i  ),
+    .clk_o ( tck_ni )
+  );
+
+  pulp_clock_mux2 i_dft_tck_mux (
+    .clk0_i    ( tck_ni     ),
+    .clk1_i    ( tck_i      ), // bypass the inverted clock for testing
+    .clk_sel_i ( testmode_i ),
+    .clk_o     ( tck_n      )
+  );
+
+  // TDO changes state at negative edge of TCK
+  always_ff @(posedge tck_n, negedge trst_ni) begin : p_tdo_regs
+    if (!trst_ni) begin
+      td_o     <= 1'b0;
+      tdo_oe_o <= 1'b0;
+    end else begin
+      td_o     <= tdo_mux;
+      tdo_oe_o <= virtual_state_sdr_i;
+    end
+  end
+
+  always_ff @(posedge tck_i or negedge trst_ni) begin : p_regs
+    if (!trst_ni) begin
+      idcode_q    <= IdcodeValue;
+      bypass_q    <= 1'b0;
+      dtmcs_q     <= '0;
+    end else begin
+      idcode_q    <= idcode_d;
+      bypass_q    <= bypass_d;
+      dtmcs_q     <= dtmcs_d;
+    end
+  end
+
+endmodule : dmi_vjtag_tap

corev_apu/fpga/src/apb

@@ -0,0 +1 @@
+Subproject commit 77ddf073f194d44b9119949d2421be59789e69ae

corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter.v

@@ -0,0 +1,324 @@
+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 width adapter
+ */
+module axi_dw_adapter #
+(
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of input (slave) interface data bus in bits
+    parameter S_DATA_WIDTH = 32,
+    // Width of input (slave) interface wstrb (width of data bus in words)
+    parameter S_STRB_WIDTH = (S_DATA_WIDTH/8),
+    // Width of output (master) interface data bus in bits
+    parameter M_DATA_WIDTH = 32,
+    // Width of output (master) interface wstrb (width of data bus in words)
+    parameter M_STRB_WIDTH = (M_DATA_WIDTH/8),
+    // Width of ID signal
+    parameter ID_WIDTH = 8,
+    // Propagate awuser signal
+    parameter AWUSER_ENABLE = 0,
+    // Width of awuser signal
+    parameter AWUSER_WIDTH = 1,
+    // Propagate wuser signal
+    parameter WUSER_ENABLE = 0,
+    // Width of wuser signal
+    parameter WUSER_WIDTH = 1,
+    // Propagate buser signal
+    parameter BUSER_ENABLE = 0,
+    // Width of buser signal
+    parameter BUSER_WIDTH = 1,
+    // Propagate aruser signal
+    parameter ARUSER_ENABLE = 0,
+    // Width of aruser signal
+    parameter ARUSER_WIDTH = 1,
+    // Propagate ruser signal
+    parameter RUSER_ENABLE = 0,
+    // Width of ruser signal
+    parameter RUSER_WIDTH = 1,
+    // When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible
+    parameter CONVERT_BURST = 1,
+    // When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible
+    parameter CONVERT_NARROW_BURST = 0,
+    // Forward ID through adapter
+    parameter FORWARD_ID = 0
+)
+(
+    input  wire                     clk,
+    input  wire                     rst,
+
+    /*
+     * AXI slave interface
+     */
+    input  wire [ID_WIDTH-1:0]      s_axi_awid,
+    input  wire [ADDR_WIDTH-1:0]    s_axi_awaddr,
+    input  wire [7:0]               s_axi_awlen,
+    input  wire [2:0]               s_axi_awsize,
+    input  wire [1:0]               s_axi_awburst,
+    input  wire                     s_axi_awlock,
+    input  wire [3:0]               s_axi_awcache,
+    input  wire [2:0]               s_axi_awprot,
+    input  wire [3:0]               s_axi_awqos,
+    input  wire [3:0]               s_axi_awregion,
+    input  wire [AWUSER_WIDTH-1:0]  s_axi_awuser,
+    input  wire                     s_axi_awvalid,
+    output wire                     s_axi_awready,
+    input  wire [S_DATA_WIDTH-1:0]  s_axi_wdata,
+    input  wire [S_STRB_WIDTH-1:0]  s_axi_wstrb,
+    input  wire                     s_axi_wlast,
+    input  wire [WUSER_WIDTH-1:0]   s_axi_wuser,
+    input  wire                     s_axi_wvalid,
+    output wire                     s_axi_wready,
+    output wire [ID_WIDTH-1:0]      s_axi_bid,
+    output wire [1:0]               s_axi_bresp,
+    output wire [BUSER_WIDTH-1:0]   s_axi_buser,
+    output wire                     s_axi_bvalid,
+    input  wire                     s_axi_bready,
+    input  wire [ID_WIDTH-1:0]      s_axi_arid,
+    input  wire [ADDR_WIDTH-1:0]    s_axi_araddr,
+    input  wire [7:0]               s_axi_arlen,
+    input  wire [2:0]               s_axi_arsize,
+    input  wire [1:0]               s_axi_arburst,
+    input  wire                     s_axi_arlock,
+    input  wire [3:0]               s_axi_arcache,
+    input  wire [2:0]               s_axi_arprot,
+    input  wire [3:0]               s_axi_arqos,
+    input  wire [3:0]               s_axi_arregion,
+    input  wire [ARUSER_WIDTH-1:0]  s_axi_aruser,
+    input  wire                     s_axi_arvalid,
+    output wire                     s_axi_arready,
+    output wire [ID_WIDTH-1:0]      s_axi_rid,
+    output wire [S_DATA_WIDTH-1:0]  s_axi_rdata,
+    output wire [1:0]               s_axi_rresp,
+    output wire                     s_axi_rlast,
+    output wire [RUSER_WIDTH-1:0]   s_axi_ruser,
+    output wire                     s_axi_rvalid,
+    input  wire                     s_axi_rready,
+
+    /*
+     * AXI master interface
+     */
+    output wire [ID_WIDTH-1:0]      m_axi_awid,
+    output wire [ADDR_WIDTH-1:0]    m_axi_awaddr,
+    output wire [7:0]               m_axi_awlen,
+    output wire [2:0]               m_axi_awsize,
+    output wire [1:0]               m_axi_awburst,
+    output wire                     m_axi_awlock,
+    output wire [3:0]               m_axi_awcache,
+    output wire [2:0]               m_axi_awprot,
+    output wire [3:0]               m_axi_awqos,
+    output wire [3:0]               m_axi_awregion,
+    output wire [AWUSER_WIDTH-1:0]  m_axi_awuser,
+    output wire                     m_axi_awvalid,
+    input  wire                     m_axi_awready,
+    output wire [M_DATA_WIDTH-1:0]  m_axi_wdata,
+    output wire [M_STRB_WIDTH-1:0]  m_axi_wstrb,
+    output wire                     m_axi_wlast,
+    output wire [WUSER_WIDTH-1:0]   m_axi_wuser,
+    output wire                     m_axi_wvalid,
+    input  wire                     m_axi_wready,
+    input  wire [ID_WIDTH-1:0]      m_axi_bid,
+    input  wire [1:0]               m_axi_bresp,
+    input  wire [BUSER_WIDTH-1:0]   m_axi_buser,
+    input  wire                     m_axi_bvalid,
+    output wire                     m_axi_bready,
+    output wire [ID_WIDTH-1:0]      m_axi_arid,
+    output wire [ADDR_WIDTH-1:0]    m_axi_araddr,
+    output wire [7:0]               m_axi_arlen,
+    output wire [2:0]               m_axi_arsize,
+    output wire [1:0]               m_axi_arburst,
+    output wire                     m_axi_arlock,
+    output wire [3:0]               m_axi_arcache,
+    output wire [2:0]               m_axi_arprot,
+    output wire [3:0]               m_axi_arqos,
+    output wire [3:0]               m_axi_arregion,
+    output wire [ARUSER_WIDTH-1:0]  m_axi_aruser,
+    output wire                     m_axi_arvalid,
+    input  wire                     m_axi_arready,
+    input  wire [ID_WIDTH-1:0]      m_axi_rid,
+    input  wire [M_DATA_WIDTH-1:0]  m_axi_rdata,
+    input  wire [1:0]               m_axi_rresp,
+    input  wire                     m_axi_rlast,
+    input  wire [RUSER_WIDTH-1:0]   m_axi_ruser,
+    input  wire                     m_axi_rvalid,
+    output wire                     m_axi_rready
+);
+
+axi_dw_adapter_wr #(
+    .ADDR_WIDTH(ADDR_WIDTH),
+    .S_DATA_WIDTH(S_DATA_WIDTH),
+    .S_STRB_WIDTH(S_STRB_WIDTH),
+    .M_DATA_WIDTH(M_DATA_WIDTH),
+    .M_STRB_WIDTH(M_STRB_WIDTH),
+    .ID_WIDTH(ID_WIDTH),
+    .AWUSER_ENABLE(AWUSER_ENABLE),
+    .AWUSER_WIDTH(AWUSER_WIDTH),
+    .WUSER_ENABLE(WUSER_ENABLE),
+    .WUSER_WIDTH(WUSER_WIDTH),
+    .BUSER_ENABLE(BUSER_ENABLE),
+    .BUSER_WIDTH(BUSER_WIDTH),
+    .CONVERT_BURST(CONVERT_BURST),
+    .CONVERT_NARROW_BURST(CONVERT_NARROW_BURST),
+    .FORWARD_ID(FORWARD_ID)
+)
+axi_adapter_wr_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI slave interface
+     */
+    .s_axi_awid(s_axi_awid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awregion(s_axi_awregion),
+    .s_axi_awuser(s_axi_awuser),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wuser(s_axi_wuser),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(s_axi_bid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(s_axi_buser),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+
+    /*
+     * AXI master interface
+     */
+    .m_axi_awid(m_axi_awid),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awlock(m_axi_awlock),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awqos(m_axi_awqos),
+    .m_axi_awregion(m_axi_awregion),
+    .m_axi_awuser(m_axi_awuser),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+    .m_axi_wuser(m_axi_wuser),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(m_axi_bid),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(m_axi_buser),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready)
+);
+
+axi_dw_adapter_rd #(
+    .ADDR_WIDTH(ADDR_WIDTH),
+    .S_DATA_WIDTH(S_DATA_WIDTH),
+    .S_STRB_WIDTH(S_STRB_WIDTH),
+    .M_DATA_WIDTH(M_DATA_WIDTH),
+    .M_STRB_WIDTH(M_STRB_WIDTH),
+    .ID_WIDTH(ID_WIDTH),
+    .ARUSER_ENABLE(ARUSER_ENABLE),
+    .ARUSER_WIDTH(ARUSER_WIDTH),
+    .RUSER_ENABLE(RUSER_ENABLE),
+    .RUSER_WIDTH(RUSER_WIDTH),
+    .CONVERT_BURST(CONVERT_BURST),
+    .CONVERT_NARROW_BURST(CONVERT_NARROW_BURST),
+    .FORWARD_ID(FORWARD_ID)
+)
+axi_adapter_rd_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI slave interface
+     */
+    .s_axi_arid(s_axi_arid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_arregion(s_axi_arregion),
+    .s_axi_aruser(s_axi_aruser),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(s_axi_rid),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_ruser(s_axi_ruser),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+
+    /*
+     * AXI master interface
+     */
+    .m_axi_arid(m_axi_arid),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arlock(m_axi_arlock),
+    .m_axi_arcache(m_axi_arcache),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arqos(m_axi_arqos),
+    .m_axi_arregion(m_axi_arregion),
+    .m_axi_aruser(m_axi_aruser),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(m_axi_rid),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_ruser(m_axi_ruser),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+);
+
+endmodule
+
+`resetall

corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter_rd.v

@@ -0,0 +1,686 @@
+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 width adapter
+ */
+module axi_dw_adapter_rd #
+(
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of input (slave) interface data bus in bits
+    parameter S_DATA_WIDTH = 32,
+    // Width of input (slave) interface wstrb (width of data bus in words)
+    parameter S_STRB_WIDTH = (S_DATA_WIDTH/8),
+    // Width of output (master) interface data bus in bits
+    parameter M_DATA_WIDTH = 32,
+    // Width of output (master) interface wstrb (width of data bus in words)
+    parameter M_STRB_WIDTH = (M_DATA_WIDTH/8),
+    // Width of ID signal
+    parameter ID_WIDTH = 8,
+    // Propagate aruser signal
+    parameter ARUSER_ENABLE = 0,
+    // Width of aruser signal
+    parameter ARUSER_WIDTH = 1,
+    // Propagate ruser signal
+    parameter RUSER_ENABLE = 0,
+    // Width of ruser signal
+    parameter RUSER_WIDTH = 1,
+    // When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible
+    parameter CONVERT_BURST = 1,
+    // When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible
+    parameter CONVERT_NARROW_BURST = 0,
+    // Forward ID through adapter
+    parameter FORWARD_ID = 0
+)
+(
+    input  wire                     clk,
+    input  wire                     rst,
+
+    /*
+     * AXI slave interface
+     */
+    input  wire [ID_WIDTH-1:0]      s_axi_arid,
+    input  wire [ADDR_WIDTH-1:0]    s_axi_araddr,
+    input  wire [7:0]               s_axi_arlen,
+    input  wire [2:0]               s_axi_arsize,
+    input  wire [1:0]               s_axi_arburst,
+    input  wire                     s_axi_arlock,
+    input  wire [3:0]               s_axi_arcache,
+    input  wire [2:0]               s_axi_arprot,
+    input  wire [3:0]               s_axi_arqos,
+    input  wire [3:0]               s_axi_arregion,
+    input  wire [ARUSER_WIDTH-1:0]  s_axi_aruser,
+    input  wire                     s_axi_arvalid,
+    output wire                     s_axi_arready,
+    output wire [ID_WIDTH-1:0]      s_axi_rid,
+    output wire [S_DATA_WIDTH-1:0]  s_axi_rdata,
+    output wire [1:0]               s_axi_rresp,
+    output wire                     s_axi_rlast,
+    output wire [RUSER_WIDTH-1:0]   s_axi_ruser,
+    output wire                     s_axi_rvalid,
+    input  wire                     s_axi_rready,
+
+    /*
+     * AXI master interface
+     */
+    output wire [ID_WIDTH-1:0]      m_axi_arid,
+    output wire [ADDR_WIDTH-1:0]    m_axi_araddr,
+    output wire [7:0]               m_axi_arlen,
+    output wire [2:0]               m_axi_arsize,
+    output wire [1:0]               m_axi_arburst,
+    output wire                     m_axi_arlock,
+    output wire [3:0]               m_axi_arcache,
+    output wire [2:0]               m_axi_arprot,
+    output wire [3:0]               m_axi_arqos,
+    output wire [3:0]               m_axi_arregion,
+    output wire [ARUSER_WIDTH-1:0]  m_axi_aruser,
+    output wire                     m_axi_arvalid,
+    input  wire                     m_axi_arready,
+    input  wire [ID_WIDTH-1:0]      m_axi_rid,
+    input  wire [M_DATA_WIDTH-1:0]  m_axi_rdata,
+    input  wire [1:0]               m_axi_rresp,
+    input  wire                     m_axi_rlast,
+    input  wire [RUSER_WIDTH-1:0]   m_axi_ruser,
+    input  wire                     m_axi_rvalid,
+    output wire                     m_axi_rready
+);
+
+parameter S_ADDR_BIT_OFFSET = $clog2(S_STRB_WIDTH);
+parameter M_ADDR_BIT_OFFSET = $clog2(M_STRB_WIDTH);
+parameter S_WORD_WIDTH = S_STRB_WIDTH;
+parameter M_WORD_WIDTH = M_STRB_WIDTH;
+parameter S_WORD_SIZE = S_DATA_WIDTH/S_WORD_WIDTH;
+parameter M_WORD_SIZE = M_DATA_WIDTH/M_WORD_WIDTH;
+parameter S_BURST_SIZE = $clog2(S_STRB_WIDTH);
+parameter M_BURST_SIZE = $clog2(M_STRB_WIDTH);
+
+// output bus is wider
+parameter EXPAND = M_STRB_WIDTH > S_STRB_WIDTH;
+parameter DATA_WIDTH = EXPAND ? M_DATA_WIDTH : S_DATA_WIDTH;
+parameter STRB_WIDTH = EXPAND ? M_STRB_WIDTH : S_STRB_WIDTH;
+// required number of segments in wider bus
+parameter SEGMENT_COUNT = EXPAND ? (M_STRB_WIDTH / S_STRB_WIDTH) : (S_STRB_WIDTH / M_STRB_WIDTH);
+// data width and keep width per segment
+parameter SEGMENT_DATA_WIDTH = DATA_WIDTH / SEGMENT_COUNT;
+parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT;
+
+// bus width assertions
+initial begin
+    if (S_WORD_SIZE * S_STRB_WIDTH != S_DATA_WIDTH) begin
+        $error("Error: AXI slave interface data width not evenly divisble (instance %m)");
+        $finish;
+    end
+
+    if (M_WORD_SIZE * M_STRB_WIDTH != M_DATA_WIDTH) begin
+        $error("Error: AXI master interface data width not evenly divisble (instance %m)");
+        $finish;
+    end
+
+    if (S_WORD_SIZE != M_WORD_SIZE) begin
+        $error("Error: word size mismatch (instance %m)");
+        $finish;
+    end
+
+    if (2**$clog2(S_WORD_WIDTH) != S_WORD_WIDTH) begin
+        $error("Error: AXI slave interface word width must be even power of two (instance %m)");
+        $finish;
+    end
+
+    if (2**$clog2(M_WORD_WIDTH) != M_WORD_WIDTH) begin
+        $error("Error: AXI master interface word width must be even power of two (instance %m)");
+        $finish;
+    end
+end
+
+localparam [1:0]
+    STATE_IDLE = 2'd0,
+    STATE_DATA = 2'd1,
+    STATE_DATA_READ = 2'd2,
+    STATE_DATA_SPLIT = 2'd3;
+
+reg [1:0] state_reg = STATE_IDLE, state_next;
+
+reg [ID_WIDTH-1:0] id_reg = {ID_WIDTH{1'b0}}, id_next;
+reg [ADDR_WIDTH-1:0] addr_reg = {ADDR_WIDTH{1'b0}}, addr_next;
+reg [DATA_WIDTH-1:0] data_reg = {DATA_WIDTH{1'b0}}, data_next;
+reg [1:0] resp_reg = 2'd0, resp_next;
+reg [RUSER_WIDTH-1:0] ruser_reg = {RUSER_WIDTH{1'b0}}, ruser_next;
+reg [7:0] burst_reg = 8'd0, burst_next;
+reg [2:0] burst_size_reg = 3'd0, burst_size_next;
+reg [7:0] master_burst_reg = 8'd0, master_burst_next;
+reg [2:0] master_burst_size_reg = 3'd0, master_burst_size_next;
+
+reg s_axi_arready_reg = 1'b0, s_axi_arready_next;
+
+reg [ID_WIDTH-1:0] m_axi_arid_reg = {ID_WIDTH{1'b0}}, m_axi_arid_next;
+reg [ADDR_WIDTH-1:0] m_axi_araddr_reg = {ADDR_WIDTH{1'b0}}, m_axi_araddr_next;
+reg [7:0] m_axi_arlen_reg = 8'd0, m_axi_arlen_next;
+reg [2:0] m_axi_arsize_reg = 3'd0, m_axi_arsize_next;
+reg [1:0] m_axi_arburst_reg = 2'd0, m_axi_arburst_next;
+reg m_axi_arlock_reg = 1'b0, m_axi_arlock_next;
+reg [3:0] m_axi_arcache_reg = 4'd0, m_axi_arcache_next;
+reg [2:0] m_axi_arprot_reg = 3'd0, m_axi_arprot_next;
+reg [3:0] m_axi_arqos_reg = 4'd0, m_axi_arqos_next;
+reg [3:0] m_axi_arregion_reg = 4'd0, m_axi_arregion_next;
+reg [ARUSER_WIDTH-1:0] m_axi_aruser_reg = {ARUSER_WIDTH{1'b0}}, m_axi_aruser_next;
+reg m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next;
+reg m_axi_rready_reg = 1'b0, m_axi_rready_next;
+
+// internal datapath
+reg  [ID_WIDTH-1:0]     s_axi_rid_int;
+reg  [S_DATA_WIDTH-1:0] s_axi_rdata_int;
+reg  [1:0]              s_axi_rresp_int;
+reg                     s_axi_rlast_int;
+reg  [RUSER_WIDTH-1:0]  s_axi_ruser_int;
+reg                     s_axi_rvalid_int;
+reg                     s_axi_rready_int_reg = 1'b0;
+wire                    s_axi_rready_int_early;
+
+assign s_axi_arready = s_axi_arready_reg;
+
+assign m_axi_arid = FORWARD_ID ? m_axi_arid_reg : {ID_WIDTH{1'b0}};
+assign m_axi_araddr = m_axi_araddr_reg;
+assign m_axi_arlen = m_axi_arlen_reg;
+assign m_axi_arsize = m_axi_arsize_reg;
+assign m_axi_arburst = m_axi_arburst_reg;
+assign m_axi_arlock = m_axi_arlock_reg;
+assign m_axi_arcache = m_axi_arcache_reg;
+assign m_axi_arprot = m_axi_arprot_reg;
+assign m_axi_arqos = m_axi_arqos_reg;
+assign m_axi_arregion = m_axi_arregion_reg;
+assign m_axi_aruser = ARUSER_ENABLE ? m_axi_aruser_reg : {ARUSER_WIDTH{1'b0}};
+assign m_axi_arvalid = m_axi_arvalid_reg;
+assign m_axi_rready = m_axi_rready_reg;
+
+always @* begin
+    state_next = STATE_IDLE;
+
+    id_next = id_reg;
+    addr_next = addr_reg;
+    data_next = data_reg;
+    resp_next = resp_reg;
+    ruser_next = ruser_reg;
+    burst_next = burst_reg;
+    burst_size_next = burst_size_reg;
+    master_burst_next = master_burst_reg;
+    master_burst_size_next = master_burst_size_reg;
+
+    s_axi_arready_next = 1'b0;
+    m_axi_arid_next = m_axi_arid_reg;
+    m_axi_araddr_next = m_axi_araddr_reg;
+    m_axi_arlen_next = m_axi_arlen_reg;
+    m_axi_arsize_next = m_axi_arsize_reg;
+    m_axi_arburst_next = m_axi_arburst_reg;
+    m_axi_arlock_next = m_axi_arlock_reg;
+    m_axi_arcache_next = m_axi_arcache_reg;
+    m_axi_arprot_next = m_axi_arprot_reg;
+    m_axi_arqos_next = m_axi_arqos_reg;
+    m_axi_arregion_next = m_axi_arregion_reg;
+    m_axi_aruser_next = m_axi_aruser_reg;
+    m_axi_arvalid_next = m_axi_arvalid_reg && !m_axi_arready;
+    m_axi_rready_next = 1'b0;
+
+    if (SEGMENT_COUNT == 1) begin
+        // master output is same width; direct transfer with no splitting/merging
+        s_axi_rid_int = id_reg;
+        s_axi_rdata_int = m_axi_rdata;
+        s_axi_rresp_int = m_axi_rresp;
+        s_axi_rlast_int = m_axi_rlast;
+        s_axi_ruser_int = m_axi_ruser;
+        s_axi_rvalid_int = 0;
+
+        case (state_reg)
+            STATE_IDLE: begin
+                // idle state; wait for new burst
+                s_axi_arready_next = !m_axi_arvalid;
+
+                if (s_axi_arready && s_axi_arvalid) begin
+                    s_axi_arready_next = 1'b0;
+                    id_next = s_axi_arid;
+                    m_axi_arid_next = s_axi_arid;
+                    m_axi_araddr_next = s_axi_araddr;
+                    m_axi_arlen_next = s_axi_arlen;
+                    m_axi_arsize_next = s_axi_arsize;
+                    m_axi_arburst_next = s_axi_arburst;
+                    m_axi_arlock_next = s_axi_arlock;
+                    m_axi_arcache_next = s_axi_arcache;
+                    m_axi_arprot_next = s_axi_arprot;
+                    m_axi_arqos_next = s_axi_arqos;
+                    m_axi_arregion_next = s_axi_arregion;
+                    m_axi_aruser_next = s_axi_aruser;
+                    m_axi_arvalid_next = 1'b1;
+                    m_axi_rready_next = s_axi_rready_int_early;
+                    state_next = STATE_DATA;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                // data state; transfer read data
+                m_axi_rready_next = s_axi_rready_int_early;
+
+                if (m_axi_rready && m_axi_rvalid) begin
+                    s_axi_rid_int = id_reg;
+                    s_axi_rdata_int = m_axi_rdata;
+                    s_axi_rresp_int = m_axi_rresp;
+                    s_axi_rlast_int = m_axi_rlast;
+                    s_axi_ruser_int = m_axi_ruser;
+                    s_axi_rvalid_int = 1'b1;
+                    if (m_axi_rlast) begin
+                        // last data word, return to idle
+                        m_axi_rready_next = 1'b0;
+                        s_axi_arready_next = !m_axi_arvalid;
+                        state_next = STATE_IDLE;
+                    end else begin
+                        state_next = STATE_DATA;
+                    end
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+        endcase
+    end else if (EXPAND) begin
+        // master output is wider; split reads
+        s_axi_rid_int = id_reg;
+        s_axi_rdata_int = m_axi_rdata;
+        s_axi_rresp_int = m_axi_rresp;
+        s_axi_rlast_int = m_axi_rlast;
+        s_axi_ruser_int = m_axi_ruser;
+        s_axi_rvalid_int = 0;
+
+        case (state_reg)
+            STATE_IDLE: begin
+                // idle state; wait for new burst
+                s_axi_arready_next = !m_axi_arvalid;
+
+                if (s_axi_arready && s_axi_arvalid) begin
+                    s_axi_arready_next = 1'b0;
+                    id_next = s_axi_arid;
+                    m_axi_arid_next = s_axi_arid;
+                    m_axi_araddr_next = s_axi_araddr;
+                    addr_next = s_axi_araddr;
+                    burst_next = s_axi_arlen;
+                    burst_size_next = s_axi_arsize;
+                    if (CONVERT_BURST && s_axi_arcache[1] && (CONVERT_NARROW_BURST || s_axi_arsize == S_BURST_SIZE)) begin
+                        // split reads
+                        // require CONVERT_BURST and arcache[1] set
+                        master_burst_size_next = M_BURST_SIZE;
+                        if (CONVERT_NARROW_BURST) begin
+                            m_axi_arlen_next = (({{S_ADDR_BIT_OFFSET+1{1'b0}}, s_axi_arlen} << s_axi_arsize) + s_axi_araddr[M_ADDR_BIT_OFFSET-1:0]) >> M_BURST_SIZE;
+                        end else begin
+                            m_axi_arlen_next = ({1'b0, s_axi_arlen} + s_axi_araddr[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]) >> $clog2(SEGMENT_COUNT);
+                        end
+                        m_axi_arsize_next = M_BURST_SIZE;
+                        state_next = STATE_DATA_READ;
+                    end else begin
+                        // output narrow burst
+                        master_burst_size_next = s_axi_arsize;
+                        m_axi_arlen_next = s_axi_arlen;
+                        m_axi_arsize_next = s_axi_arsize;
+                        state_next = STATE_DATA;
+                    end
+                    m_axi_arburst_next = s_axi_arburst;
+                    m_axi_arlock_next = s_axi_arlock;
+                    m_axi_arcache_next = s_axi_arcache;
+                    m_axi_arprot_next = s_axi_arprot;
+                    m_axi_arqos_next = s_axi_arqos;
+                    m_axi_arregion_next = s_axi_arregion;
+                    m_axi_aruser_next = s_axi_aruser;
+                    m_axi_arvalid_next = 1'b1;
+                    m_axi_rready_next = s_axi_rready_int_early;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                m_axi_rready_next = s_axi_rready_int_early;
+
+                if (m_axi_rready && m_axi_rvalid) begin
+                    s_axi_rid_int = id_reg;
+                    s_axi_rdata_int = m_axi_rdata >> (addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET] * S_DATA_WIDTH);
+                    s_axi_rresp_int = m_axi_rresp;
+                    s_axi_rlast_int = m_axi_rlast;
+                    s_axi_ruser_int = m_axi_ruser;
+                    s_axi_rvalid_int = 1'b1;
+                    addr_next = addr_reg + (1 << burst_size_reg);
+                    if (m_axi_rlast) begin
+                        m_axi_rready_next = 1'b0;
+                        s_axi_arready_next = !m_axi_arvalid;
+                        state_next = STATE_IDLE;
+                    end else begin
+                        state_next = STATE_DATA;
+                    end
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+            STATE_DATA_READ: begin
+                m_axi_rready_next = s_axi_rready_int_early;
+
+                if (m_axi_rready && m_axi_rvalid) begin
+                    s_axi_rid_int = id_reg;
+                    data_next = m_axi_rdata;
+                    resp_next = m_axi_rresp;
+                    ruser_next = m_axi_ruser;
+                    s_axi_rdata_int = m_axi_rdata >> (addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET] * S_DATA_WIDTH);
+                    s_axi_rresp_int = m_axi_rresp;
+                    s_axi_rlast_int = 1'b0;
+                    s_axi_ruser_int = m_axi_ruser;
+                    s_axi_rvalid_int = 1'b1;
+                    burst_next = burst_reg - 1;
+                    addr_next = addr_reg + (1 << burst_size_reg);
+                    if (burst_reg == 0) begin
+                        m_axi_rready_next = 1'b0;
+                        s_axi_arready_next = !m_axi_arvalid;
+                        s_axi_rlast_int = 1'b1;
+                        state_next = STATE_IDLE;
+                    end else if (addr_next[master_burst_size_reg] != addr_reg[master_burst_size_reg]) begin
+                        state_next = STATE_DATA_READ;
+                    end else begin
+                        m_axi_rready_next = 1'b0;
+                        state_next = STATE_DATA_SPLIT;
+                    end
+                end else begin
+                    state_next = STATE_DATA_READ;
+                end
+            end
+            STATE_DATA_SPLIT: begin
+                m_axi_rready_next = 1'b0;
+
+                if (s_axi_rready_int_reg) begin
+                    s_axi_rid_int = id_reg;
+                    s_axi_rdata_int = data_reg >> (addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET] * S_DATA_WIDTH);
+                    s_axi_rresp_int = resp_reg;
+                    s_axi_rlast_int = 1'b0;
+                    s_axi_ruser_int = ruser_reg;
+                    s_axi_rvalid_int = 1'b1;
+                    burst_next = burst_reg - 1;
+                    addr_next = addr_reg + (1 << burst_size_reg);
+                    if (burst_reg == 0) begin
+                        s_axi_arready_next = !m_axi_arvalid;
+                        s_axi_rlast_int = 1'b1;
+                        state_next = STATE_IDLE;
+                    end else if (addr_next[master_burst_size_reg] != addr_reg[master_burst_size_reg]) begin
+                        m_axi_rready_next = s_axi_rready_int_early;
+                        state_next = STATE_DATA_READ;
+                    end else begin
+                        state_next = STATE_DATA_SPLIT;
+                    end
+                end else begin
+                    state_next = STATE_DATA_SPLIT;
+                end
+            end
+        endcase
+    end else begin
+        // master output is narrower; merge reads and possibly split burst
+        s_axi_rid_int = id_reg;
+        s_axi_rdata_int = data_reg;
+        s_axi_rresp_int = resp_reg;
+        s_axi_rlast_int = 1'b0;
+        s_axi_ruser_int = m_axi_ruser;
+        s_axi_rvalid_int = 0;
+
+        case (state_reg)
+            STATE_IDLE: begin
+                // idle state; wait for new burst
+                s_axi_arready_next = !m_axi_arvalid;
+
+                resp_next = 2'd0;
+
+                if (s_axi_arready && s_axi_arvalid) begin
+                    s_axi_arready_next = 1'b0;
+                    id_next = s_axi_arid;
+                    m_axi_arid_next = s_axi_arid;
+                    m_axi_araddr_next = s_axi_araddr;
+                    addr_next = s_axi_araddr;
+                    burst_next = s_axi_arlen;
+                    burst_size_next = s_axi_arsize;
+                    if (s_axi_arsize > M_BURST_SIZE) begin
+                        // need to adjust burst size
+                        if (s_axi_arlen >> (8+M_BURST_SIZE-s_axi_arsize) != 0) begin
+                            // limit burst length to max
+                            master_burst_next = (8'd255 << (s_axi_arsize-M_BURST_SIZE)) | ((~s_axi_araddr & (8'hff >> (8-s_axi_arsize))) >> M_BURST_SIZE);
+                        end else begin
+                            master_burst_next = (s_axi_arlen << (s_axi_arsize-M_BURST_SIZE)) | ((~s_axi_araddr & (8'hff >> (8-s_axi_arsize))) >> M_BURST_SIZE);
+                        end
+                        master_burst_size_next = M_BURST_SIZE;
+                        m_axi_arlen_next = master_burst_next;
+                        m_axi_arsize_next = master_burst_size_next;
+                    end else begin
+                        // pass through narrow (enough) burst
+                        master_burst_next = s_axi_arlen;
+                        master_burst_size_next = s_axi_arsize;
+                        m_axi_arlen_next = s_axi_arlen;
+                        m_axi_arsize_next = s_axi_arsize;
+                    end
+                    m_axi_arburst_next = s_axi_arburst;
+                    m_axi_arlock_next = s_axi_arlock;
+                    m_axi_arcache_next = s_axi_arcache;
+                    m_axi_arprot_next = s_axi_arprot;
+                    m_axi_arqos_next = s_axi_arqos;
+                    m_axi_arregion_next = s_axi_arregion;
+                    m_axi_aruser_next = s_axi_aruser;
+                    m_axi_arvalid_next = 1'b1;
+                    m_axi_rready_next = 1'b0;
+                    state_next = STATE_DATA;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                m_axi_rready_next = s_axi_rready_int_early && !m_axi_arvalid;
+
+                if (m_axi_rready && m_axi_rvalid) begin
+                    data_next[addr_reg[S_ADDR_BIT_OFFSET-1:M_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = m_axi_rdata;
+                    if (m_axi_rresp) begin
+                        resp_next = m_axi_rresp;
+                    end
+                    s_axi_rid_int = id_reg;
+                    s_axi_rdata_int = data_next;
+                    s_axi_rresp_int = resp_next;
+                    s_axi_rlast_int = 1'b0;
+                    s_axi_ruser_int = m_axi_ruser;
+                    s_axi_rvalid_int = 1'b0;
+                    master_burst_next = master_burst_reg - 1;
+                    addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_WIDTH{1'b1}} << master_burst_size_reg);
+                    m_axi_araddr_next = addr_next;
+                    if (addr_next[burst_size_reg] != addr_reg[burst_size_reg]) begin
+                        data_next = {DATA_WIDTH{1'b0}};
+                        burst_next = burst_reg - 1;
+                        s_axi_rvalid_int = 1'b1;
+                    end
+                    if (master_burst_reg == 0) begin
+                        if (burst_next >> (8+M_BURST_SIZE-burst_size_reg) != 0) begin
+                            // limit burst length to max
+                            master_burst_next = 8'd255;
+                        end else begin
+                            master_burst_next = (burst_next << (burst_size_reg-M_BURST_SIZE)) | (8'hff >> (8-burst_size_reg) >> M_BURST_SIZE);
+                        end
+                        m_axi_arlen_next = master_burst_next;
+
+                        if (burst_reg == 0) begin
+                            m_axi_rready_next = 1'b0;
+                            s_axi_rlast_int = 1'b1;
+                            s_axi_rvalid_int = 1'b1;
+                            s_axi_arready_next = !m_axi_arvalid;
+                            state_next = STATE_IDLE;
+                        end else begin
+                            // start new burst
+                            m_axi_arvalid_next = 1'b1;
+                            m_axi_rready_next = 1'b0;
+                            state_next = STATE_DATA;
+                        end
+                    end else begin
+                        state_next = STATE_DATA;
+                    end
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+        endcase
+    end
+end
+
+always @(posedge clk) begin
+    state_reg <= state_next;
+
+    id_reg <= id_next;
+    addr_reg <= addr_next;
+    data_reg <= data_next;
+    resp_reg <= resp_next;
+    ruser_reg <= ruser_next;
+    burst_reg <= burst_next;
+    burst_size_reg <= burst_size_next;
+    master_burst_reg <= master_burst_next;
+    master_burst_size_reg <= master_burst_size_next;
+
+    s_axi_arready_reg <= s_axi_arready_next;
+
+    m_axi_arid_reg <= m_axi_arid_next;
+    m_axi_araddr_reg <= m_axi_araddr_next;
+    m_axi_arlen_reg <= m_axi_arlen_next;
+    m_axi_arsize_reg <= m_axi_arsize_next;
+    m_axi_arburst_reg <= m_axi_arburst_next;
+    m_axi_arlock_reg <= m_axi_arlock_next;
+    m_axi_arcache_reg <= m_axi_arcache_next;
+    m_axi_arprot_reg <= m_axi_arprot_next;
+    m_axi_arqos_reg <= m_axi_arqos_next;
+    m_axi_arregion_reg <= m_axi_arregion_next;
+    m_axi_aruser_reg <= m_axi_aruser_next;
+    m_axi_arvalid_reg <= m_axi_arvalid_next;
+    m_axi_rready_reg <= m_axi_rready_next;
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+
+        s_axi_arready_reg <= 1'b0;
+
+        m_axi_arvalid_reg <= 1'b0;
+        m_axi_rready_reg <= 1'b0;
+    end
+end
+
+// output datapath logic
+reg [ID_WIDTH-1:0]     s_axi_rid_reg    = {ID_WIDTH{1'b0}};
+reg [S_DATA_WIDTH-1:0] s_axi_rdata_reg  = {S_DATA_WIDTH{1'b0}};
+reg [1:0]              s_axi_rresp_reg  = 2'd0;
+reg                    s_axi_rlast_reg  = 1'b0;
+reg [RUSER_WIDTH-1:0]  s_axi_ruser_reg  = 1'b0;
+reg                    s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
+
+reg [ID_WIDTH-1:0]     temp_s_axi_rid_reg    = {ID_WIDTH{1'b0}};
+reg [S_DATA_WIDTH-1:0] temp_s_axi_rdata_reg  = {S_DATA_WIDTH{1'b0}};
+reg [1:0]              temp_s_axi_rresp_reg  = 2'd0;
+reg                    temp_s_axi_rlast_reg  = 1'b0;
+reg [RUSER_WIDTH-1:0]  temp_s_axi_ruser_reg  = 1'b0;
+reg                    temp_s_axi_rvalid_reg = 1'b0, temp_s_axi_rvalid_next;
+
+// datapath control
+reg store_axi_r_int_to_output;
+reg store_axi_r_int_to_temp;
+reg store_axi_r_temp_to_output;
+
+assign s_axi_rid    = s_axi_rid_reg;
+assign s_axi_rdata  = s_axi_rdata_reg;
+assign s_axi_rresp  = s_axi_rresp_reg;
+assign s_axi_rlast  = s_axi_rlast_reg;
+assign s_axi_ruser  = RUSER_ENABLE ? s_axi_ruser_reg : {RUSER_WIDTH{1'b0}};
+assign s_axi_rvalid = s_axi_rvalid_reg;
+
+// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+assign s_axi_rready_int_early = s_axi_rready | (~temp_s_axi_rvalid_reg & (~s_axi_rvalid_reg | ~s_axi_rvalid_int));
+
+always @* begin
+    // transfer sink ready state to source
+    s_axi_rvalid_next = s_axi_rvalid_reg;
+    temp_s_axi_rvalid_next = temp_s_axi_rvalid_reg;
+
+    store_axi_r_int_to_output = 1'b0;
+    store_axi_r_int_to_temp = 1'b0;
+    store_axi_r_temp_to_output = 1'b0;
+
+    if (s_axi_rready_int_reg) begin
+        // input is ready
+        if (s_axi_rready | ~s_axi_rvalid_reg) begin
+            // output is ready or currently not valid, transfer data to output
+            s_axi_rvalid_next = s_axi_rvalid_int;
+            store_axi_r_int_to_output = 1'b1;
+        end else begin
+            // output is not ready, store input in temp
+            temp_s_axi_rvalid_next = s_axi_rvalid_int;
+            store_axi_r_int_to_temp = 1'b1;
+        end
+    end else if (s_axi_rready) begin
+        // input is not ready, but output is ready
+        s_axi_rvalid_next = temp_s_axi_rvalid_reg;
+        temp_s_axi_rvalid_next = 1'b0;
+        store_axi_r_temp_to_output = 1'b1;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        s_axi_rvalid_reg <= 1'b0;
+        s_axi_rready_int_reg <= 1'b0;
+        temp_s_axi_rvalid_reg <= 1'b0;
+    end else begin
+        s_axi_rvalid_reg <= s_axi_rvalid_next;
+        s_axi_rready_int_reg <= s_axi_rready_int_early;
+        temp_s_axi_rvalid_reg <= temp_s_axi_rvalid_next;
+    end
+
+    // datapath
+    if (store_axi_r_int_to_output) begin
+        s_axi_rid_reg <= s_axi_rid_int;
+        s_axi_rdata_reg <= s_axi_rdata_int;
+        s_axi_rresp_reg <= s_axi_rresp_int;
+        s_axi_rlast_reg <= s_axi_rlast_int;
+        s_axi_ruser_reg <= s_axi_ruser_int;
+    end else if (store_axi_r_temp_to_output) begin
+        s_axi_rid_reg <= temp_s_axi_rid_reg;
+        s_axi_rdata_reg <= temp_s_axi_rdata_reg;
+        s_axi_rresp_reg <= temp_s_axi_rresp_reg;
+        s_axi_rlast_reg <= temp_s_axi_rlast_reg;
+        s_axi_ruser_reg <= temp_s_axi_ruser_reg;
+    end
+
+    if (store_axi_r_int_to_temp) begin
+        temp_s_axi_rid_reg <= s_axi_rid_int;
+        temp_s_axi_rdata_reg <= s_axi_rdata_int;
+        temp_s_axi_rresp_reg <= s_axi_rresp_int;
+        temp_s_axi_rlast_reg <= s_axi_rlast_int;
+        temp_s_axi_ruser_reg <= s_axi_ruser_int;
+    end
+end
+
+endmodule
+
+`resetall

corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter_wr.v

@@ -0,0 +1,779 @@
+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 width adapter
+ */
+module axi_dw_adapter_wr #
+(
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of input (slave) interface data bus in bits
+    parameter S_DATA_WIDTH = 32,
+    // Width of input (slave) interface wstrb (width of data bus in words)
+    parameter S_STRB_WIDTH = (S_DATA_WIDTH/8),
+    // Width of output (master) interface data bus in bits
+    parameter M_DATA_WIDTH = 32,
+    // Width of output (master) interface wstrb (width of data bus in words)
+    parameter M_STRB_WIDTH = (M_DATA_WIDTH/8),
+    // Width of ID signal
+    parameter ID_WIDTH = 8,
+    // Propagate awuser signal
+    parameter AWUSER_ENABLE = 0,
+    // Width of awuser signal
+    parameter AWUSER_WIDTH = 1,
+    // Propagate wuser signal
+    parameter WUSER_ENABLE = 0,
+    // Width of wuser signal
+    parameter WUSER_WIDTH = 1,
+    // Propagate buser signal
+    parameter BUSER_ENABLE = 0,
+    // Width of buser signal
+    parameter BUSER_WIDTH = 1,
+    // When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible
+    parameter CONVERT_BURST = 1,
+    // When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible
+    parameter CONVERT_NARROW_BURST = 0,
+    // Forward ID through adapter
+    parameter FORWARD_ID = 0
+)
+(
+    input  wire                     clk,
+    input  wire                     rst,
+
+    /*
+     * AXI slave interface
+     */
+    input  wire [ID_WIDTH-1:0]      s_axi_awid,
+    input  wire [ADDR_WIDTH-1:0]    s_axi_awaddr,
+    input  wire [7:0]               s_axi_awlen,
+    input  wire [2:0]               s_axi_awsize,
+    input  wire [1:0]               s_axi_awburst,
+    input  wire                     s_axi_awlock,
+    input  wire [3:0]               s_axi_awcache,
+    input  wire [2:0]               s_axi_awprot,
+    input  wire [3:0]               s_axi_awqos,
+    input  wire [3:0]               s_axi_awregion,
+    input  wire [AWUSER_WIDTH-1:0]  s_axi_awuser,
+    input  wire                     s_axi_awvalid,
+    output wire                     s_axi_awready,
+    input  wire [S_DATA_WIDTH-1:0]  s_axi_wdata,
+    input  wire [S_STRB_WIDTH-1:0]  s_axi_wstrb,
+    input  wire                     s_axi_wlast,
+    input  wire [WUSER_WIDTH-1:0]   s_axi_wuser,
+    input  wire                     s_axi_wvalid,
+    output wire                     s_axi_wready,
+    output wire [ID_WIDTH-1:0]      s_axi_bid,
+    output wire [1:0]               s_axi_bresp,
+    output wire [BUSER_WIDTH-1:0]   s_axi_buser,
+    output wire                     s_axi_bvalid,
+    input  wire                     s_axi_bready,
+
+    /*
+     * AXI master interface
+     */
+    output wire [ID_WIDTH-1:0]      m_axi_awid,
+    output wire [ADDR_WIDTH-1:0]    m_axi_awaddr,
+    output wire [7:0]               m_axi_awlen,
+    output wire [2:0]               m_axi_awsize,
+    output wire [1:0]               m_axi_awburst,
+    output wire                     m_axi_awlock,
+    output wire [3:0]               m_axi_awcache,
+    output wire [2:0]               m_axi_awprot,
+    output wire [3:0]               m_axi_awqos,
+    output wire [3:0]               m_axi_awregion,
+    output wire [AWUSER_WIDTH-1:0]  m_axi_awuser,
+    output wire                     m_axi_awvalid,
+    input  wire                     m_axi_awready,
+    output wire [M_DATA_WIDTH-1:0]  m_axi_wdata,
+    output wire [M_STRB_WIDTH-1:0]  m_axi_wstrb,
+    output wire                     m_axi_wlast,
+    output wire [WUSER_WIDTH-1:0]   m_axi_wuser,
+    output wire                     m_axi_wvalid,
+    input  wire                     m_axi_wready,
+    input  wire [ID_WIDTH-1:0]      m_axi_bid,
+    input  wire [1:0]               m_axi_bresp,
+    input  wire [BUSER_WIDTH-1:0]   m_axi_buser,
+    input  wire                     m_axi_bvalid,
+    output wire                     m_axi_bready
+);
+
+parameter S_ADDR_BIT_OFFSET = $clog2(S_STRB_WIDTH);
+parameter M_ADDR_BIT_OFFSET = $clog2(M_STRB_WIDTH);
+parameter S_WORD_WIDTH = S_STRB_WIDTH;
+parameter M_WORD_WIDTH = M_STRB_WIDTH;
+parameter S_WORD_SIZE = S_DATA_WIDTH/S_WORD_WIDTH;
+parameter M_WORD_SIZE = M_DATA_WIDTH/M_WORD_WIDTH;
+parameter S_BURST_SIZE = $clog2(S_STRB_WIDTH);
+parameter M_BURST_SIZE = $clog2(M_STRB_WIDTH);
+
+// output bus is wider
+parameter EXPAND = M_STRB_WIDTH > S_STRB_WIDTH;
+parameter DATA_WIDTH = EXPAND ? M_DATA_WIDTH : S_DATA_WIDTH;
+parameter STRB_WIDTH = EXPAND ? M_STRB_WIDTH : S_STRB_WIDTH;
+// required number of segments in wider bus
+parameter SEGMENT_COUNT = EXPAND ? (M_STRB_WIDTH / S_STRB_WIDTH) : (S_STRB_WIDTH / M_STRB_WIDTH);
+// data width and keep width per segment
+parameter SEGMENT_DATA_WIDTH = DATA_WIDTH / SEGMENT_COUNT;
+parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT;
+
+// bus width assertions
+initial begin
+    if (S_WORD_SIZE * S_STRB_WIDTH != S_DATA_WIDTH) begin
+        $error("Error: AXI slave interface data width not evenly divisble (instance %m)");
+        $finish;
+    end
+
+    if (M_WORD_SIZE * M_STRB_WIDTH != M_DATA_WIDTH) begin
+        $error("Error: AXI master interface data width not evenly divisble (instance %m)");
+        $finish;
+    end
+
+    if (S_WORD_SIZE != M_WORD_SIZE) begin
+        $error("Error: word size mismatch (instance %m)");
+        $finish;
+    end
+
+    if (2**$clog2(S_WORD_WIDTH) != S_WORD_WIDTH) begin
+        $error("Error: AXI slave interface word width must be even power of two (instance %m)");
+        $finish;
+    end
+
+    if (2**$clog2(M_WORD_WIDTH) != M_WORD_WIDTH) begin
+        $error("Error: AXI master interface word width must be even power of two (instance %m)");
+        $finish;
+    end
+end
+
+localparam [1:0]
+    STATE_IDLE = 2'd0,
+    STATE_DATA = 2'd1,
+    STATE_DATA_2 = 2'd2,
+    STATE_RESP = 2'd3;
+
+reg [1:0] state_reg = STATE_IDLE, state_next;
+
+reg [ID_WIDTH-1:0] id_reg = {ID_WIDTH{1'b0}}, id_next;
+reg [ADDR_WIDTH-1:0] addr_reg = {ADDR_WIDTH{1'b0}}, addr_next;
+reg [DATA_WIDTH-1:0] data_reg = {DATA_WIDTH{1'b0}}, data_next;
+reg [STRB_WIDTH-1:0] strb_reg = {STRB_WIDTH{1'b0}}, strb_next;
+reg [WUSER_WIDTH-1:0] wuser_reg = {WUSER_WIDTH{1'b0}}, wuser_next;
+reg [7:0] burst_reg = 8'd0, burst_next;
+reg [2:0] burst_size_reg = 3'd0, burst_size_next;
+reg [7:0] master_burst_reg = 8'd0, master_burst_next;
+reg [2:0] master_burst_size_reg = 3'd0, master_burst_size_next;
+reg burst_active_reg = 1'b0, burst_active_next;
+reg first_transfer_reg = 1'b0, first_transfer_next;
+
+reg s_axi_awready_reg = 1'b0, s_axi_awready_next;
+reg s_axi_wready_reg = 1'b0, s_axi_wready_next;
+reg [ID_WIDTH-1:0] s_axi_bid_reg = {ID_WIDTH{1'b0}}, s_axi_bid_next;
+reg [1:0] s_axi_bresp_reg = 2'd0, s_axi_bresp_next;
+reg [BUSER_WIDTH-1:0] s_axi_buser_reg = {BUSER_WIDTH{1'b0}}, s_axi_buser_next;
+reg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
+
+reg [ID_WIDTH-1:0] m_axi_awid_reg = {ID_WIDTH{1'b0}}, m_axi_awid_next;
+reg [ADDR_WIDTH-1:0] m_axi_awaddr_reg = {ADDR_WIDTH{1'b0}}, m_axi_awaddr_next;
+reg [7:0] m_axi_awlen_reg = 8'd0, m_axi_awlen_next;
+reg [2:0] m_axi_awsize_reg = 3'd0, m_axi_awsize_next;
+reg [1:0] m_axi_awburst_reg = 2'd0, m_axi_awburst_next;
+reg m_axi_awlock_reg = 1'b0, m_axi_awlock_next;
+reg [3:0] m_axi_awcache_reg = 4'd0, m_axi_awcache_next;
+reg [2:0] m_axi_awprot_reg = 3'd0, m_axi_awprot_next;
+reg [3:0] m_axi_awqos_reg = 4'd0, m_axi_awqos_next;
+reg [3:0] m_axi_awregion_reg = 4'd0, m_axi_awregion_next;
+reg [AWUSER_WIDTH-1:0] m_axi_awuser_reg = {AWUSER_WIDTH{1'b0}}, m_axi_awuser_next;
+reg m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
+reg m_axi_bready_reg = 1'b0, m_axi_bready_next;
+
+// internal datapath
+reg  [M_DATA_WIDTH-1:0] m_axi_wdata_int;
+reg  [M_STRB_WIDTH-1:0] m_axi_wstrb_int;
+reg                     m_axi_wlast_int;
+reg  [WUSER_WIDTH-1:0]  m_axi_wuser_int;
+reg                     m_axi_wvalid_int;
+reg                     m_axi_wready_int_reg = 1'b0;
+wire                    m_axi_wready_int_early;
+
+assign s_axi_awready = s_axi_awready_reg;
+assign s_axi_wready = s_axi_wready_reg;
+assign s_axi_bid = s_axi_bid_reg;
+assign s_axi_bresp = s_axi_bresp_reg;
+assign s_axi_buser = BUSER_ENABLE ? s_axi_buser_reg : {BUSER_WIDTH{1'b0}};
+assign s_axi_bvalid = s_axi_bvalid_reg;
+
+assign m_axi_awid = FORWARD_ID ? m_axi_awid_reg : {ID_WIDTH{1'b0}};
+assign m_axi_awaddr = m_axi_awaddr_reg;
+assign m_axi_awlen = m_axi_awlen_reg;
+assign m_axi_awsize = m_axi_awsize_reg;
+assign m_axi_awburst = m_axi_awburst_reg;
+assign m_axi_awlock = m_axi_awlock_reg;
+assign m_axi_awcache = m_axi_awcache_reg;
+assign m_axi_awprot = m_axi_awprot_reg;
+assign m_axi_awqos = m_axi_awqos_reg;
+assign m_axi_awregion = m_axi_awregion_reg;
+assign m_axi_awuser = AWUSER_ENABLE ? m_axi_awuser_reg : {AWUSER_WIDTH{1'b0}};
+assign m_axi_awvalid = m_axi_awvalid_reg;
+assign m_axi_bready = m_axi_bready_reg;
+
+integer i;
+
+always @* begin
+    state_next = STATE_IDLE;
+
+    id_next = id_reg;
+    addr_next = addr_reg;
+    data_next = data_reg;
+    strb_next = strb_reg;
+    wuser_next = wuser_reg;
+    burst_next = burst_reg;
+    burst_size_next = burst_size_reg;
+    master_burst_next = master_burst_reg;
+    master_burst_size_next = master_burst_size_reg;
+    burst_active_next = burst_active_reg;
+    first_transfer_next = first_transfer_reg;
+
+    s_axi_awready_next = 1'b0;
+    s_axi_wready_next = 1'b0;
+    s_axi_bid_next = s_axi_bid_reg;
+    s_axi_bresp_next = s_axi_bresp_reg;
+    s_axi_buser_next = s_axi_buser_reg;
+    s_axi_bvalid_next = s_axi_bvalid_reg && !s_axi_bready;
+    m_axi_awid_next = m_axi_awid_reg;
+    m_axi_awaddr_next = m_axi_awaddr_reg;
+    m_axi_awlen_next = m_axi_awlen_reg;
+    m_axi_awsize_next = m_axi_awsize_reg;
+    m_axi_awburst_next = m_axi_awburst_reg;
+    m_axi_awlock_next = m_axi_awlock_reg;
+    m_axi_awcache_next = m_axi_awcache_reg;
+    m_axi_awprot_next = m_axi_awprot_reg;
+    m_axi_awqos_next = m_axi_awqos_reg;
+    m_axi_awregion_next = m_axi_awregion_reg;
+    m_axi_awuser_next = m_axi_awuser_reg;
+    m_axi_awvalid_next = m_axi_awvalid_reg && !m_axi_awready;
+    m_axi_bready_next = 1'b0;
+
+    if (SEGMENT_COUNT == 1) begin
+        // master output is same width; direct transfer with no splitting/merging
+        m_axi_wdata_int = s_axi_wdata;
+        m_axi_wstrb_int = s_axi_wstrb;
+        m_axi_wlast_int = s_axi_wlast;
+        m_axi_wuser_int = s_axi_wuser;
+        m_axi_wvalid_int = 1'b0;
+
+        case (state_reg)
+            STATE_IDLE: begin
+                // idle state; wait for new burst
+                s_axi_awready_next = !m_axi_awvalid;
+
+                if (s_axi_awready && s_axi_awvalid) begin
+                    s_axi_awready_next = 1'b0;
+                    id_next = s_axi_awid;
+                    m_axi_awid_next = s_axi_awid;
+                    m_axi_awaddr_next = s_axi_awaddr;
+                    m_axi_awlen_next = s_axi_awlen;
+                    m_axi_awsize_next = s_axi_awsize;
+                    m_axi_awburst_next = s_axi_awburst;
+                    m_axi_awlock_next = s_axi_awlock;
+                    m_axi_awcache_next = s_axi_awcache;
+                    m_axi_awprot_next = s_axi_awprot;
+                    m_axi_awqos_next = s_axi_awqos;
+                    m_axi_awregion_next = s_axi_awregion;
+                    m_axi_awuser_next = s_axi_awuser;
+                    m_axi_awvalid_next = 1'b1;
+                    s_axi_wready_next = m_axi_wready_int_early;
+                    state_next = STATE_DATA;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                // data state; transfer write data
+                s_axi_wready_next = m_axi_wready_int_early;
+
+                if (s_axi_wready && s_axi_wvalid) begin
+                    m_axi_wdata_int = s_axi_wdata;
+                    m_axi_wstrb_int = s_axi_wstrb;
+                    m_axi_wlast_int = s_axi_wlast;
+                    m_axi_wuser_int = s_axi_wuser;
+                    m_axi_wvalid_int = 1'b1;
+                    if (s_axi_wlast) begin
+                        // last data word, wait for response
+                        s_axi_wready_next = 1'b0;
+                        m_axi_bready_next = !s_axi_bvalid;
+                        state_next = STATE_RESP;
+                    end else begin
+                        state_next = STATE_DATA;
+                    end
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+            STATE_RESP: begin
+                // resp state; transfer write response
+                m_axi_bready_next = !s_axi_bvalid;
+
+                if (m_axi_bready && m_axi_bvalid) begin
+                    m_axi_bready_next = 1'b0;
+                    s_axi_bid_next = id_reg;
+                    s_axi_bresp_next = m_axi_bresp;
+                    s_axi_buser_next = m_axi_buser;
+                    s_axi_bvalid_next = 1'b1;
+                    s_axi_awready_next = !m_axi_awvalid;
+                    state_next = STATE_IDLE;
+                end else begin
+                    state_next = STATE_RESP;
+                end
+            end
+        endcase
+    end else if (EXPAND) begin
+        // master output is wider; merge writes
+        m_axi_wdata_int = {(M_WORD_WIDTH/S_WORD_WIDTH){s_axi_wdata}};
+        m_axi_wstrb_int = s_axi_wstrb;
+        m_axi_wlast_int = s_axi_wlast;
+        m_axi_wuser_int = s_axi_wuser;
+        m_axi_wvalid_int = 1'b0;
+
+        case (state_reg)
+            STATE_IDLE: begin
+                // idle state; wait for new burst
+                s_axi_awready_next = !m_axi_awvalid;
+
+                data_next = {DATA_WIDTH{1'b0}};
+                strb_next = {STRB_WIDTH{1'b0}};
+
+                if (s_axi_awready && s_axi_awvalid) begin
+                    s_axi_awready_next = 1'b0;
+                    id_next = s_axi_awid;
+                    m_axi_awid_next = s_axi_awid;
+                    m_axi_awaddr_next = s_axi_awaddr;
+                    addr_next = s_axi_awaddr;
+                    burst_next = s_axi_awlen;
+                    burst_size_next = s_axi_awsize;
+                    if (CONVERT_BURST && s_axi_awcache[1] && (CONVERT_NARROW_BURST || s_axi_awsize == S_BURST_SIZE)) begin
+                        // merge writes
+                        // require CONVERT_BURST and awcache[1] set
+                        master_burst_size_next = M_BURST_SIZE;
+                        if (CONVERT_NARROW_BURST) begin
+                            m_axi_awlen_next = (({{S_ADDR_BIT_OFFSET+1{1'b0}}, s_axi_awlen} << s_axi_awsize) + s_axi_awaddr[M_ADDR_BIT_OFFSET-1:0]) >> M_BURST_SIZE;
+                        end else begin
+                            m_axi_awlen_next = ({1'b0, s_axi_awlen} + s_axi_awaddr[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]) >> $clog2(SEGMENT_COUNT);
+                        end
+                        m_axi_awsize_next = M_BURST_SIZE;
+                        state_next = STATE_DATA_2;
+                    end else begin
+                        // output narrow burst
+                        master_burst_size_next = s_axi_awsize;
+                        m_axi_awlen_next = s_axi_awlen;
+                        m_axi_awsize_next = s_axi_awsize;
+                        state_next = STATE_DATA;
+                    end
+                    m_axi_awburst_next = s_axi_awburst;
+                    m_axi_awlock_next = s_axi_awlock;
+                    m_axi_awcache_next = s_axi_awcache;
+                    m_axi_awprot_next = s_axi_awprot;
+                    m_axi_awqos_next = s_axi_awqos;
+                    m_axi_awregion_next = s_axi_awregion;
+                    m_axi_awuser_next = s_axi_awuser;
+                    m_axi_awvalid_next = 1'b1;
+                    s_axi_wready_next = m_axi_wready_int_early;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                // data state; transfer write data
+                s_axi_wready_next = m_axi_wready_int_early;
+
+                if (s_axi_wready && s_axi_wvalid) begin
+                    m_axi_wdata_int = {(M_WORD_WIDTH/S_WORD_WIDTH){s_axi_wdata}};
+                    m_axi_wstrb_int = s_axi_wstrb << (addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET] * S_STRB_WIDTH);
+                    m_axi_wlast_int = s_axi_wlast;
+                    m_axi_wuser_int = s_axi_wuser;
+                    m_axi_wvalid_int = 1'b1;
+                    addr_next = addr_reg + (1 << burst_size_reg);
+                    if (s_axi_wlast) begin
+                        s_axi_wready_next = 1'b0;
+                        m_axi_bready_next = !s_axi_bvalid;
+                        state_next = STATE_RESP;
+                    end else begin
+                        state_next = STATE_DATA;
+                    end
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+            STATE_DATA_2: begin
+                s_axi_wready_next = m_axi_wready_int_early;
+
+                if (s_axi_wready && s_axi_wvalid) begin
+                    if (CONVERT_NARROW_BURST) begin
+                        for (i = 0; i < S_WORD_WIDTH; i = i + 1) begin
+                            if (s_axi_wstrb[i]) begin
+                                data_next[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH+i*M_WORD_SIZE +: M_WORD_SIZE] = s_axi_wdata[i*M_WORD_SIZE +: M_WORD_SIZE];
+                                strb_next[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]*SEGMENT_STRB_WIDTH+i] = 1'b1;
+                            end
+                        end
+                    end else begin
+                        data_next[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = s_axi_wdata;
+                        strb_next[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]*SEGMENT_STRB_WIDTH +: SEGMENT_STRB_WIDTH] = s_axi_wstrb;
+                    end
+                    m_axi_wdata_int = data_next;
+                    m_axi_wstrb_int = strb_next;
+                    m_axi_wlast_int = s_axi_wlast;
+                    m_axi_wuser_int = s_axi_wuser;
+                    burst_next = burst_reg - 1;
+                    addr_next = addr_reg + (1 << burst_size_reg);
+                    if (addr_next[master_burst_size_reg] != addr_reg[master_burst_size_reg]) begin
+                        data_next = {DATA_WIDTH{1'b0}};
+                        strb_next = {STRB_WIDTH{1'b0}};
+                        m_axi_wvalid_int = 1'b1;
+                    end
+                    if (burst_reg == 0) begin
+                        m_axi_wvalid_int = 1'b1;
+                        s_axi_wready_next = 1'b0;
+                        m_axi_bready_next = !s_axi_bvalid;
+                        state_next = STATE_RESP;
+                    end else begin
+                        state_next = STATE_DATA_2;
+                    end
+                end else begin
+                    state_next = STATE_DATA_2;
+                end
+            end
+            STATE_RESP: begin
+                // resp state; transfer write response
+                m_axi_bready_next = !s_axi_bvalid;
+
+                if (m_axi_bready && m_axi_bvalid) begin
+                    m_axi_bready_next = 1'b0;
+                    s_axi_bid_next = id_reg;
+                    s_axi_bresp_next = m_axi_bresp;
+                    s_axi_buser_next = m_axi_buser;
+                    s_axi_bvalid_next = 1'b1;
+                    s_axi_awready_next = !m_axi_awvalid;
+                    state_next = STATE_IDLE;
+                end else begin
+                    state_next = STATE_RESP;
+                end
+            end
+        endcase
+    end else begin
+        // master output is narrower; split writes, and possibly split burst
+        m_axi_wdata_int = data_reg;
+        m_axi_wstrb_int = strb_reg;
+        m_axi_wlast_int = 1'b0;
+        m_axi_wuser_int = wuser_reg;
+        m_axi_wvalid_int = 1'b0;
+
+        case (state_reg)
+            STATE_IDLE: begin
+                // idle state; wait for new burst
+                s_axi_awready_next = !m_axi_awvalid;
+
+                first_transfer_next = 1'b1;
+
+                if (s_axi_awready && s_axi_awvalid) begin
+                    s_axi_awready_next = 1'b0;
+                    id_next = s_axi_awid;
+                    m_axi_awid_next = s_axi_awid;
+                    m_axi_awaddr_next = s_axi_awaddr;
+                    addr_next = s_axi_awaddr;
+                    burst_next = s_axi_awlen;
+                    burst_size_next = s_axi_awsize;
+                    burst_active_next = 1'b1;
+                    if (s_axi_awsize > M_BURST_SIZE) begin
+                        // need to adjust burst size
+                        if (s_axi_awlen >> (8+M_BURST_SIZE-s_axi_awsize) != 0) begin
+                            // limit burst length to max
+                            master_burst_next = (8'd255 << (s_axi_awsize-M_BURST_SIZE)) | ((~s_axi_awaddr & (8'hff >> (8-s_axi_awsize))) >> M_BURST_SIZE);
+                        end else begin
+                            master_burst_next = (s_axi_awlen << (s_axi_awsize-M_BURST_SIZE)) | ((~s_axi_awaddr & (8'hff >> (8-s_axi_awsize))) >> M_BURST_SIZE);
+                        end
+                        master_burst_size_next = M_BURST_SIZE;
+                        m_axi_awlen_next = master_burst_next;
+                        m_axi_awsize_next = master_burst_size_next;
+                    end else begin
+                        // pass through narrow (enough) burst
+                        master_burst_next = s_axi_awlen;
+                        master_burst_size_next = s_axi_awsize;
+                        m_axi_awlen_next = s_axi_awlen;
+                        m_axi_awsize_next = s_axi_awsize;
+                    end
+                    m_axi_awburst_next = s_axi_awburst;
+                    m_axi_awlock_next = s_axi_awlock;
+                    m_axi_awcache_next = s_axi_awcache;
+                    m_axi_awprot_next = s_axi_awprot;
+                    m_axi_awqos_next = s_axi_awqos;
+                    m_axi_awregion_next = s_axi_awregion;
+                    m_axi_awuser_next = s_axi_awuser;
+                    m_axi_awvalid_next = 1'b1;
+                    s_axi_wready_next = m_axi_wready_int_early;
+                    state_next = STATE_DATA;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                s_axi_wready_next = m_axi_wready_int_early;
+
+                if (s_axi_wready && s_axi_wvalid) begin
+                    data_next = s_axi_wdata;
+                    strb_next = s_axi_wstrb;
+                    wuser_next = s_axi_wuser;
+                    m_axi_wdata_int = s_axi_wdata >> (addr_reg[S_ADDR_BIT_OFFSET-1:M_ADDR_BIT_OFFSET] * M_DATA_WIDTH);
+                    m_axi_wstrb_int = s_axi_wstrb >> (addr_reg[S_ADDR_BIT_OFFSET-1:M_ADDR_BIT_OFFSET] * M_STRB_WIDTH);
+                    m_axi_wlast_int = 1'b0;
+                    m_axi_wuser_int = s_axi_wuser;
+                    m_axi_wvalid_int = 1'b1;
+                    burst_next = burst_reg - 1;
+                    burst_active_next = burst_reg != 0;
+                    master_burst_next = master_burst_reg - 1;
+                    addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_WIDTH{1'b1}} << master_burst_size_reg);
+                    if (master_burst_reg == 0) begin
+                        s_axi_wready_next = 1'b0;
+                        m_axi_bready_next = !s_axi_bvalid && !s_axi_awvalid;
+                        m_axi_wlast_int = 1'b1;
+                        state_next = STATE_RESP;
+                    end else if (addr_next[burst_size_reg] != addr_reg[burst_size_reg]) begin
+                        state_next = STATE_DATA;
+                    end else begin
+                        s_axi_wready_next = 1'b0;
+                        state_next = STATE_DATA_2;
+                    end
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+            STATE_DATA_2: begin
+                s_axi_wready_next = 1'b0;
+
+                if (m_axi_wready_int_reg) begin
+                    m_axi_wdata_int = data_reg >> (addr_reg[S_ADDR_BIT_OFFSET-1:M_ADDR_BIT_OFFSET] * M_DATA_WIDTH);
+                    m_axi_wstrb_int = strb_reg >> (addr_reg[S_ADDR_BIT_OFFSET-1:M_ADDR_BIT_OFFSET] * M_STRB_WIDTH);
+                    m_axi_wlast_int = 1'b0;
+                    m_axi_wuser_int = wuser_reg;
+                    m_axi_wvalid_int = 1'b1;
+                    master_burst_next = master_burst_reg - 1;
+                    addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_WIDTH{1'b1}} << master_burst_size_reg);
+                    if (master_burst_reg == 0) begin
+                        // burst on master interface finished; transfer response
+                        s_axi_wready_next = 1'b0;
+                        m_axi_bready_next = !s_axi_bvalid && !m_axi_awvalid;
+                        m_axi_wlast_int = 1'b1;
+                        state_next = STATE_RESP;
+                    end else if (addr_next[burst_size_reg] != addr_reg[burst_size_reg]) begin
+                        state_next = STATE_DATA;
+                    end else begin
+                        s_axi_wready_next = 1'b0;
+                        state_next = STATE_DATA_2;
+                    end
+                end else begin
+                    state_next = STATE_DATA_2;
+                end
+            end
+            STATE_RESP: begin
+                // resp state; transfer write response
+                m_axi_bready_next = !s_axi_bvalid && !m_axi_awvalid;
+
+                if (m_axi_bready && m_axi_bvalid) begin
+                    first_transfer_next = 1'b0;
+                    m_axi_bready_next = 1'b0;
+                    s_axi_bid_next = id_reg;
+                    if (first_transfer_reg || m_axi_bresp != 0) begin
+                        s_axi_bresp_next = m_axi_bresp;
+                    end
+
+                    if (burst_reg >> (8+M_BURST_SIZE-burst_size_reg) != 0) begin
+                        // limit burst length to max
+                        master_burst_next = 8'd255;
+                    end else begin
+                        master_burst_next = (burst_reg << (burst_size_reg-M_BURST_SIZE)) | (8'hff >> (8-burst_size_reg) >> M_BURST_SIZE);
+                    end
+                    master_burst_size_next = M_BURST_SIZE;
+                    m_axi_awaddr_next = addr_reg;
+                    m_axi_awlen_next = master_burst_next;
+                    m_axi_awsize_next = master_burst_size_next;
+                    if (burst_active_reg) begin
+                        // burst on slave interface still active; start new burst
+                        m_axi_awvalid_next = 1'b1;
+                        state_next = STATE_DATA;
+                    end else begin
+                        // burst on slave interface finished; return to idle
+                        s_axi_bvalid_next = 1'b1;
+                        s_axi_awready_next = !m_axi_awvalid;
+                        state_next = STATE_IDLE;
+                    end
+                end else begin
+                    state_next = STATE_RESP;
+                end
+            end
+        endcase
+    end
+end
+
+always @(posedge clk) begin
+    state_reg <= state_next;
+
+    id_reg <= id_next;
+    addr_reg <= addr_next;
+    data_reg <= data_next;
+    strb_reg <= strb_next;
+    wuser_reg <= wuser_next;
+    burst_reg <= burst_next;
+    burst_size_reg <= burst_size_next;
+    master_burst_reg <= master_burst_next;
+    master_burst_size_reg <= master_burst_size_next;
+    burst_active_reg <= burst_active_next;
+    first_transfer_reg <= first_transfer_next;
+
+    s_axi_awready_reg <= s_axi_awready_next;
+    s_axi_wready_reg <= s_axi_wready_next;
+    s_axi_bid_reg <= s_axi_bid_next;
+    s_axi_bresp_reg <= s_axi_bresp_next;
+    s_axi_buser_reg <= s_axi_buser_next;
+    s_axi_bvalid_reg <= s_axi_bvalid_next;
+
+    m_axi_awid_reg <= m_axi_awid_next;
+    m_axi_awaddr_reg <= m_axi_awaddr_next;
+    m_axi_awlen_reg <= m_axi_awlen_next;
+    m_axi_awsize_reg <= m_axi_awsize_next;
+    m_axi_awburst_reg <= m_axi_awburst_next;
+    m_axi_awlock_reg <= m_axi_awlock_next;
+    m_axi_awcache_reg <= m_axi_awcache_next;
+    m_axi_awprot_reg <= m_axi_awprot_next;
+    m_axi_awqos_reg <= m_axi_awqos_next;
+    m_axi_awregion_reg <= m_axi_awregion_next;
+    m_axi_awuser_reg <= m_axi_awuser_next;
+    m_axi_awvalid_reg <= m_axi_awvalid_next;
+    m_axi_bready_reg <= m_axi_bready_next;
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+
+        s_axi_awready_reg <= 1'b0;
+        s_axi_wready_reg <= 1'b0;
+        s_axi_bvalid_reg <= 1'b0;
+
+        m_axi_awvalid_reg <= 1'b0;
+        m_axi_bready_reg <= 1'b0;
+    end
+end
+
+// output datapath logic
+reg [M_DATA_WIDTH-1:0] m_axi_wdata_reg  = {M_DATA_WIDTH{1'b0}};
+reg [M_STRB_WIDTH-1:0] m_axi_wstrb_reg  = {M_STRB_WIDTH{1'b0}};
+reg                    m_axi_wlast_reg  = 1'b0;
+reg [WUSER_WIDTH-1:0]  m_axi_wuser_reg  = 1'b0;
+reg                    m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
+
+reg [M_DATA_WIDTH-1:0] temp_m_axi_wdata_reg  = {M_DATA_WIDTH{1'b0}};
+reg [M_STRB_WIDTH-1:0] temp_m_axi_wstrb_reg  = {M_STRB_WIDTH{1'b0}};
+reg                    temp_m_axi_wlast_reg  = 1'b0;
+reg [WUSER_WIDTH-1:0]  temp_m_axi_wuser_reg  = 1'b0;
+reg                    temp_m_axi_wvalid_reg = 1'b0, temp_m_axi_wvalid_next;
+
+// datapath control
+reg store_axi_w_int_to_output;
+reg store_axi_w_int_to_temp;
+reg store_axi_w_temp_to_output;
+
+assign m_axi_wdata  = m_axi_wdata_reg;
+assign m_axi_wstrb  = m_axi_wstrb_reg;
+assign m_axi_wlast  = m_axi_wlast_reg;
+assign m_axi_wuser  = WUSER_ENABLE ? m_axi_wuser_reg : {WUSER_WIDTH{1'b0}};
+assign m_axi_wvalid = m_axi_wvalid_reg;
+
+// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+assign m_axi_wready_int_early = m_axi_wready | (~temp_m_axi_wvalid_reg & (~m_axi_wvalid_reg | ~m_axi_wvalid_int));
+
+always @* begin
+    // transfer sink ready state to source
+    m_axi_wvalid_next = m_axi_wvalid_reg;
+    temp_m_axi_wvalid_next = temp_m_axi_wvalid_reg;
+
+    store_axi_w_int_to_output = 1'b0;
+    store_axi_w_int_to_temp = 1'b0;
+    store_axi_w_temp_to_output = 1'b0;
+
+    if (m_axi_wready_int_reg) begin
+        // input is ready
+        if (m_axi_wready | ~m_axi_wvalid_reg) begin
+            // output is ready or currently not valid, transfer data to output
+            m_axi_wvalid_next = m_axi_wvalid_int;
+            store_axi_w_int_to_output = 1'b1;
+        end else begin
+            // output is not ready, store input in temp
+            temp_m_axi_wvalid_next = m_axi_wvalid_int;
+            store_axi_w_int_to_temp = 1'b1;
+        end
+    end else if (m_axi_wready) begin
+        // input is not ready, but output is ready
+        m_axi_wvalid_next = temp_m_axi_wvalid_reg;
+        temp_m_axi_wvalid_next = 1'b0;
+        store_axi_w_temp_to_output = 1'b1;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        m_axi_wvalid_reg <= 1'b0;
+        m_axi_wready_int_reg <= 1'b0;
+        temp_m_axi_wvalid_reg <= 1'b0;
+    end else begin
+        m_axi_wvalid_reg <= m_axi_wvalid_next;
+        m_axi_wready_int_reg <= m_axi_wready_int_early;
+        temp_m_axi_wvalid_reg <= temp_m_axi_wvalid_next;
+    end
+
+    // datapath
+    if (store_axi_w_int_to_output) begin
+        m_axi_wdata_reg <= m_axi_wdata_int;
+        m_axi_wstrb_reg <= m_axi_wstrb_int;
+        m_axi_wlast_reg <= m_axi_wlast_int;
+        m_axi_wuser_reg <= m_axi_wuser_int;
+    end else if (store_axi_w_temp_to_output) begin
+        m_axi_wdata_reg <= temp_m_axi_wdata_reg;
+        m_axi_wstrb_reg <= temp_m_axi_wstrb_reg;
+        m_axi_wlast_reg <= temp_m_axi_wlast_reg;
+        m_axi_wuser_reg <= temp_m_axi_wuser_reg;
+    end
+
+    if (store_axi_w_int_to_temp) begin
+        temp_m_axi_wdata_reg <= m_axi_wdata_int;
+        temp_m_axi_wstrb_reg <= m_axi_wstrb_int;
+        temp_m_axi_wlast_reg <= m_axi_wlast_int;
+        temp_m_axi_wuser_reg <= m_axi_wuser_int;
+    end
+end
+
+endmodule
+
+`resetall

corev_apu/fpga/src/gpio

@@ -0,0 +1 @@
+Subproject commit 7f5e7b50a3d275fcbdae156ed14b7236ad5d7c0b