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Revise interrupt enable section in mstatus

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This commit is contained in:
Florian Zaruba 2017-07-14 17:31:35 +02:00
parent e37c3f4cd6
commit f90da323f1
1 changed files with 10 additions and 10 deletions
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20
src/csr_regfile.sv
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@ -227,7 +227,7 @@ module csr_regfile #(
en_ld_st_translation_n = en_ld_st_translation_q;
// check for correct access rights and that we are writing
if(csr_we) begin
if (csr_we) begin
case (csr_addr.address)
// sstatus is a subset of mstatus - mask it accordingly
CSR_SSTATUS: begin
@ -270,15 +270,15 @@ module csr_regfile #(
mstatus_n.fs = 2'b0;
mstatus_n.upie = 1'b0;
mstatus_n.uie = 1'b0;
// if the SIE was set also set the MIE, as interrupts for
// higher privilege levels are always set, 1.10 p.20
if (csr_wdata[1])
mstatus_n.mie = 1'b1;
// if the MIE was cleared, also clear SIE since interrupts
// for lower privilege levels are always disabled, 1.10 p.20
if (!csr_wdata[3])
mstatus_n.sie = 1'b0;
// this register has side-effects on other registers, flush the pipeline
// // if the SIE was set also set the MIE, as interrupts for
// // higher privilege levels are always set, 1.10 p.20
// if (csr_wdata[1])
// mstatus_n.mie = 1'b1;
// // if the MIE was cleared, also clear SIE since interrupts
// // for lower privilege levels are always disabled, 1.10 p.20
// if (!csr_wdata[3])
// mstatus_n.sie = 1'b0;
// // this register has side-effects on other registers, flush the pipeline
flush_o = 1'b1;
end
// MISA is WARL (Write Any Value, Reads Legal Value)