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Makefile : Add target to generate functional coverage using verdi tool (#2755)
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Co-authored-by: André Sintzoff <61976467+ASintzoff@users.noreply.github.com>
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Jalali 2025-01-31 13:13:36 +00:00 • committed by GitHub
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verif/sim/Makefile
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@ -382,6 +382,9 @@ questa-uvm:
generate_cov_dash:
urg -warn none -hvp_proj cva6_embedded -format both -group instcov_for_score -hvp_attributes weight+description+Comment -dir vcs_results/default/vcs.d/simv.vdb -plan cva6.hvp -tgl portsonly
generate_verdi_cov:
-verdi -cov -format both -group instcov_for_score -covdir vcs_results/default/vcs.d/simv.vdb -plan cva6.hvp -tgl portsonly
vcs_clean_all:
@echo "[VCS] Cleanup (entire vcs_work dir)"
rm -rf $(CVA6_REPO_DIR)/verif/sim/vcs_results/ verdiLog/ simv* *.daidir *.vpd *.fsdb *.db csrc ucli.key vc_hdrs.h novas* inter.fsdb uart