Merge branch 'master' into dashboardNotifWait

docs/07_cv32a60x/index.rst

@@ -0,0 +1,8 @@
+CV32A60X documentation
+======================
+
+.. toctree::
+   :maxdepth: 1
+
+   riscv/unpriv.rst
+   riscv/priv.rst

docs/07_cv32a60x/riscv/Makefile

@@ -0,0 +1,10 @@
+#   Copyright 2025 Thales DIS France SAS
+#   Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
+#   you may not use this file except in compliance with the License.
+#   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+#   You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+#   Original Author: André Sintzoff - Thales DIS
+
+CONFIG := cv32a60x
+include ../../riscv-isa/build.mk

docs/07_cv32a60x/riscv/priv.rst

@@ -0,0 +1,14 @@
+..
+   Copyright (c) 2025 Thales DIS France SAS
+   Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+   You may obtain a copy of the License at https://solderpad.org/licenses/
+
+   Original Author: André Sintzoff - Thales DIS
+
+Privileged RISC-V ISA
+=====================
+
+.. raw:: html
+   :file: priv-isa-cv32a60x.html

docs/07_cv32a60x/riscv/unpriv.rst

@@ -0,0 +1,14 @@
+..
+   Copyright (c) 2025 Thales DIS France SAS
+   Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+   You may obtain a copy of the License at https://solderpad.org/licenses/
+
+   Original Author: André Sintzoff - Thales DIS
+
+Unprivileged RISC-V ISA
+=======================
+
+.. raw:: html
+   :file: unpriv-isa-cv32a60x.html

docs/common/config_define.adoc

@@ -1,12 +1,21 @@
 
+ifeval::["{ohg-config}"=="CV32A60X"]
+:archi-CVA6:
+:archi-CV32A60X:
+// specify that it is a custom architecture
+:archi-not-default:
+endif::[]
+
 ifeval::["{ohg-config}"=="CV32A65X"]
 :archi-CVA6:
+:archi-CV32A65X:
 // specify that it is a custom architecture
 :archi-not-default:
 endif::[]
 
 ifeval::["{ohg-config}"=="CV64A6_MMU"]
 :archi-CVA6:
+:archi-CV64A6_MMU:
 // specify that it is a custom architecture
 :archi-not-default:
 endif::[]

docs/index.rst

@@ -69,5 +69,6 @@ The :doc:`CVA6 APU <05_cva6_apu/index>` describes an Application Processor Unit
    01_cva6_user/index.rst
    03_cva6_design/index.rst
    04_cv32a65x/index.rst
+   07_cv32a60x/index.rst
    06_cv64a6_mmu/index.rst
    05_cva6_apu/index.rst

docs/riscv-isa/src/machine.adoc

@@ -398,7 +398,7 @@ field is not implemented. The Implementation value should reflect the
 design of the RISC-V processor itself and not any surrounding system.
 endif::[]
 
-ifeval::["{ohg-config}" == "CV32A65X"]
+ifdef::archi-CV32A60X,archi-CV32A65X[]
 The `mimpid` CSR provides a unique encoding of the version of the
 processor implementation.
 
@@ -508,7 +508,7 @@ For RV32 only, `mstatush` is a 32-bit read/write register formatted as
 shown in <<mstatushreg>>. Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`.
 endif::[]
 
-ifeval::["{ohg-config}" == "CV32A65X"]
+ifdef::archi-CV32A60X,archi-CV32A65X[]
 [{ohg-config}] `mstatush` is a 32-bit read/write register formatted as
 shown in <<mstatushreg>>.
 endif::[]
@@ -1249,7 +1249,7 @@ different encoding than XS.
 ====
 endif::[]
 
-ifeval::["{ohg-config}" == "CV32A65X"]
+ifdef::archi-CV32A60X,archi-CV32A65X[]
 [{ohg-config}] The FS[1:0] and VS[1:0] *WARL* fields and the XS[1:0] read-only field are used
 to reduce the cost of context save and restore by setting and tracking
 the current state of the floating-point unit and any other user-mode
@@ -2115,7 +2115,7 @@ ifdef::archi-CVA6[]
 As the Sscofpmf extension is not implemented, `mip`.LCOFIP and `mie`.LCOFIE are read-only zeros.
 endif::[]
 
-ifeval::["{ohg-config}" == "CV32A65X"]
+ifdef::archi-CV32A60X,archi-CV32A65X[]
 [{ohg-config}]
 Multiple simultaneous interrupts destined for M-mode are handled in the
 following decreasing priority order: MEI, MSI, MTI.
@@ -2218,7 +2218,7 @@ As XLEN=64, `mcycleh`, `minstreth`, and `mhpmcounter__n__h`
 do not exist.
 endif::[]
 
-ifeval::["{ohg-config}" == "CV32A65X"]
+ifdef::archi-CV32A60X,archi-CV32A65X[]
 As the Sscofpmf extension is not implemented, the `mhpmevent__n__h` CSRs
 are not provided.
 endif::[]
@@ -3509,7 +3509,7 @@ As "{ohg-config}" does not distinguished different reset conditions,
 The `mcause` returns 0 after reset.
 endif::[]
 
-ifeval::["{ohg-config}" == "CV32A65X"]
+ifdef::archi-CV32A60X,archi-CV32A65X[]
 [{ohg-config}] Privilege mode is always M.
 As little-endian memory accesses are supported,
 the `mstatus`/`mstatush` field MBE is reset to 0.
@@ -4068,6 +4068,13 @@ endif::[]
 [[pmp]]
 === Physical Memory Protection
 
+ifeval::[{NrPMPEntries} == 0]
+[{ohg-config}] There is no optional physical memory protection (PMP)
+unit.
+endif::[]
+
+ifeval::[{NrPMPEntries} != 0]
+
 To support secure processing and contain faults, it is desirable to
 limit the physical addresses accessible by software running on a hart.
 An optional physical memory protection (PMP) unit provides per-hart
@@ -4491,3 +4498,5 @@ ifeval::["{ohg-config}" == "CV32A65X"]
 [{ohg-config}] As page-based virtual memory systems is not implemented, memory accesses
 check the PMP settings synchronously.
 endif::[]
+
+endif::[]

docs/riscv-isa/src/mm-formal.adoc

@@ -2,6 +2,6 @@
 == Formal Memory Model Specifications, Version 0.1
 [[mm-formal]]
 
-ifeval::["{ohg-config}" == "CV32A65X"]
+ifdef::archi-CV32A60X,archi-CV32A65X[]
 {ohg-config}: No RVWMO memory model.
 endif::[]

docs/riscv-isa/src/rv-32-64g.adoc

@@ -16,6 +16,39 @@ ifdef::archi-CVA6[]
 listings for {ohg-config}.
 endif::[]
 
+ifeval::[{RVA} == true]
+:AMO: AMO
+endif::[]
+ifeval::[{RVA} == false]
+:AMO: not used
+endif::[]
+ifeval::[{RVF} == true]
+:LOAD-FP: LOAD-FP
+:STORE-FP: STORE-FP
+:MADD: MADD
+:MSUB: MSUB
+:NMSUB: NMSUB
+:NMADD: NMADD
+:OP-FP: OP-FP
+endif::[]
+ifeval::[{RVF} == false]
+:LOAD-FP: _not-used_
+:STORE-FP: not used
+:MADD: not used
+:MSUB: not used
+:NMSUB: not used
+:NMADD: not used
+:OP-FP: not used
+endif::[]
+ifeval::[{RVV} == true]
+:OP-V: OP-V
+:OP-VE: OP-VE
+endif::[]
+ifeval::[{RVV} == false]
+:OP-V: not used
+:OP-VE: not used
+endif::[]
+
 // note: ≥ is unicode for >=
 [[opcodemap]]
 .RISC-V base opcode map, inst[1:0]=11
@@ -23,10 +56,10 @@ endif::[]
 |===
 |inst[4:2] .2+|000 .2+|001   .2+|010     .2+|011   .2+|100 .2+|101     .2+|110          .2+|111 (>32b)
 |inst[6:5]
-|00           |LOAD   |LOAD-FP  |_custom-0_ |MISC-MEM |OP-IMM |AUIPC      |OP-IMM-32       |48b
-|01           |STORE  |STORE-FP |_custom-1_ |AMO      |OP     |LUI        |OP-32           |64b
-|10           |MADD   |MSUB     |NMSUB      |NMADD    |OP-FP  |OP-V       |_custom-2/rv128_|48b
-|11           |BRANCH |JALR     |_reserved_ |JAL      |SYSTEM |OP-VE      |_custom-3/rv128_|≥80b
+|00           |LOAD   |{LOAD-FP}|_custom-0_ |MISC-MEM |OP-IMM |AUIPC      |OP-IMM-32       |48b
+|01           |STORE  |{STORE-FP}|_custom-1_|{AMO}    |OP     |LUI        |OP-32           |64b
+|10           |{MADD} |{MSUB}   |{NMSUB}    |{NMADD}  |{OP-FP}|{OP-V}     |_custom-2/rv128_|48b
+|11           |BRANCH |JALR     |_reserved_ |JAL      |SYSTEM |{OP-VE}    |_custom-3/rv128_|≥80b
 |===
 
 <<opcodemap>> shows a map of the major opcodes for

docs/riscv-isa/src/zimop.adoc

@@ -7,6 +7,6 @@ endif::[]
 
 === "Zcmop" Compressed May-Be-Operations Extension, Version 1.0
 
-ifeval::[{RVZimop} == false]
+ifeval::[{RVZcmop} == false]
 {ohg-config}: This extension is not supported.
 endif::[]

docs/scripts/spec_builder.py

@@ -51,14 +51,24 @@ DEFAULT_PARAMS = {
     'RVZabha': False,
     'RVZacas': False,
     'RVZawrs': False,
+    'RVZcmop': False,
     'RVZfa': False,
     'RVZfbf-RZvfbf': False,
     'RVZfh': False,
     'RVZfinx': False,
     'RVZicbo': False,
     'RVZicfilp': False,
+    'RVZifencei': False,
+    'RVZihintntl': False,
+    'RVZihintpause': False,
+    'RVZimop': False,
+    'RVZk': False,
     'RVZpm': False,
+    'RVZsmcdeleg': False,
+    'RVZsmcntrpmf': False,
+    'RVZsmcsrind-RVZsscsrind': False,
     'RVZsmctr': False,
+    'RVZsmdbltrp': False,
     'RVZsmepmp': False,
     'RVZsmmpm': False,
     'RVZsmrnmi': False,