mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-19 11:54:46 -04:00
e197b445fc
* Add top hierarchy modification and rs3 for general purpose register file * CVA6 core modifications to enable CoreV-eXtension-Interface feature * Addition of an example coprocessor to use with CoreV-eXtension-Interface functionnalities on CVA6 * CoreV-eXtension-Interface available for FPGA * Add work directories to gitignore * Flist: fix cvxif files * CVXIF: Modification and bugfix for cvxif feature * CVXIF: simplify destination register feature * Make 3rd read port on regfile configurable * example_copro: use fifo_v3 instead of stream_fifo * Makefile: compilation copro using defines * ariane_pkg,riscv_pkg: add parameter to en/disable cvxif * cva6.sv, ariane.sv: add hierarchy between ariane and cva6 * Clean Up code and typo * CVXIF: moved combinatorial part to cvxif_fu module in ex_stage * instr_decoder: rename instr predecoder and package * Clean Up code and typo * cvxif modification to follow style guideline * issue_read_operands.sv: fix always_ff block for cvxif functionnal uni
42 lines
496 B
Text
42 lines
496 B
Text
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covhtmlreport/*
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work/*
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work-ver/*
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corev_apu/fpga/work-fpga
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corev_apu/fpga/ariane.xpr
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corev_apu/fpga/ariane.cache/
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corev_apu/fpga/ariane.hw/
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corev_apu/fpga/.Xil/
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stdout/
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tb/riscv-isa-sim/
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install/
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